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amd geode? lx processors data book amd geode? lx processors data book february 2009 publication id: 33234h
2 amd geode? lx processors data book ? 2009 advanced micro devices, inc. all rights reserved. the contents of this document are pr ovided in connection with advanced micro devices, inc. (?amd?) products. amd make s no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to s pecifications and produ ct descriptions at any time without notice. no license, whet her express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of mer- chantability, fitness for a particular purpose, or infringement of any intellectual property right. amd?s products are not designed, intend ed, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd?s product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. contacts www.amd.com trademarks amd, the amd arrow logo, amd athl on, geode, geodelink, 3dnow!, and combinations thereof, are trademarks of advanced micro devices, inc. linux is a registered trademark of linus torvalds. winbench is a registered trademark of ziff davis, inc. windows is a registered trademark of microsoft corporat ion in the united states and/or other jurisdictions. pentium is a registered trademark and mmx is a trademark of intel corporation in the united states and/or other jurisdictions. other product names used in this publication are for identific ation purposes only and may be trademarks of their respective companies.
amd geode? lx processors data book 3 contents 33234h contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.0 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 cpu core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 geodelink? control processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.3 geodelink? interface units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 geodelink? memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 graphics processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6 display controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7 video processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.8 video input port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9 geodelink? pci bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.10 security block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.0 signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 bootstrap options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 ball assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.0 geodelink? interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1 msr set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 gliu register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.0 cpu core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.1 core processor initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.2 instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.3 application register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.4 system register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.5 cpu core register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
4 amd geode? lx processors data book contents 33234h 6.0 integrated functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 6.1 geodelink? memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 0 6.2 geodelink? memory controller register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 6.3 graphics processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 6.4 graphics processor register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 6.5 display controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 6.6 display controller register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 0 6.7 video processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 6.8 video processor register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 6.9 video input port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 6.10 video input port register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 6.11 security block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 6.12 security block register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 6.13 geodelink? control processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 6.14 geodelink? control processor register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 6.15 geodelink? pci bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 6.16 geodelink? pci bridge register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 7.0 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 7.1 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 7.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 7.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 7.4 dc current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 7.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 7.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 8.0 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 8.1 general instruction set format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 8.2 cpuid instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 8.3 processor core instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 8.4 mmx?, fpu, and amd 3dnow!? technology instructions sets . . . . . . . . . . . . . . . . . . . . . . 658 9.0 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 9.1 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 appendix a support documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 a.1 order information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 a.2 data book revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
amd geode? lx processors data book 5 list of figures 33234h list of figures figure 1-1. internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3-1. signal groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 3-2. bgu481 ball assignment diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 4-1. geodelink? architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 6-1. integrated functions block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 figure 6-2. glmc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 figure 6-3. hoi addressing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 6-4. hoi example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 6-5. loi addressing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 6-6. loi example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 6-7. request pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 figure 6-8. ddr reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 figure 6-9. ddr writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 figure 6-10. graphics processor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 6-11. 14-bit repeated pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 figure 6-12. display controller high-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 78 figure 6-13. gui block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 figure 6-14. vga block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 figure 6-15. vga frame buffer organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 figure 6-16. graphics controller high-level diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 figure 6-17. write mode data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 figure 6-18. read mode data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 figure 6-19. color compare operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 figure 6-20. graphics filter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 figure 6-21. flicker filter and line buffer path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 figure 6-22. interlaced timing settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 figure 6-23. video processor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 figure 6-24. video processor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 figure 6-25. downscaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 figure 6-26. linear interpolation calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 figure 6-27. mixer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 figure 6-28. color key and alpha-blending logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 figure 6-29. vop internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 figure 6-30. 525-line ntsc video window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 figure 6-31. hblank and vblank for lines 20-262, 283-524 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 figure 6-32. hblank and vblank for lines 263, 525 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 figure 6-33. hblank and vblank for lines 1-18, 264-281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 figure 6-34. hblank and vblank for lines 19, 282 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 0 figure 6-35. bt.656 8/16 bit line data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 figure 6-36. flat panel display controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 figure 6-37. dithered 8x8 pixel pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 figure 6-38. n-bit dithering pattern schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 figure 6-39. vip block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 figure 6-40. bt.656, 8/16-bit line data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 figure 6-41. 525 line, 60 hz digital vertical timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
6 amd geode? lx processors data book list of figures 33234h figure 6-42. ancillary data packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 figure 6-43. message passing data packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 figure 6-44. data streaming data packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 figure 6-45. bt.601 mode default field detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 figure 6-46. bt.601 mode programmable field detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 figure 6-47. bt.601 mode horizontal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 figure 6-48. bt.601 mode vertical timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 figure 6-49. yuv 4:2:2 to yuv 4:2:0 translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 figure 6-50. dual buffer for message passing and data streaming modes . . . . . . . . . . . . . . . . . . . . . . 476 figure 6-51. example vip yuv 4:2:2 sav/ eav packets stored in system me mory in a linear buffer . 477 figure 6-52. example vip yuv 4:2:0 planar buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 figure 6-53. example vip 8/16- and 10-bit ancillary packet s stored in system memory . . . . . . . . . . . . 479 figure 6-54. security block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 figure 6-55. glcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 figure 6-56. processor clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 figure 6-57. gio interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 figure 6-58. glpci block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 figure 6-59. atomic msr accesses across the pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 figure 6-60. simple round-robin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 figure 6-61. weighted round-robin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 figure 7-1. vmemlx power split . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 figure 7-2. drive level and measurement points for switching characteristics . . . . . . . . . . . . . . . . . . 607 figure 7-3. drive level and measurement points for switching characteristics . . . . . . . . . . . . . . . . . . 608 figure 7-4. power up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 figure 7-5. drive level and measurement points for switching characteristics . . . . . . . . . . . . . . . . . . 609 figure 7-6. drive level and measurement points for switching characteristics . . . . . . . . . . . . . . . . . . 610 figure 7-7. drive level and measurement points for switching characteristics . . . . . . . . . . . . . . . . . . 611 figure 7-8. ddr write timing measurement points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5 figure 7-9. ddr read timing measurement points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 figure 9-1. bgu481 top/side view/dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 75 figure 9-2. bgu481 bottom view/dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 figure a-1. amd geode? lx processors opn example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
amd geode? lx processors data book 7 list of tables 33234h list of tables table 2-1. graphics processor feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 table 3-1. video signal definitions per mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 3-2. buffer type characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 3-3. bootstrap options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 3-4. ball type definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 3-5. ball assignments - sorted by ball number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 3-6. ball assignments - sorted alphabetically by signal name . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 3-7. signal behavior during and after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 4-1. msr addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 4-2. msr mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 4-3. gliu memory descriptor address hit and routing description . . . . . . . . . . . . . . . . . . . . . . 48 table 4-4. gliu i/o descriptor address hit and routing description . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 4-5. geodelink? device standard msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 4-6. gliu specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 4-7. gliu statistic and comparator msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 4-8. gliu p2d descriptor msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 4-9. gliu reserved msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 4-10. gliu iod descriptor msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 5-1. initialized core register controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 5-2. application register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 5-3. segment register selection rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 5-4. eflags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 5-5. system register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 5-6. control registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 5-7. cr4 bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 5-8. cr3 bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 5-9. cr2 bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 5-10. cr0 bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 5-11. effects of various combinations of em, ts, and mp bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 5-12. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 5-13. cpu core specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 table 5-14. xc_hist_msr exception types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 5-15. region properties register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 5-16. read operations vs. region properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 5-17. write operations vs. region properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 6-1. loi - 2 dimms, same size, 1 dimm bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 6-2. loi - 2 dimms, same size, 2 dimm banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 6-3. non-auto loi - 1 or 2 dimms, different sizes, 1 dimm bank . . . . . . . . . . . . . . . . . . . . . . . 214 table 6-4. non-auto loi - 1 or 2 dimms, different sizes, 2 dimm banks . . . . . . . . . . . . . . . . . . . . . . 214 table 6-5. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 6-6. glmc specific msr summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 6-7. graphics processor feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 table 6-8. blt command buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 table 6-9. vector command buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 table 6-10. lut (lookup table) load command buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
8 amd geode? lx processors data book - list of tables 33234h table 6-11. data only command buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 table 6-12. bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 table 6-13. pixel ordering for 4-bit pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 table 6-14. example vector pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 table 6-15. example vector length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 table 6-16. example of monochrome pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 table 6-17. example of 8-bit color pattern (3:3:2 format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 48 table 6-18. example of 16-bit color pattern (5:6:5 format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 table 6-19. 32-bpp 8:8:8:8 color data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 table 6-20. 16-bpp color data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 table 6-21. 8-bpp 3:3:2 color data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 table 6-22. monochrome data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 table 6-23. example of byte-packed monochrome source data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 table 6-24. example of unpacked monochrome source data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 table 6-25. gp_raster_mode bit patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 51 table 6-26. common raster operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 table 6-27. alpha blending modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 table 6-28. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 table 6-29. graphics processor configuration register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 table 6-30. pat_color usage for color patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 table 6-31. pat_data usage for color patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 table 6-32. display modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 table 6-33. cursor display encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 table 6-34. icon display encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 table 6-35. cursor/color key/alpha interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 table 6-36. video bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 table 6-37. yuv 4:2:0 video data ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 table 6-38. yuv 4:2:2 video data ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 table 6-39. vga text modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 table 6-40. text mode attribute byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 table 6-41. vga graphics modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 table 6-42. programming image sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 table 6-43. vertical timing in number of lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 table 6-44. timing register settings for interlaced modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 table 6-45. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 table 6-46. dc specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 table 6-47. dc configuration control register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 table 6-48. vga block configuration register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 table 6-49. vga block standard register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 table 6-50. vga block extended register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 table 6-51. vga sequencer registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 table 6-52. font table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 table 6-53. crtc register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 table 6-54. crtc registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 table 6-55. crtc memory addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 71 table 6-56. graphics controller registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 73 table 6-57. attribute controller registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 table 6-58. video dac registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 table 6-59. extended registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 table 6-60. truth table for alpha-blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 table 6-61. vop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 table 6-62. sav/eav sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 table 6-63. protection bit values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 table 6-64. sav vip flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 table 6-65. vop clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
amd geode? lx processors data book 9 list of tables 33234h table 6-66. panel output signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 table 6-67. register settings for dither enable/disable feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 table 6-68. display rgb modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 table 6-69. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 table 6-70. video processor module specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 table 6-71. video processor module configuration control registers summary . . . . . . . . . . . . . . . . . 412 table 6-72. vip capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 table 6-73. sav/eav sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 table 6-74. vip data types / memory registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 table 6-75. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 table 6-76. vip configuration/control registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 table 6-77. eeprom address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 table 6-78. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 table 6-79. security block specific msrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 table 6-80. security block configuration/control registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . 513 table 6-81. tap control instructions (25-bit ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 table 6-82. tap instruction bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 table 6-83. gio_pci outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 table 6-84. cis signaling protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 table 6-85. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 table 6-86. glcp specific msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 table 6-87. bootstrap bit settings and reset state of glcp_sys_rstpll (pw1 and irq13 = 0) . . 556 table 6-88. bootstrap bit settings and reset state of glcp_sys_rstpll (pw1 and irq13 vary) . . 557 table 6-89. format for accessing the internal pci configuration registers . . . . . . . . . . . . . . . . . . . . . 569 table 6-90. pci device to ad bus mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 table 6-91. standard geodelink? device msrs summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 table 6-92. glpci specific registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 table 6-93. region properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 table 7-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 table 7-2. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 table 7-3. amd geode lx 900@1.5w processor dc currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 table 7-4. amd geode lx 800@0.9w processor dc currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 table 7-5. amd geode lx 700@0.8w processor dc currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 table 7-6. amd geode lx 600@0.7w processor dc currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 table 7-7. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 table 7-8. system interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 table 7-9. pci interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 table 7-10. vip interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 table 7-11. flat panel interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 table 7-12. crt interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 table 7-13. crt display recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 table 7-14. crt display analog (dac) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3 table 7-15. memory (ddr) interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 table 7-16. jtag interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 table 8-1. general instruction set format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 table 8-2. instruction fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 table 8-3. instruction prefix summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 table 8-4. w field encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 table 8-5. d field encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 table 8-6. s field encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 table 8-7. eee field encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 table 8-8. mod r/m field encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 table 8-9. general registers selected by mod r/m fields and w field . . . . . . . . . . . . . . . . . . . . . . . . 623 table 8-10. reg field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 table 8-11. sreg2 field encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
10 amd geode? lx processors data book - list of tables 33234h table 8-12. sreg3 field (fs and gs segment register selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 table 8-13. ss field encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 table 8-14. index field encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 table 8-15. mod base field encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 table 8-16. cpuid instruction with eax = 0000 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 table 8-17. cpuid instruction with eax = 0000 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 table 8-18. cpuid instruction codes with eax = 00000000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 table 8-19. cpuid instruction with eax = 8000 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 table 8-20. cpuid instruction with eax = 8000 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 table 8-21. cpuid instruction codes with eax = 80000001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 table 8-22. cpuid instruction with eax = 80000002h, 80 000003h, or 8 0000004h . . . . . . . . . . . . . . . 631 table 8-23. cpuid instruction with eax = 8000 0005h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 table 8-24. cpuid instruction with eax = 8000 0006h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 table 8-25. processor core instruction set table legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 table 8-26. processor core instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 table 8-27. mmx?, fpu, and amd 3dnow!? instruction set table legend . . . . . . . . . . . . . . . . . . . 658 table 8-28. mmx? instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 table 8-29. fpu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 table 8-30. amd 3dnow!? technology instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 table a-1. valid opn combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 table a-2. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 table a-3. edits to current revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
amd geode? lx processors data book 11 1 overview 33234h 1.0 overview 1.1 general description amd geode? lx processors are integrated x86 proces- sors specifically designed to power embedded devices for entertainment, education, and business. serving the needs of consumers and business professionals alike, it?s an excellent solution for embedded applications, such as thin clients, interactive set-top boxes, single board computers, and mobile computing devices. available with a core voltage of 1.2v, 1.25v, or 1.4v it offers extremely low typical power consumption leading to longer battery life and enabling small form-factor, fanless designs. while the processor core provides maximum compatibility with the vast amount of internet content available, the intel- ligent integration of several other functions, including graphics and video datapaths, offers a true system-level multimedia solution. for implementation details and suggestions for this device, see the supporting documentation (i.e., application notes, schematics, etc.) on the amd embedded developer sup- port web site ( http://wwwd.amd.com/dev , nda required). figure 1-1. internal block diagram geodelink? interface unit 0 geodelink? interface unit 1 geodelink? control diagnostic te s t power mgmnt geodelink? sdclks tlb integer unit mmu load/store fpu 64 kb l1 d-cache 64 kb l1 i-cache bus controller cpu core alpha compositing rop unit blt engine graphics processor (gp) timing palette ram compression buffer display controller (dc) alpha blender video mixer video scalar video processor (vp) rgb yuv graphics filter/scaling (gliu0) (gliu1) memory clock module cpu pll system pll tft/vop 3x8-bit dac crt geodelink? pci video input sysref dotref test/reset interface processor (glcp) pci bridge (glpci) controller (glmc) port (vip) dotclk pll 128 kb l2 cache 1 kb lut rotation blt companion i/f vip hw vga 128-bit aes tft controller/ video output port (vop) amd geode? companion device 64-bit ddr security block random number generator eeprom on package 64-bit ddr sdram (cbc/ecb) tr u e (optional)
12 amd geode? lx processors data book overview 33234h 1.2 features general features functional blocks include: ?cpu core ? geodelink? control processor ? geodelink interface units ? geodelink memory controller ? graphics processor ? display controller ? video processor ? tft controller/video output port ? video input port ? geodelink pci bridge ? security block 0.13 micron process packaging: ? 481-terminal bgu (ball grid array cavity up) with internal heatspreader single packaging option supports all features industrial temperature range available for the lx 800@0.9w processor* cpu processor features x86/x87-compatible cpu core performance: ? processor frequency: up to 600 mhz ? dhrystone 2.1 mips: 150 to 450 ? fully pipelined fpu split i/d cache/tlb (translation look-aside buffer): ? 64 kb i-cache/64 kb d-cache ? 128 kb l2 cache configurable as i-cache, d-cache, or both efficient prefetch and branch prediction integrated fpu that supports the mmx? and amd 3dnow!? instruction sets fully pipelined single precision fpu hardware with microcode support for higher precisions geodelink? control processor jtag interface: ? atpg, full scan, bist on all arrays ? 1149.1 boundary scan compliant ice (in-circuit emulator) interface reset and clock control designed for improved software debug methods and performance analysis power management: ? lx 900@1.5w processor* (unterminated): total dissipated power (tdp) 5.1w, 2.6w typical @ 600 mhz max power ? lx 800@0.9w processor* (unterminated): total dissipated power (tdp) 3.6w, 1.8w typical @ 500 mhz max power ? lx 700@0.8w processor* (unterminated): total dissipated power (tdp) 3.1w, 1.3w typical @ 433 mhz max power ? lx 600@0.7w processor* (unterminated): total dissipated power (tdp) 2.8w, 1.2w typical @ 366 mhz max power ? geodelink active hardware power management ? hardware support for standard acpi software power management ? i/o companion susp/suspa power controls ? lower power i/o ? wakeup on smi/intr works in conjunction with the amd geode? cs5536 (usb 2.0) or cs5535 (usb 1.1) companion device geodelink? architecture high bandwidth packetized uni-directional bus for internal peripherals standardized protocol to allow variants of products to be developed by adding or removing modules geodelink control processor (glcp) for diagnostics and scan control dual geodelink interface units (glius) for device inter- connect geodelink? memory controller integrated memory controller for low latency to cpu and on-chip peripherals 64-bit wide ddr sdram bus operating frequency: ? 200 mhz, 400 mt/s supports unbuffered ddr dimms using up to 2 gb dram technology supports up to 2 dimms (16 devices max) 2d graphics processor high performance 2d graphics controller alpha blt windows ? gdi gui acceleration: ? hardware support for all microsoft rdp codes command buffer interface for asynchronous blts second pattern channel support hardware screen rotation *the amd geode lx 900@1.5w processor operates at 600 mhz, th e amd geode lx 800@0.9w processor operates at 500 mhz, the amd geode lx 700@0.8w processor operates at 433 mhz and the am d geode lx 600@.07w processor operates at 366 mhz. model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodelxbenchmark .
amd geode? lx processors data book 13 overview 33234h display controller hardware frame buffer compression improves unified memory architecture (u ma) memory efficiency crt resolutions supported: ? supports up to 1920x1440x32 bpp at 85 hz ? supports up to 1600x1200x32 bpp at 100 hz supports up to 1600x1200x32 bpp at 60 hz for tft standard definition (sd) resolution for video output port (vop): ? 720x482 at 59.94 hz interlaced for ntsc ? 768x576 at 50 hz interlaced for pal high definition (hd) resolution for video output port (vop): ? up to 1920x1080 at 30 hz interlaced (1080i hd) (74.25 mhz) ? up to 1280x720 at 60 hz progressive (720p hd) (74.25 mhz) supports down to 7.652 mhz dot clock (320x240 qvga) hardware vga hardware supported 48x64 32-bit cursor with alpha blending video processor supports video scaling, mixing and vop hardware video up/down scalar graphics/video alpha blending and color key muxing digital vop (sd and hd) or tft outputs legacy rgb mode vop supports sd and hd 480p, 480i, 720p, and 1080i vesa 1.1, 2.0 and bt.601 24-bit (out only), bt.656 compliant integrated analog crt dac, system clock plls and dot clock pll integrated dot clock pll with up to 350 mhz clock integrated 3x8-bit dac with up to 350 mhz sampling integrated x86 core pll memory pll geodelink? pci bridge pci 2.2 compliant 3.3v signaling and 3.3v i/os 33 to 66 mhz operation 32-bit interface supports virtual pci headers for geodelink devices video input port (vip) vesa 1.1 and 2.0 comp liant, 8 or 16-bit video blanking interval (vbi) support 8 or 16-bit 80 mhz sd or hd capable security block serial eeprom interface for 2k bit unique id and aes (advanced encryption standard) hidden key storage (eeprom optional inside package) electronic code book (ecb) or cipher block chaining (cbc)128-bit aes hardware support true random number generator (trng)
14 amd geode? lx processors data book overview 33234h
amd geode? lx processors data book 15 2 architecture overview 33234h 2.0 architecture overview the cpu core provides maximum compatibility with the vast amount of internet content available while the intelli- gent integration of several other functions, including graph- ics, makes the amd geode? lx processor a true system- level multimedia solution. the amd geode lx processor can be divided into major functional blocks (as shown in figure 1-1 on page 11): ? cpu core ? geodelink? control processor ? geodelink interface units ? geodelink memory controller ? graphics processor ? display controller ? video processor ? tft controller/video output port ? video input port ? geodelink pci bridge ? security block 2.1 cpu core the x86 core consists of an integer unit, cache memory subsystem, and an x87 compat ible fpu (floating point unit). the integer unit contains the instruction pipeline and associated logic. the memory subsystem contains the instruction and data caches, translation look-aside buffers (tlbs), and an interface to the geodelink interface units (glius). the instruction set supported by the core is a combination of intel pentium ? processor, amd athlon? processor, and amd geode lx processor specific instructions. specifi- cally, it supports the pentium, pentium pro, amd 3dnow!? technology and mmx? instructions for the amd athlon processor. it supports a subset of the specialized amd geode lx processor instructions including special smm instructions. the cpu core does not support the entire katmai new instruction (kni) set as implemented in the pentium 3. it does support the mmx instructions for the amd athlon processor, which are a subset of the pentium 3 kni instructions. 2.1.1 integer unit the integer unit consists of a single issue 8-stage pipeline and all the necessary support hardware to keep the pipe- line running efficiently. the instruction pipeline in the integer unit consists of eight stages: 1) instruction prefetch - raw instruction data is fetched from the instruction memory cache. 2) instruction pre-decode - prefix bytes are extracted from raw instruction data. this decode looks-ahead to the next instruction and the bubble can be squashed if the pipeline stalls down stream. 3) instruction decode - performs full decode of instruc- tion data. indicates instruction length back to the prefetch unit, allowing the prefetch unit to shift the appropriate number of bytes to the beginning of the next instruction. 4) instruction queue - fifo containing decoded x86 instructions. allows instruction decode to proceed even if the pipeline is stalled downstream. register reads for data operand address calculations are per- formed during this stage. 5) address calculation #1 - computes linear address of operand data (if required) and issues request to the data memory cache. microcode can take over the pipeline and inject a micro-box here if multi-box instructions require additional data operands. 6) address calculation #2 - operand data (if required) is returned and set up to the execution stage with no bubbles if there was a data cache hit. segment limit checking is performed on the data operand address. the rom is read for setup to execution unit. 7) execution unit - register and/or data memory fetch fed through the arithmetic logic unit (alu) for arith- metic or logical operations. rom always fires for the first instruction box down the pipeline. microcode can take over the pipeline and insert additional boxes here if the instruction requires multiple execution unit stages to complete. 8) writeback - results of the execution unit stages are written to the register file or to data memory.
16 amd geode? lx processors data book architecture overview 33234h 2.1.2 memory management unit the memory management uni t (mmu) translates the linear address supplied by the integer unit into a physical address to be used by the cache unit and the internal bus interface unit. memory management pr ocedures are x86-compati- ble, adhering to standard paging mechanisms. the mmu also contains a load/store unit that is responsible for scheduling cache and external memory accesses. the load/store unit incorporates two performance-enhancing features: ? load-store reordering gives memory reads required by the integer unit a priority over writes to external memory. ? memory-read bypassing eliminates unnecessary memory reads by using vali d data from the execution unit. 2.1.3 cache and tlb subsystem the cache and tlb subsystem of the cpu core supplies the integer pipeline with instructions, data, and translated addresses (when necessary). to support the efficient deliv- ery of instructions, the cache and tlb subsystem has a single clock access 64 kb 16- way set associative instruc- tion cache and a 16-entry fully associative tlb. the tlb performs necessary address translations when in protected mode. for data, there is a 64 kb 16-way set associative writeback cache, and a 16-entry fully associative tlb. when there is a miss to the instruction or data tlbs, there is a second level unified (instruction and data) 64-entry 2- way set associative tlb that takes an additional clock to access. when there is a miss to the instruction or data caches or the tlb, the access must go to the geodelink memory controller (glmc) fo r processing. having both an instruction and a data cache and their associated tlbs improves overall efficiency of the integer unit by enabling simultaneous access to both caches. the l1 caches are supported by a 128 kb unified l2 victim cache. the l2 cache can be configured to hold data, instructions, or both. the l2 cache is 4-way set associa- tive. 2.1.4 bus controller unit the bus controller unit provides a bridge from the proces- sor to the glius. when external memory access is required, due to a cache miss, the physical address is passed to the bus controller unit, that translates the cycle to a geodelink cycle. 2.1.5 floating point unit the floating point unit (fpu) is a pipelined arithmetic unit that performs floating point operations as per the ieee 754 standard. the instruction se ts supported are x87, mmx, and amd 3dnow! technology. the fpu is a pipelined machine with dynamic scheduling of instructions to mini- mize stalls due to data dependencies. it performs out of order execution and register renaming. it is designed to support an instruction issue ra te of one per clock from the integer core. the datapath is optimized for single precision arithmetic. extended precision instructions are handled in microcode and require multiple passes through the pipe- line. there is an execution pipeline and a load/store pipe- line. this allows load/store operations to execute in parallel with arithmetic instructions. 2.2 geodelink? control processor the geodelink control processor (glcp) is responsible for reset control, macro clock management, and debug support provided in the geode lx processor. it contains the jtag interface and the scan chain control logic. it sup- ports chip reset, including initial pll control and program- ming and runtime power management macro clock control. the jtag support includes a tap controller that is ieee 1149.1 compliant. cpu control can be obtained through the jtag interface into the tap controller, and all internal registers, including cpu core registers, can be accessed. in-circuit emulation (ice) capabilities are supported through this jtag and tap controller interface. the glcp also includes the companion device interface. the companion device has several unique signals con- nected to this module that support geode lx processor reset, interrupts, and system power management. 2.3 geodelink? interface units together, the two geodelink interface units (gliu0 and gliu1) make up the internal bus derived from the geodelink architecture. gliu0 connects five high band- width modules together with a seventh link to gliu1 that connects to the five low bandwidth modules. 2.4 geodelink? memory controller the geodelink memory controller (glmc) is the source for all memory needs in a typical geode lx processor sys- tem. the glmc supports a memory data bus width of 64 bits and supports 200 mhz, 400 mt/s for ddr (double data rate). the modules that need memory are the cpu core, graph- ics processor, display controller, video input port, and security block. because the glmc supports memory needs for both the cpu core and the display subsystem, the glmc is classically called a uma (unified memory architecture) subsystem. pc i accesses to main memory are also supported. up to four banks, with eight devices maximum in each bank of sdram, are supported with up to 512 mb in each bank. four banks means that one or two dimm or sodimm mod- ules can be used in a amd geode lx processor system. some memory configurations have additional restrictions on maximum devi ce quantity.
amd geode? lx processors data book 17 architecture overview 33234h 2.5 graphics processor the graphics processor is based on the graphics proces- sor used in the amd geode gx processor with several fea- tures added to enhance performance and functionality. like its predecessor, the amd geode lx processor?s graphics processor is a bitblt/vector engine that supports pattern generation, source expansion, pattern/source transpar- ency, 256 ternary raster operations, alpha blenders to sup- port alpha-blts, incorporated blt fifos, a geodelink interface and the ability to throttle blts according to video timing. features added to the graphics processor include: ? command buffer interface ? hardware accelerated rotation blts ? color depth conversion ? paletized color ? full 8x8 color pattern buffer ? channel 3 - third dma channel ? monochrome inversion table 2-1 presents a comparison between the graphics processor features of the amd geode gx and lx proces- sors. table 2-1. graphics processor feature comparison feature amd geode? gx processor amd geode? lx processor color depth 8, 16, 32 bpp 8, 16, 32 bpp (a) rgb 4 and 8-bit indexed rops 256 (src, dest, pattern) 256 (2-src, dest and pattern) blt buffers fifos in graphics proc essor fifos in graphics processor blt splitting managed by hardware managed by hardware video synchronized blt/vector throttle by vblank throttle by vblank bresenham lines yes yes patterned (stippled) lines no yes screen to screen blt yes yes screen to screen blt with mono expansion ye s ye s memory to screen blt yes (through cpu writes) yes (throttled rep movs writes) accelerated text no no pattern size (mono) 8x8 pixels 8x8 pixels pattern size (color) 8x1 (32 pixels) 8x8 pixels 8x2 (16 pixels) 8x4 (8 pixels) monochrome pattern yes yes (with inversion) dithered pattern (4 color) no no color pattern 8, 16, 32 bpp 8, 16, 32 bpp transparent pattern monochrome monochrome solid fill yes yes pattern fill yes yes transparent source monochrome monochrome color key source transparency y with mask y with mask variable source stride yes yes variable destination stride yes yes destination write bursting yes yes selectable blt direction vertical and horizontal vertical and horizontal alpha blt yes (constant or /pix) yes (constant , /pix, or sep. channel) vga support decodes vga register decodes vga register pipeline depth 2 ops unlimited accelerated rotation blt no 8, 16, 32 bpp color depth conversion no 5:6:5, 1:5:5:5, 4:4:4:4, 8:8:8:8
18 amd geode? lx processors data book architecture overview 33234h 2.6 display controller the display controller performs the following functions: 1) retrieves graphics, video, and cursor data. 2) serializes the streams. 3) performs any necessary color lookups and output for- matting. 4) interfaces to the video processor for driving the dis- play device(s). the display controller consists of a memory retrieval sys- tem for rasterized graphics data, a vga, and a back-end fil- ter. the amd geode lx processor?s display controller corresponds to the display controller function found in the amd geode gx processor with additional hardware for graphics filter functions. the vga provides full hardware compatibility with the vga graphics standard. the raster- ized graphics and the vga share a single display fifo and display refresh memory interface to the geodelink mem- ory controller (glmc). the vga uses 8 bpp and syncs, that are expanded to 24 bpp via the color lookup table, and passes the information to the graphics filter for scaling and interlaced display support. the stream is then passed to the video processor, which is used for video overlay. the video processor forwards this information to the dac (dig- ital-to-analog converter), that generates the analog red, green, and blue signals, and buffers the sync signals that are then sent to the display. the video processor output can also be rendered as yuv data, and can be output on the video output port (vop). 2.7 video processor the video processor mixes the graphics and video streams, and outputs either di gital rgb data to the internal dacs or the flat panel interface, or digital yuv data via the vop interface. the video processor delivers high-resolution and true- color graphics. it can also overlay or blend a scaled true- color video image on the graphic background. the video processor interfaces with the cpu core via a gliu master/slave interface. the video processor is a slave only, as it has no memory requirements. 2.7.1 crt interface the internal high performance dacs support crt resolu- tions up to: ? 1920x1440x32 bpp at 85 hz ? 1600x1200x32 bpp at 100 hz 2.7.2 tft controller the tft controller converts the digital rgb output of a video mixer block to the digital output suitable for driving a tft flat panel lcd. the flat panel connects to the rgb port of the video mixer. it interfaces directly to industry standard 18-bit or 24-bit active matrix thin film transi stor (tft). the digital rgb or video data that is supplied by the video logic is converted into a suitable format to drive a wide range of panels with variable bits. the lcd interface includes dithering logic to increase the apparent number of colors displayed for use on panels with less than 6 bits per color. the lcd interface also supports automatic power sequencing of panel power supplies. it supports panels up to a 24-bit interface and up to 1600x1200 resolution. the tft controller interfaces with the cpu core via a gliu master/slave interface. the tft controller is both a gliu master and slave. 2.7.3 video output port the vop receives yuv 4:4:4 encoded data from the video processor and formats the data into a video stream that is bt.656 compliant. output from the vop goes to either a vip or a tv encoder. the vop is bt.656/601 compliant since its output may go directly (or indirectly) to a display. 2.8 video input port the video input port (vip) receives 8- or 16-bit video or ancillary data, 8-bit message data, or 8-bit raw video and passes it to data buffers located in system memory. the vip is a dma engine. the primary operational mode is as a compliant vesa 2.0 slave. the vesa 2.0 specification defines the protocol for receiving video, vbi, and ancillary data. the addition of the message passing and data streaming modes provides additional flexibility in receiving non-vesa 2.0 compliant data streams. input data is packed into qwords, buffered into a fifo, and sent to system memory over the gliu. the vip masters the inter- nal gliu and transfers the data from the fifo to system memory. the maximum input data rate (8- or 16-bits) is 150 mhz. 2.9 geodelink? pci bridge the geodelink pci bridge (glpci) contains all the neces- sary logic to support an external pci interface. the pci interface is pci v2.2 specification compliant. the logic includes the pci and gliu interf ace control, read and write fifos, and a pci arbiter.
amd geode? lx processors data book 19 architecture overview 33234h 2.10 security block the amd geode lx processor has an on-chip aes 128-bit crypto acceleration block capable of 44 mbps throughput on either encryption or decryption at a processor speed of 500 mhz. the aes block runs asynchronously to the pro- cessor core and is dma ba sed. the aes block supports both ebc and cbc modes and has an interface for accessing the optional eepr om memory for storing unique ids and/or security keys. the aes and eeprom sections have separate contro l registers but share a single set of interrupt registers. the aes module has two key sources: one hidden 128-bit key stored in the ?on-package? eeprom, and a write only 128-bit key (reads as all zeros). the hidden key is loaded automatically by the hardware after reset and is not visible to the processor. the eeprom can be locked. the initialization vector for the cbc mode can be generated by the true random number generator (trng). the trng is addressable separately and generates a 32-bit random number.
20 amd geode? lx processors data book architecture overview 33234h
amd geode? lx processors data book 21 3 signal definitions 33234h 3.0 signal definitions this chapter defines the signals and describes the external in terface of the amd geode? lx processor. figure 3-1 shows the pins organized by their functional groupings. where signal s are multiplexed, the default signal name is listed first and is separated by a plus sign (+). multi-functi on pins are described in table 3-1 on page 22. figure 3-1. signal groups reset# inta# irq13 (strap) sdclk[5:0]n cke[1:0] cs[3:0]# ras[1:0]# cas[1:0]# we[1:0]# dqm[7:0] dqs[7:0] ba[1:0] dq[63:0] ma[13:0] ad[31:0] cbe[3:0]# frame# irdy# trdy# stop# devsel# dotref pa r (strap) gnt[2:0]# cis suspa# (strap) tdp tdn system memory display (tft option) vdden+vip_hsync drgb[25:24]+vid[9:8]+ dotclk+vopclk vsync+vop_vsync hsync+vop_hsync green blue red ldemod+vip_vsync sysref tla[1:0] req[2:0]# vid[7:0] vipclk vipsync vip pw[1:0] (strap) (total of 32) v core (total of 33) v mem (total of 128) v ss (total of 30) v io power/ground interface tclk tms tdi tdo tdbgi tdbgo internal test and measurement amd geode? vav dd , cav dd , mav dd vav ss , cav ss , mav ss mvref display (crt option) dvref drset (total of 4) dav dd (total of 4) dav ss dispen+vop_blank clpf mlpf vlpf lx processor pll pci interface signals signals interface signals interface signals interface signals interface signals interface signals interface signals interface signals sdclk[5:0]p vsync hsync drgb[23:16] drbg[15:8]+vop[15:8] drgb[7:0]+vop[7:0] msgstart+msgstop drgb[31:26]+vid[15:10]
22 amd geode? lx processors data book signal definitions 33234h table 3-1. video signal definitions per mode signal name crt w/16-bit vip rgb w/16-bit vip argb (note 1) w/8-bit vip tft w/16-bit vip (not 601) 8- or 16-bit vop w/16-bit vip red red green green blue blue drgb[31:24] (i/o) vid[15:8] (i) vid[15:8] (i) alpha vid[15:8] (i) vid[15:8] (i) drgb[23:16] (o) r[7:0] r[7:0] r[7:0] r[7:0] (note 2) driven low drgb[15:8] (o) g[7:0] g[7:0] g[7:0] g[7:0] (note 2) vop[15:8] (o) drgb[7:0] (o) b[7:0] b[7:0] b[7:0] b[7:0] (note 2) vop[7:0] (o) dotclk (o) dotclk (o) dotclk (o) dotclk (o) dotclk (o) vopclk (o) hsync (o) hsync (o) hsync (o) hsync (o) vop_hsync (o) vop_hsync (o) vsync (o) vsync (o) vsync (o) vsync (o) vsync (o) vop_vsync (o) dispen (o) dispen (o) vop_blank (o) vdden (i/o) vip_hsync (i) vip_hsync (i) vip_hsync (i) vdden (o) vip_hsync (i) ldemod (i/o) vip_vsync (i) vip_vsync (i) vip_vsync (i) ldemod (o) vip_vsync (i) vid[7:0] (i) vid[7:0] vid[7:0] vid[7:0] vid[7:0] vid[7:0] vipclk (i) vipclk vipclk vipclk vipclk vipclk vipsync (i) vipsync vipsync vipsync vipsync vipsync note 1. alpha red/green/blue: useful for off-chip graphics digital interfaces. note 2. pin usage depends on tft mode. see section 6.7.7 "flat panel display controller" on page 405 for details.
amd geode? lx processors data book 23 signal definitions 33234h 3.1 buffer types the ball assignment tables starting on page 26 include a column labeled ?buffer type?. the details of each buffer type listed in this column are given in table 3-2. the col- umn headings in table 3-2 are identified as follows: ts: indicates whether the buffer may be put into the tri- state mode. note some pins that have buffer types that allow tri-state may never actually enter the tri-state mode in practice, since they may be inputs or provide other signals that are always driven. to determine if a particular signal can be put in the tri-state mode, consult the indi- vidual signal descriptions in section 3.4 "signal descrip- tions" on page 33. od: indicates if the buffer is open-drain, or not. open-drain outputs may be wire ored t ogether and require a discrete pull-up resistor to operate properly. 5vt: indicates if the buffer is 5-volt tolerant, or not. if it is 5- volt tolerant, then 5 volt ttl signals may be safely applied to this pin. pu/pd: indicates if an internal, programmable pull-up or pull-down resistor may be present. current high/low (ma): this column gives the current source/sink capacities when the voltage at the pin is high, and low. the high and low values are separated by a ?/? and values given are in milli-amps (ma). rise/fall @ load: this column indicates the rise and fall times for the different buffer types at the load capacitance indicated. these measuremen ts are given in two ways: rise/fall time between the 20%-80% voltage levels, or, the rate of change the buffer is capable of, in volts-per-nano- second (v/ns). note the presence of ?wire? type buffer in this table. sig- nals identified as a wire-type are not driven by a buffer, hence no rise/fall time or other measurements are given; these are marked ?na? in tabl e 3-2. the wire-type connec- tion indicates a direct connection to internal circuits such as power, ground, and analog signals. table 3-2. buffer type characteristics name ts od 5vt pu/pd current high/low (ma) rise/fall @ load 24/q3 x x 24/24 3 ns @ 50 pf 24/q5 x x 24/24 5 ns @ 50 pf 24/q7 x x 24/24 7 ns @ 50 pf 5v x x 16/16 1.25v/ns @ 40 pf pci x 0.5/1.5 1-4v/ns @ 10 pf ddrclk 10/10 8.5v/ns @ 15 pf ddr 2.4v/ns @ 50 pf wire na na na na na
24 amd geode? lx processors data book signal definitions 33234h 3.2 bootstrap options the bootstrap options shown in table 3-3 are supported in the amd geode lx processor for configuring the system. 3.3 ball assignments the tables in this chapter use several common abbrevia- tions. table 3-4 lists the mnemonics and their meanings. table 3-3. bootstrap options pins description irq13 0: normal boot operation, tap reset active during pci reset 1: debug stall of cpu after cpu reset, tap reset active until v io valid pw1 0: pci (sysref) is 33 mhz 1: pci (sysref) is 66 mhz pw0, suspa#, gnt[2:0]# select cpu and geodelink system mhz options including a pll bypass option. refer to table 6-87 on page 556 for programming. table 3-4. ball type definitions mnemonic definition aanalog i input ball i/o bidirectional ball cav ss core pll ground ball: analog cav dd core pll power ball: analog dav ss dac pll ground ball: analog dav dd dac pll power ball: analog mav ss gliu pll ground ball: analog mav dd gliu pll power ball: analog o output ball vav ss video pll ground ball: analog vav dd video pll power ball: analog v core power ball: 1.2v (nominal) v io i/o power ball: 3.3v (nominal) v mem power ball: 2.5v v ss ground ball # the ?#? symbol at the end of a signal name indicates that the active, or asserted state, occurs when the sig- nal is at a low voltage level. when ?#? is not present after the signal name, the signal is asserted when at a high voltage level.
amd geode? lx processors data book 25 signal definitions 33234h figure 3-2. bgu481 ball assignment diagram 12345678910111213141516171819202122232425262728293031 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al note: signal names have been abbreviated in this figure due to space constraints. v ss v mem v ss dq21 v ss dqm2 dq22 v ss dq28 dqs3 v ss dq26 dq31 v mem dq32 v ss dq37 v mem dqm4 dq39 v ss dq40 dq41 v ss dq42 dq43 v ss we1# v ss v mem v ss 12345678910111213141516171819202122232425262728293031 v mem v ss v ss dq17 v mem dq18 dq23 v mem dq24 dqm3 v mem dq27 tla1 v ss tla0 dq36 dq33 v ss dq34 dq38 v mem dq35 dqs5 v mem dq46 dq47 v mem cs0# v ss v ss v mem v ss v ss v mem v ss ma12 dqs2 v mem dq19 dq29 dq25 dq30 v ss ma3 v mem ma2 ma0 ma1 v mem dqs4 ba1 v ss dq44 dq45 dqm5 v mem ras0# we0# v ss v mem v ss v ss dq20 dq16 v ss v mem ma11 ma9 v ss ma7 ma8 v ss ma5 ma6 ma4 v ss v core v ss v core v ss ma10 sdk5p sdk5n v ss sdk4p sdk4n v ss ba0 ras1# v mem v ss cs3# dq48 v ss v mem dq11 cke0 cas0# cas1# v mem v ss dq15 dq14 dq10 cke1 cs1# cs2# ma13 dq49 dq13 dqm1 v mem v ss v ss v mem dq52 dq53 v mem v ss dqs1 sdk1n sdk3n dqm6 v ss v mem dq9 dq8 dq12 sdk1p sdk3p dqs6 dq55 dq54 dq7 dq3 v mem v ss v ss v mem dq50 dq51 v mem v ss dq6 sdk0n sdk2n dq60 v ss v mem dqm0 dqs0 dq2 sdk0p sdk2p dq61 dq57 dq56 dq5 dq1 v ss v mem mvref dq0 dq4 v ss v ss v mem dqm7 dqs7 v ss v mem dq62 v ss v ss v ss v ss v ss v core v core v core v core dav dd blue dav ss v core dav dd green dav ss dav dd dvref dav ss red dav dd drset dav ss v io v ss vav dd vav ss vlpf tms dotref tdbgi tdi tdbgo tdo tclk v io v ss v io v ss vsync ldemod dotclk vden hsync dispen drb17 drb16 v io v ss v io v ss drb18 drb19 v core dq63 dq58 dq59 v ss v ss v ss v ss v core v core v core v core v core mlpf mav ss mav dd v ss clpf cav ss cav dd v core v ss reset# syref gnt0# req0# v ss v io req2# irq13 gnt1# req1# v ss v io gnt2# supa# inta# ad31 v ss v io ad27 cis ad29 ad30 v ss v io ad26 ad28 ad25 ad24 v ss v io drb20 drb21 drb22 v ss drb11 v ss drb0 drb6 v ss drb29 drb24 v ss vid3 v ss v core v ss v core v ss ad1 v ss ad5 ad11 v ss ad14 irdy# v ss cbe2# v ss ad23 ad22 cbe3# drb23 drb8 v io drb12 drb15 v io drb3 drb7 v io drb28 drb25 v io vid4 v io vid0 v ss pw1 v io ad0 v io ad6 cbe0# v io ad15 stop# v io pa r a d 1 6 v io ad19 ad21 v io v ss drb9 drb14 v ss drb1 drb4 v ss drb31 drb26 v ss vid7 vid5 v ss vid1 v ss tdn v ss ad4 ad3 v ss ad8 ad10 v ss devsl# trdy# v ss ad17 ad20 v ss v io v ss v io drb10 drb13 v io drb2 drb5 v io drb30 drb27 v io vipclk vid6 vipsync vid2 v ss tdp pw0 ad7 ad2 v io ad9 ad12 v io ad13 cbe1# v io frame# ad18 v io v ss amd geode? lx processor s = gnd ball = pwr ball = strap option ball = multiplexed ball v core v core v ss v ss v ss v core v core v core v core v ss v ss v ss v core v core v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v core v core v ss v ss v ss v core v core v core v core v ss v ss v ss v core v core (top view) s s s s s s s
26 amd geode? lx processors data book signal definitions 33234h ball no. signal name (note 1) type (pd) buffer type a1 v ss gnd --- a2 v mem pwr --- a3 v ss gnd --- a4 dq21 i/o ddr a5 v ss gnd --- a6 dqm2 i/o ddr a7 dq22 i/o ddr a8 v ss gnd --- a9 dq28 i/o ddr a10 dqs3 i/o ddr a11 v ss gnd --- a12 dq26 i/o ddr a13 dq31 i/o ddr a14 v mem pwr --- a15 dq32 i/o ddr a16 v ss gnd --- a17 dq37 i/o ddr a18 v mem pwr --- a19 dqm4 i/o ddr a20 dq39 i/o ddr a21 v ss gnd --- a22 dq40 i/o ddr a23 dq41 i/o ddr a24 v ss gnd --- a25 dq42 i/o ddr a26 dq43 i/o ddr a27 v ss gnd --- a28 we1# i/o ddr a29 v ss gnd --- a30 v mem pwr --- a31 v ss gnd --- b1 v mem pwr --- b2 v ss gnd --- b3 v ss gnd --- b4 dq17 i/o ddr b5 v mem pwr --- b6 dq18 i/o ddr b7 dq23 i/o ddr b8 v mem pwr --- b9 dq24 i/o ddr b10 dqm3 i/o ddr b11 v mem pwr --- b12 dq27 i/o ddr b13 tla1 i/o ddr b14 v ss gnd --- b15 tla0 i/o ddr b16 dq36 i/o ddr b17 dq33 i/o ddr b18 v ss gnd --- b19 dq34 i/o ddr b20 dq38 i/o ddr b21 v mem pwr --- b22 dq35 i/o ddr b23 dqs5 i/o ddr b24 v mem pwr --- b25 dq46 i/o ddr b26 dq47 i/o ddr b27 v mem pwr --- b28 cs0# i/o ddr b29 v ss gnd --- b30 v ss gnd --- b31 v mem pwr --- c1 v ss gnd --- c2 v ss gnd --- c3 v mem pwr --- c4 v ss gnd --- c5 ma12 i/o ddr c6 dqs2 i/o ddr c7 v mem pwr --- c8 dq19 i/o ddr c9 dq29 i/o ddr c10 dq25 i/o ddr c11 dq30 i/o ddr c12 v ss gnd --- c13 ma3 i/o ddr c14 v mem pwr --- c15 ma2 i/o ddr c16 ma0 i/o ddr c17 ma1 i/o ddr c18 v mem pwr --- c19 dqs4 i/o ddr c20 ba1 i/o ddr c21 v ss gnd --- c22 dq44 i/o ddr c23 dq45 i/o ddr c24 dqm5 i/o ddr c25 v mem pwr --- c26 ras0# i/o ddr c27 we0# i/o ddr c28 v ss gnd --- c29 v mem pwr --- c30 v ss gnd --- c31 v ss gnd --- d1 dq20 i/o ddr d2 dq16 i/o ddr d3 v ss gnd --- d4 v mem pwr --- d5 ma11 i/o ddr d6 ma9 i/o ddr ball no. signal name (note 1) type (pd) buffer type d7 v ss gnd --- d8 ma7 i/o ddr d9 ma8 i/o ddr d10 v ss gnd --- d11 ma5 i/o ddr d12 ma6 i/o ddr d13 ma4 i/o ddr d14 v ss gnd --- d15 v core pwr --- d16 v ss gnd --- d17 v core pwr --- d18 v ss gnd --- d19 ma10 i/o ddr d20 sdclk5p o ddrclk d21 sdclk5n o ddrclk d22 v ss gnd --- d23 sdclk4p o ddrclk d24 sdclk4n o ddrclk d25 v ss gnd --- d26 ba0 i/o ddr d27 ras1# i/o ddr d28 v mem pwr --- d29 v ss gnd --- d30 cs3# i/o ddr d31 dq48 i/o ddr e1 v ss gnd --- e2 v mem pwr --- e3 dq11 i/o ddr e4 cke0 i/o ddr e28 cas0# i/o ddr e29 cas1# i/o ddr e30 v mem pwr --- e31 v ss gnd --- f1 dq15 i/o ddr f2 dq14 i/o ddr f3 dq10 i/o ddr f4 cke1 i/o ddr f28 cs1# i/o ddr f29 cs2# i/o ddr f30 ma13 i/o ddr f31 dq49 i/o ddr g1 dq13 i/o ddr g2 dqm1 i/o ddr g3 v mem pwr --- g4 v ss gnd --- g28 v ss gnd --- g29 v mem pwr --- g30 dq52 i/o ddr g31 dq53 i/o ddr h1 v mem pwr --- ball no. signal name (note 1) type (pd) buffer type table 3-5. ball assignments - sorted by ball number
amd geode? lx processors data book 27 signal definitions 33234h h2 v ss gnd --- h3 dqs1 i/o ddr h4 sdclk1n o ddrclk h28 sdclk3n o ddrclk h29 dqm6 i/o ddr h30 v ss gnd --- h31 v mem pwr --- j1 dq9 i/o ddr j2 dq8 i/o ddr j3 dq12 i/o ddr j4 sdclk1p o ddrclk j28 sdclk3p o ddrclk j29 dqs6 i/o ddr j30 dq55 i/o ddr j31 dq54 i/o ddr k1 dq7 i/o ddr k2 dq3 i/o ddr k3 v mem pwr --- k4 v ss gnd --- k28 v ss gnd --- k29 v mem pwr --- k30 dq50 i/o ddr k31 dq51 i/o ddr l1 v mem pwr --- l2 v ss gnd --- l3 dq6 i/o ddr l4 sdclk0n o ddrclk l28 sdclk2n o ddrclk l29 dq60 i/o ddr l30 v ss gnd --- l31 v mem pwr --- m1 dqm0 i/o ddr m2 dqs0 i/o ddr m3 dq2 i/o ddr m4 sdclk0p o ddrclk m28 sdclk2p o ddrclk m29 dq61 i/o ddr m30 dq57 i/o ddr m31 dq56 i/o ddr n1 dq5 i/o ddr n2 dq1 i/o ddr n3 v ss gnd --- n4 v mem pwr --- n13 v core pwr --- n14 v core pwr --- n15 v ss gnd --- n16 v ss gnd --- n17 v ss gnd --- n18 v core pwr --- n19 v core pwr --- ball no. signal name (note 1) type (pd) buffer type n28 v ss gnd --- n29 v mem pwr --- n30 dqm7 i/o ddr n31 dqs7 i/o ddr p1 mvref i --- p2 dq0 i/o ddr p3 dq4 i/o ddr p4 v ss gnd --- p13 v core pwr --- p14 v core pwr --- p15 v ss gnd --- p16 v ss gnd --- p17 v ss gnd --- p18 v core pwr --- p19 v core pwr --- p28 v ss gnd --- p29 v mem pwr --- p30 dq62 i/o ddr p31 v ss gnd --- r1 v ss gnd --- r2 v ss gnd --- r3 v ss gnd --- r4 v ss gnd --- r13 v ss gnd --- r14 v ss gnd --- r15 v ss gnd --- r16 v ss gnd --- r17 v ss gnd --- r18 v ss gnd --- r19 v ss gnd --- r28 v core pwr --- r29 dq63 i/o ddr r30 dq58 i/o ddr r31 dq59 i/o ddr t1 v core pwr --- t2 v core pwr --- t3 v core pwr --- t4 v core pwr --- t13 v ss gnd --- t14 v ss gnd --- t15 v ss gnd --- t16 v ss gnd --- t17 v ss gnd --- t18 v ss gnd --- t19 v ss gnd --- t28 v ss gnd --- t29 v ss gnd --- t30 v ss gnd --- ball no. signal name (note 1) type (pd) buffer type t31 v ss gnd --- u1 dav dd apwr --- u2 blue a --- u3 dav ss agnd --- u4 v core pwr --- u13 v ss gnd --- u14 v ss gnd --- u15 v ss gnd --- u16 v ss gnd --- u17 v ss gnd --- u18 v ss gnd --- u19 v ss gnd --- u28 v core pwr --- u29 v core pwr --- u30 v core pwr --- u31 v core pwr --- v1 dav dd apwr --- v2 green a --- v3 dav ss agnd --- v4 dav dd apwr --- v13 v core pwr --- v14 v core pwr --- v15 v ss gnd --- v16 v ss gnd --- v17 v ss gnd --- v18 v core pwr --- v19 v core pwr --- v28 v core pwr --- v29 mlpf a --- v30 mav ss agnd --- v31 mav dd apwr --- w1 dvref a --- w2 dav ss agnd --- w3 red a --- w4 dav dd apwr --- w13 v core pwr --- w14 v core pwr --- w15 v ss gnd --- w16 v ss gnd --- w17 v ss gnd --- w18 v core pwr --- w19 v core pwr ddr w28 v ss gnd --- w29 clpf a --- w30 cav ss agnd --- w31 cav dd apwr --- y1 drset a --- ball no. signal name (note 1) type (pd) buffer type table 3-5. ball assignments - sorted by ball number (continued)
28 amd geode? lx processors data book signal definitions 33234h y2 dav ss agnd --- y3 v io pwr --- y4 v ss gnd --- y28 v core pwr --- y29 v ss gnd --- y30 reset# i pci y31 sysref i pci aa1 vav dd apwr --- aa2 vav ss agnd --- aa3 vlpf a --- aa4 tms i 24/q7 aa28 gnt0# i/o pci aa29 req0# i pci aa30 v ss gnd --- aa31 v io pwr --- ab1 dotref i pci ab2 tdbgi i 24/q7 ab3 tdi i 24/q7 ab4 tdbgo o (pd) 24/q3 ab28 req2# i/o pci ab29 irq13 i/o (pd) 24/q5 ab30 gnt1# i/o pci ab31 req1# i/o pci ac1 tdo o 24/q5 ac2 tclk i 24/q7 ac3 v io pwr --- ac4 v ss gnd --- ac28 v ss gnd --- ac29 v io pwr --- ac30 gnt2# i/o pci ac31 suspa# i/o 24/q5 ad1 v io pwr --- ad2 v ss gnd --- ad3 vsync o (pd) 5v vop_vsync o ad4 ldemod i/o (pd) 24/q5 vip_vsync i ad28 inta# i/o (pd) 24/q5 ad29 ad31 i/o pci ad30 v ss gnd --- ad31 v io pwr --- ae1 dotclk o (pd) 24/q3 vopclk o ae2 vdden i/o (pd) 24/q5 vip_hsync i ae3 hsync o (pd) 5v vop_hsync o ae4 dispen o (pd) 24/q5 vop_blank o ae28 ad27 i/o pci ball no. signal name (note 1) type (pd) buffer type ae29 cis i/o 24/q7 ae30 ad29 i/o pci ae31 ad30 i/o pci af1 drgb17 o (pd) 24/q5 af2 drgb16 o (pd) 24/q5 af3 v io pwr --- af4 v ss gnd --- af28 v ss gnd --- af29 v io pwr --- af30 ad26 i/o pci af31 ad28 i/o pci ag1 v io pwr --- ag2 v ss gnd --- ag3 drgb18 o (pd) 24/q5 ag4 drgb19 o (pd) 24/q5 ag28 ad25 i/o pci ag29 ad24 i/o pci ag30 v ss gnd --- ag31 v io pwr --- ah1 drgb20 o (pd) 24/q5 ah2 drgb21 o (pd) 24/q5 ah3 drgb22 o (pd) 24/q5 ah4 v ss gnd --- ah5 drgb11 o (pd) 24/q5 vop12 o ah6 v ss gnd --- ah7 drgb0 o (pd) 24/q5 vop7 o ah8 drgb6 o (pd) 24/q5 vop1 o ah9 v ss gnd --- ah10 drgb29 i/o (pd) 24/q5 vid13 i ah11 drgb24 i/o (pd) 24/q5 msgstart i vid8 i ah12 v ss gnd --- ah13 vid3 i/o (pd) 24/q7 ah14 v ss gnd --- ah15 v core pwr --- ah16 v ss gnd --- ah17 v core pwr --- ah18 v ss gnd --- ah19 ad1 i/o pci ah20 v ss gnd --- ah21 ad5 i/o pci ah22 ad11 i/o pci ah23 v ss gnd --- ah24 ad14 i/o pci ah25 irdy# i/o pci ball no. signal name (note 1) type (pd) buffer type ah26 v ss gnd --- ah27 cbe2# i/o pci ah28 v ss gnd --- ah29 ad23 i/o pci ah30 ad22 i/o pci ah31 cbe3# i/o pci aj1 drgb23 o (pd) 24/q5 aj2 drgb8 o (pd) 24/q5 vop15 o aj3 v io pwr --- aj4 drgb12 o (pd) 24/q5 vop11 o aj5 drgb15 o (pd) 24/q5 vop8 o aj6 v io pwr --- aj7 drgb3 o (pd) 24/q5 vop4 o aj8 drgb7 o (pd) 24/q5 vop0 o aj9 v io pwr --- aj10 drgb28 i/o (pd) 24/q5 vid12 o aj11 drgb25 i/o (pd) 24/q5 msgstop i vid9 i aj12 v io pwr --- aj13 vid4 i/o (pd) 24/q7 aj14 v io pwr --- aj15 vid0 i/o (pd) 24/q7 aj16 v ss gnd --- aj17 pw1 i/o 24/q7 aj18 v io pwr --- aj19 ad0 i/o pci aj20 v io pwr --- aj21 ad6 i/o pci aj22 cbe0# i/o pci aj23 v io pwr --- aj24 ad15 i/o pci aj25 stop# i/o pci aj26 v io pwr --- aj27 par i/o pci aj28 ad16 i/o pci aj29 v io pwr --- aj30 ad19 i/o pci aj31 ad21 i/o pci ak1 v io pwr --- ak2 v ss gnd --- ak3 drgb9 o (pd) 24/q5 vop14 o ball no. signal name (note 1) type (pd) buffer type table 3-5. ball assignments - sorted by ball number (continued)
amd geode? lx processors data book 29 signal definitions 33234h ak4 drgb14 o (pd) 24/q5 vop9 o ak5 v ss gnd --- ak6 drgb1 o (pd) 24/q5 vop6 o ak7 drgb4 o (pd) 24/q5 vop3 o ak8 v ss gnd --- ak9 drgb31 i/o (pd) 24/q5 vid15 i ak10 drgb26 i/o (pd) 24/q5 vid10 i ak11 v ss gnd --- ak12 vid7 i/o (pd) 24/q7 ak13 vid5 i/o (pd) 24/q7 ak14 v ss gnd --- ak15 vid1 i/o (pd) 24/q7 ak16 v ss gnd --- ak17 tdn a a ak18 v ss gnd --- ak19 ad4 i/o pci ak20 ad3 i/o pci ak21 v ss gnd --- ak22 ad8 i/o pci ak23 ad10 i/o pci ball no. signal name (note 1) type (pd) buffer type ak24 v ss gnd --- ak25 devsel# i/o pci ak26 trdy# i/o pci ak27 v ss gnd --- ak28 ad17 i/o pci ak29 ad20 i/o pci ak30 v ss gnd --- ak31 v io pwr --- al1 v ss gnd --- al2 v io pwr --- al3 drgb10 o (pd) 24/q5 vop13 o al4 drgb13 o (pd) 24/q5 vop10 o al5 v io pwr --- al6 drgb2 o (pd) 24/q5 vop5 o al7 drgb5 o (pd) 24/q5 vop2 o al8 v io pwr --- al9 drgb30 i/o (pd) 24/q5 vid14 i al10 drgb27 i/o (pd) 24/q5 vid11 i ball no. signal name (note 1) type (pd) buffer type al11 v io pwr --- al12 vipclk i/o (pd) 5v al13 vid6 i/o (pd) 24/q7 al14 vipsync i/o (pd) 5v al15 vid2 i/o (pd) 24/q7 al16 v ss gnd --- al17 tdp a --- al18 pw0 i/o 24/q7 al19 ad7 i/o pci al20 ad2 i/o pci al21 v io pwr --- al22 ad9 i/o pci al23 ad12 i/o pci al24 v io pwr --- al25 ad13 i/o pci al26 cbe1# i/o pci al27 v io pwr --- al28 frame# i/o pci al29 ad18 i/o pci al30 v io pwr --- al31 v ss gnd --- note 1.the primary signal name is listed first. ball no. signal name (note 1) type (pd) buffer type table 3-5. ball assignments - sorted by ball number (continued)
30 amd geode? lx processors data book signal definitions 33234h signal name ball no. ad0 aj19 ad1 ah19 ad2 al20 ad3 ak20 ad4 ak19 ad5 ah21 ad6 aj21 ad7 al19 ad8 ak22 ad9 al22 ad10 ak23 ad11 ah22 ad12 al23 ad13 al25 ad14 ah24 ad15 aj24 ad16 aj28 ad17 ak28 ad18 al29 ad19 aj30 ad20 ak29 ad21 aj31 ad22 ah30 ad23 ah29 ad24 ag29 ad25 ag28 ad26 af30 ad27 ae28 ad28 af31 ad29 ae30 ad30 ae31 ad31 ad29 ba0 d26 ba1 c20 blue u2 cas0# e28 cas1# e29 cav dd w31 cav ss w30 cbe0# aj22 cbe1# al26 cbe2# ah27 cbe3# ah31 cis ae29 cke0 e4 cke1 f4 clpf w29 cs0# b28 cs1# f28 cs2# f29 cs3# d30 dav dd u1, v1, v4, w4 dav ss u3, v3, y2, w2 devsel# ak25 dispen ae4 dotclk ae1 dotref ab1 dq0 p2 dq1 n2 dq2 m3 dq3 k2 dq4 p3 dq5 n1 dq6 l3 dq7 k1 dq8 j2 dq9 j1 dq10 f3 dq11 e3 dq12 j3 dq13 g1 dq14 f2 dq15 f1 dq16 d2 dq17 b4 dq18 b6 dq19 c8 dq20 d1 dq21 a4 dq22 a7 dq23 b7 dq24 b9 dq25 c10 dq26 a12 dq27 b12 dq28 a9 dq29 c9 dq30 c11 dq31 a13 dq32 a15 dq33 b17 dq34 b19 dq35 b22 dq36 b16 dq37 a17 dq38 b20 signal name ball no. dq39 a20 dq40 a22 dq41 a23 dq42 a25 dq43 a26 dq44 c22 dq45 c23 dq46 b25 dq47 b26 dq48 d31 dq49 f31 dq50 k30 dq51 k31 dq52 g30 dq53 g31 dq54 j31 dq55 j30 dq56 m31 dq57 m30 dq58 r30 dq59 r31 dq60 l29 dq61 m29 dq62 p30 dq63 r29 dqm0 m1 dqm1 g2 dqm2 a6 dqm3 b10 dqm4 a19 dqm5 c24 dqm6 h29 dqm7 n30 dqs0 m2 dqs1 h3 dqs2 c6 dqs3 a10 dqs4 c19 dqs5 b23 dqs6 j29 dqs7 n31 drgb0 ah7 drgb1 ak6 drgb2 al6 drgb3 aj7 drgb4 ak7 drgb5 al7 drgb6 ah8 signal name ball no. table 3-6. ball assignments - sorted alphabetically by signal name
amd geode? lx processors data book 31 signal definitions 33234h drgb7 aj8 drgb8 aj2 drgb9 ak3 drgb10 al3 drgb11 ah5 drgb12 aj4 drgb13 al4 drgb14 ak4 drgb15 aj5 drgb16 af2 drgb17 af1 drgb18 ag3 drgb19 ag4 drgb20 ah1 drgb21 ah2 drgb22 ah3 drgb23 aj1 drgb24 ah11 drgb25 aj11 drgb26 ak10 drgb27 al10 drgb28 aj10 drgb29 ah10 drgb30 al9 drgb31 ak9 drset y1 dvref w1 frame# al28 gnt0# aa28 gnt1# ab30 gnt2# ac30 green v2 hsync ae3 inta# ad28 irdy# ah25 irq13 ab29 ldemod ad4 ma0 c16 ma1 c17 ma2 c15 ma3 c13 ma4 d13 ma5 d11 ma6 d12 ma7 d8 ma8 d9 ma9 d6 ma10 d19 signal name ball no. ma11 d5 ma12 c5 ma13 f30 mav dd v31 mav ss v30 mlpf v29 msgstart ah11 msgstop aj11 mvref p1 pa r a j 2 7 pw0 al18 pw1 aj17 ras0# c26 ras1# d27 red w3 req0# aa29 req1# ab31 req2# ab28 reset# y30 sdclk0n l4 sdclk0p m4 sdclk1n h4 sdclk1p j4 sdclk2n l28 sdclk2p m28 sdclk3n h28 sdclk3p j28 sdclk4n d24 sdclk4p d23 sdclk5n d21 sdclk5p d20 stop# aj25 suspa# ac31 sysref y31 tclk ac2 tdbgi ab2 tdbgo ab4 tdi ab3 tdn ak17 tdo ac1 tdp al17 tla0 b15 tla1 b13 tms aa4 trdy# ak26 vav dd aa1 vav ss aa2 signal name ball no. v core (total of 32) d15, d17, n13, n14, n18, n19, p13, p14, p18, p19, r28, t1, t2, t3, t4, u4, v13, v14, v18, v19, u28, u29, u30, u31, v28, w13, w14, w18, w19, y28, ah15, ah17 vdden ae2 v io (total of 30) y3, aa31, aj3, aj6, aj9, aj12, aj14, aj18, aj20, aj23, aj26, aj29, ac3, ak1, ak31, al2, al5, al8, al11, al21, al24, al27, al30, ac29, ad1, ad31, af3, af29, ag1, ag31 vid0 aj15 vid1 ak15 vid2 al15 vid3 ah13 vid4 aj13 vid5 ak13 vid6 al13 vid7 ak12 vid8 ah11 vid9 aj11 vid10 ak10 vid11 al10 vid12 aj10 vid13 ah10 vid14 al9 vid15 ak9 vipclk al12 vip_hsync ae2 vipsync al14 vip_vsync ad4 vlpf aa3 vop0 aj8 vop1 ah8 vop2 al7 vop3 ak7 vop4 aj7 vop5 al6 vop6 ak6 vop7 ah7 vop8 aj5 vop9 ak4 vop10 al4 vop11 aj4 vop12 ah5 signal name ball no. table 3-6. ball assignments - sorted alphabetically by signal name (continued)
32 amd geode? lx processors data book signal definitions 33234h vop13 al3 vop14 ak3 vop15 aj2 vop_blank ae4 vopclk ae1 vop_hsync ae3 vop_vsync ad3 v mem (total of 33) a2, a14, b1, b5, b8, b11, b21. b24, b27, b31, c3, c7, c14, c18, c25, c29, d4, d28, a18, e2, e30, g3, g29, h1, h31, k3, k29, l1, l31, a30, n4, n29, p29 signal name ball no. v ss (total of 128) a1, a3, a29, a31, aa30, ac4, ac28, ad2, ad30, af4, af28, ag2, ag30, ah4, ah6, ah9, ah12, ah14, ah16, ah18, ah20, b2, ah23, ah26, ah28, aj16, ak2, ak5, ak8, ak11, ak14, ak16, b3, ak18, ak21, ak24, ak27, ak30, al1, al16, al31, b14, b18, b29, b30, c1, c2, c4, a5, c12, c21, c28, c30, c31, d3, d7, d10, d14, d16, a8, d18, d22, d25, d29, e1, e31, g4, g28, h2, h30, a11, k4, k28, l2, l30, n3, n15, n16, n17, n28, p4, a16, p15, p16, p17, p28, p31, r1, r2, r3, r4, r13, a21, r14, r15, r16, r17, r18, r19, t13, t14, t15, t16, a24, t17, t18, t19, t28, t29, t30, t31, u13, u14, u15, a27, u16, u17, u18, u19, v15, v16, v17, w15, w16, w17, w28, y4, y29 signal name ball no. vsync ad3 we0# c27 we1# a28 signal name ball no. table 3-6. ball assignments - sorted alphabetically by signal name (continued)
amd geode? lx processors data book 33 signal definitions 33234h 3.4 signal descriptions 3.4.1 system interface signals signal name ball no. type f v description sysref y31 i 33, 66 mhz 3.3 system reference. pci input clock; typically 33 or 66 mhz. dotref ab1 i 48 mhz 3.3 dot clock reference. input clock for dotclk pll. inta# ad28 i/o (pd) 0-66 mb/s 3.3 interrupt . interrupt from the amd geode lx proces- sor to the cs5536 companion device (open drain). irq13 ab29 (strap) i/o (pd) 0-66 mb/s 3.3 interrupt request level 13. when a floating point error occurs, the amd geode lx processor asserts irq13. the floating point interrupt handler then per- forms an out instruction to i/o address f0h or f1h. the amd geode lx processor accepts either of these cycles and clears irq13. irq13 is an output during normal operation. it is an input at reset and functions as a boot strap for tester features on a board. it must be pulled low for normal operation. cis ae29 i/o 0-66 mb/s 3.3 cpu interface serial. the glcp i/o companion interface uses the cis signal to create a serial bus. it contains intr#, susp# , nmi#, input_dis#, output_dis#, and smi#. for details see "gio_pci serial protocol" on page 538. suspa# ac31 (strap) i/o 0-66 mb/s 3.3 suspend acknowledge. suspend acknowledge indicates that the amd geode lx processor has entered low-power suspend mode as a result of susp# assertion (as part of the packet asserted on the cis signal) or executi on of a hlt instruction. (the amd geode lx processor enters suspend mode following execution of a hlt instruction if the susponhlt bit, msr 00001210h[0], is set.) the sysref input may be stopped after suspa# has been asserted to further reduce power con- sumption if the system is configured for 3 volt sus- pend mode. suspa# is an output during normal operation. it is an input at reset and functions as a boot strap for fre- quency selection on a board. it must be pulled high or low to invoke the strap. pw0, pw1 al18, aj17 (strap) i/o 0-300 mb/s 3.3 powerwise controls. used for debug. pwx is an output during normal operation. it is an input at reset and functions as a boot strap for fre- quency selection on a board. it must be pulled high or low to invoke the strap.
34 amd geode? lx processors data book signal definitions 33234h tdp al17 a analog n/a thermal diode positive (tdp). tdp is the positive terminal of the thermal diode on the die. the diode is used to do thermal characterization of the device in a system. this signal wor ks in conjunction with tdn. for accurate die temperature measurements, a dual current source remote sensor, such as the national semiconductor lm82, should be used. single cur- rent source sensors may not yield the desired level of accuracy. if reading the cpu temperature is required while the system is off, then a small bias (<0.25v) on v io is required for the thermal diode to operate properly. tdn ak17 a analog n/a thermal diode negative (tdn). tdn is the nega- tive terminal of the thermal diode on the die. the diode is used to do thermal characterization of the device in a system. this si gnal works in conjunction with tdp. for accurate die temperature measurements, a dual current source remote sensor, such as the national semiconductor lm82, should be used. single cur- rent source sensors may not yield the desired level of accuracy. if reading the cpu temperature is required while the system is off, then a small bias (<0.25v) on v io is required for the thermal diode to operate properly. 3.4.1 system interface signals (continued) signal name ball no. type f v description 3.4.2 pll interface signals signal name ball no. type f v description cav dd w31 apwr analog 3.3 core pll analog power. connect to 3.3v. cav ss w30 apwr analog 0 core pll analog ground. connect to ground. mav dd v31 apwr analog 3.3 gliu pll analog power. connect to 3.3v. mav ss v30 apwr analog 0 gliu pll analog ground. connect to ground. vav dd aa1 apwr analog 3.3 video pll analog power. connect to 3.3v. vav ss aa2 apwr analog 0 video pll analog ground. connect to ground. clpf w29 a analog n/a core pll low pass filter. 220 pf to cav ss . mlpf v29 a analog n/a gliu pll low pass filter. 220 pf to mav ss. vlpf aa3 a analog n/a video pll low pass filter. 220 pf to vav ss.
amd geode? lx processors data book 35 signal definitions 33234h 3.4.3 memory interface signals (ddr) signal name ball no. type f v description sdclk[5:0]p, sdclk[5:0]n d20, d21, d23, d24, j28, h28, m28, l28, j4, h4, m4, l4 o up to 200 mhz 2.5 sdram clock differential pairs. the sdram devices sample all the control, address, and data based on these clocks. all clocks are dif- ferential clock outputs. mvref p1 i analog v mem memory voltage reference. this input oper- ates at half the v mem voltage. cke[1:0] f4, e4 i/o up to 200 mb/s 2.5 clock enable. for normal operation, cke is held high. cke goes low during suspend. cke0 is used with cs0# and cs1#. cke1 is used with cs2# and cs3#. cs[3:0]# d30, f29, f28, b28 i/o up to 200 mb/s 2.5 chip selects. the chip selects are used to select the module bank within the system mem- ory. each chip select corresponds to a specific module bank. if cs# is high, the bank(s) do not respond to ras#, cas#, or we# until the bank is selected again. ras[1:0]# d27, c26 i/o up to 200 mb/s 2.5 row address strobe. ras#, cas#, we#, and cke are encoded to support the different sdram commands. ras0# is used with cs0# and cs1#. ras1# is used with cs2# and cs3#. cas[1:0]# e29, e28 i/o up to 200 mb/s 2.5 column address strobe. ras#, cas#, we#, and cke are encoded to support the different sdram commands. cas0# is used with cs0# and cs1#. cas1# is used with cs2# and cs3#. we[1:0]# a28, c27 i/o up to 200 mb/s 2.5 write enable. ras#, cas#, we#, and cke are encoded to support the different sdram commands. we0# is used with cs0# and cs1#. we1# is used with cs2# and cs3#. ba[1:0] c20, d26 i/o up to 200 mb/s 2.5 bank address bits. these bits are used to select the component bank within the sdram. ma[13:0] see table 3-6 on page 30 i/o up to 200 mb/s 2.5 memory address bus. the multiplexed row/ column address lines driven to the system memory. supports 256-mbit sdram. tla[1:0] b13, b15 i/o up to 200 mb/s 2.5 memory debug pins . these pins provide use- ful memory interface debug timing signals. (should be wired to dimm slot.) tla[0] is wired to dqs[8] on the dimm tla[1] is wired to cb[0] on the dimm dqs[7:0] n31, j29, b23, c19, a10, c6, h3, m2 i/o up to 200 mhz 2.5 ddr data strobe.
36 amd geode? lx processors data book signal definitions 33234h dqm[7:0] n30, h29, c24, a19, b10, a6, g2, m1 i/o 166-400 mb/s 2.5 data mask control bits. during memory read cycles, these outputs control whether the sdram output buffers are driven on the mem- ory data bus or not. all dqm signals are asserted during read cycles. during memory write cycles, these outputs con- trol whether or not memory data is written into the sdram. dqm[0] is associat ed with md[7:0]. dqm[7] is associated with md[63:56]. dq[63:0] see table 3-6 on page 30 i/o 166-400 mb/s 2.5 memory data bus. 3.4.3 memory interface signals (ddr) (continued) signal name ball no. type f v description 3.4.4 internal test and measurement interface signals signal name ball no. type f v description tclk ac2 i 0-66 mhz 3.3 test clock. jtag test clock. tms aa4 i 0-66 mb/s 3.3 test mode select. jtag test mode select. tdi ab3 i 0-66 mb/s 3.3 test data input. jtag serial test data input. tdo ac1 o 0-66 mb/s 3.3 test data output. jtag serial test data output. tdbgi ab2 i 0-400 mb/s 3.3 test debug input. the debug management interrupt (dmi) is input via tdbgi. the selects for tdbgi are msr programmable via the glcp module. when using tdbgi for dmi, it cannot be used for other debug purposes. dmi can be setup via the glcp module to be edge sensitive or level sensitive tdbgo ab4 o (pd) 0-400 mb/s 3.3 test debug output. the amd geode lx pro- cessor can output internal clocks on tdbgo. the selects for tdbgo are msr programmable via the glcp module. the internal clock can be selected from any clock domain and may be divided down by 2 or 3 before output. this enables tester and board level visibility of the internal clock quality.
amd geode? lx processors data book 37 signal definitions 33234h 3.4.5 pci interface signals signal name ball no. type f v description ad[31:0] see table 3-6 on page 30 i/o 33-66 mb/s 3.3 multiplexed address and data. addresses and data are multiplexed together on the same pins. a bus transaction consists of an address phase in the cycle in which frame# is asserted fol- lowed by one or more data phases. during the address phase, ad[31:0] contain a physical 32- bit address. during data phases, ad[7:0] contain the least significant byte (lsb) and ad[31:24] contain the most significant byte (msb). write data is stable and valid when irdy# is asserted and read data is stable and valid when trdy# is asserted. data is transferred during the sysref when both irdy# and trdy# are asserted. cbe[3:0]# ah31, ah27, al26, aj22 i/o 33-66 mb/s 3.3 multiplexed command and byte enables. c/ be# are the bus commands and byte enables. during the address phase of a transaction when frame# is active, c/be# define the bus com- mand. during the data phase c/be# are used as byte enables. the byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. c/be0# applies to byte 0 (lsb) and c/be3# applies to byte 3 (msb). the command encoding and types are listed below: 0000: interrupt acknowledge 0001: special cycle 0010: i/o read 0011: i/o write 0100: reserved 0101: reserved 0110: memory read 0111: memory write 1000: reserved 1001: reserved 1010: configuration read 1011: configuration write 1100: memory read multiple 1101: dual address cycle (rsvd) 1110: memory read line 1111: memory write and invalidate par aj27 i/o 33-66 mb/s 3.3 parity. par is used with ad[31:0] and c/be# to generate even parity. parity generation is required by all pci agents: the master drives par for address and write-data phases and the target drives par for read-data phases. for address phases, par is stable and valid one sysref after the address phase. for data phases, par is stable and valid one sysref after either irdy# is asserted on a write transaction or after trdy# is asserted on a read transaction. once par is valid, it remains valid until one sysref after the completion of the data phase.
38 amd geode? lx processors data book signal definitions 33234h reset# y30 i 0-1 mb/s 3.3 pci reset. reset# aborts all operations in progress and places the amd geode lx proces- sor into a reset state. reset# forces the cpu and peripheral functions to begin executing at a known state. all data in the on-chip cache is invalidated upon a reset. reset# is an asynchronous input, but must meet specified setup and hold times to guarantee recognition at a particular clock edge. this input is typically generated during the power-on-reset (por) sequence. stop# aj25 i/o 33-66 mb/s 3.3 target stop. stop# is asserted to indicate that the current target is requ esting the master to stop the current transaction. this signal is used with devsel# to indicate retry, disconnect, or target abort. if stop# is sampled active while a master, frame# is de-asserted and the cycle is stopped within three sysrefs. stop# can be asserted when the pci write buffers are full or a previously buffered cycle has not completed. frame# al28 i/o 33-66 mb/s 3.3 frame. frame# is driven by the current master to indicate the beginning and duration of an access. frame# is asserted to indicate a bus transaction is beginning. while frame# is asserted, data transfers continue. when frame# is de-asserted, the transaction is in the final data phase. irdy# ah25 i/o 33-66 mb/s 3.3 initiator ready. irdy# is asserted to indicate that the bus master is ab le to comple te the cur- rent data phase of the transaction. irdy# is used in conjunction with trdy#. a data phase is com- pleted on any sysref in which both irdy# and trdy# are sampled asserted. during a write, irdy# indicates valid data is present on ad[31:0]. during a read, it indicates the master is prepared to accept data. wait cycles are inserted until both irdy# and trdy# are asserted together. trdy# ak26 i/o 33-66 mb/s 3.3 target ready. trdy# is asserted to indicate that the target agent is able to complete the current data phase of the transaction. trdy# is used in conjunction with irdy#. a data phase is com- plete on any sysref in which both trdy# and irdy# are sampled asserted. during a read, trdy# indicates that valid data is present on ad[31:0]. during a write, it indicates the target is prepared to accept data. wait cycles are inserted until both irdy# and trdy# are asserted together. 3.4.5 pci interface signals (continued) signal name ball no. type f v description
amd geode? lx processors data book 39 signal definitions 33234h devsel# ak25 i/o 33-66 mb/s 3.3 device select. devsel# indicates that the driv- ing device has decoded its address as the target of the current access. as an input, devsel# indicates whether any device on the bus has been selected. devsel# is also driven by any agent that has the abilit y to accept cycles on a subtractive decode basis. as a master, if no devsel# is detected withi n and up to the sub- tractive decode clock, a master abort cycle results, except for special cycles that do not expect a devsel# returned. req[2:0]# ab28, ab31, aa29 i 33-66 mb/s 3.3 request lines. req# indicates to the arbiter that an agent desires use of the bus. each mas- ter has its own req# line. req# priorities are based on the arbitration scheme chosen. req2# is reserved for the interface with the amd geode cs5536 companion device. gnt[2:0]# ac30, ab30, aa28 (strap) i/o 33-66 mb/s 3.3 grant lines. gnt# indicates to the requesting master that it has been granted access to the bus. each master has its own gnt# line. gnt# can be pulled away any time a higher req# is received or if the master does not begin a cycle within a set period of time. gnt# is an output during normal operation. it is an input at reset and functions as a boot strap for frequency selection on a board. it must be pulled high or low to invoke the strap. gnt2# is reserved for the interface with the amd geode cs5536 companion device. 3.4.5 pci interface signals (continued) signal name ball no. type f v description
40 amd geode? lx processors data book signal definitions 33234h 3.4.6 tft display interface signals signal name ball no. type f v description drgb[31:24] drgb[23:0] see table 3-6 on page 30 i/o o (pd) 0-162 mb/s 3.3 display data bus. dotclk ae1 o (pd) 0-162 mhz 3.3 dot clock. output clock from dotclk pll. hsync ae3 o (pd) 0-162 mb/s 3.3 (5vt) horizontal sync. horizontal sync establishes the line rate and horizontal retrace interval for an attached flat panel. the polarity is programmable (see section 6.8.3.43 on page 451, vp memory offset 400h[29]). vsync ad3 o (pd) 0-162 mb/s 3.3 (5vt) vertical sync. vertical sync establishes the screen refresh rate and vertical retrace interval for an attached flat panel. the polarity is pro- grammable (see section 6.8.3.43 on page 451, vp memory offset 400h[30]). dispen ae4 o (pd) 0-162 mb/s 3.3 flat panel backlight enable. vdden ae2 i/o (pd) 0-162 mb/s 3.3 lcd vdd fet control. when this output is asserted high, v dd voltage is applied to the panel. this signal is intended to control a power fet to the lcd panel. the fet may be internal to the panel or not, depending on the panel man- ufacturer. ldemod ad4 i/o (pd) 0-162 mb/s 3.3 flat panel display enable (tft panels). msgstart ah11 i 0-75 mb/s 3.3 message start. used in vip message passing mode to indicate start of message. msgstop aj11 i 0-75 mb/s 3.3 message stop. used in vip message passing mode to indicate end of message. vid[15:8] see table 3-6 on page 30 i (pd) 0-75 mb/s 3.3 video input port data. when in 16 bit vip mode, these are the eight msbs of the vip data. vop[15:0] see table 3-6 on page 30 o 0-75 mb/s 3.3 video output port data. vop output data. vopclk ae1 o 0-75 mhz 3.3 video output port clock. vop_blank ae4 o 0-75 mb/s 3.3 video output port blank. vop_hsync ae3 o 0-75 mb/s 3.3 video output port horizontal sync. vop_vsync ad3 o 0-75 mb/s 3.3 video output port vertical sync.
amd geode? lx processors data book 41 signal definitions 33234h 3.4.7 crt display interface signals signal name ball no. type f v description hsync ae3 i/o 0-350 mb/s 3.3 (5vt) horizontal sync. horizontal sync establishes the line rate and horizontal retrace interval for an attached crt. the polarity is programmable (see section 6.8.3.2 on page 422, vp memory offset 008h[8]). vsync ad3 i/o 0-350 mb/s 3.3 (5vt) vertical sync. vertical sync establishes the screen refresh rate and vertical retrace interval for an attached crt. the polarity is programma- ble (see section 6.8.3.2 on page 422, vp mem- ory offset 008h[9]). dvref w1 a analog 1.235 video dac voltage reference. connect this pin to a 1.235v voltage reference. drset y1 a analog n/a dac current setting resistor. 1.21k, 1% to dav ss . dav dd [3:0] w4, v4, v1, u1 apwr analog 3.3 dac analog power connection. dav ss [3:0] w2, y2, v3, u3 agnd analog 0 dac analog ground connection. red w3 a analog n/a red dac output. red analog output. green v2 a analog n/a green dac output. green analog output. blue u2 a analog n/a blue dac output. blue analog output. 3.4.8 vip interface signals signal name ball no. type f v description vipclk al12 i/o (pd) 0-75 mhz 3.3 video input port clock. vid[7:0] ak12, al13, ak13, aj13, ah13, al15, ak15, aj15 i/o (pd) 0-150 mb/s 3.3 video input port data. vipsync al14 i/o (pd) 0-150 mb/s 3.3 video input port sync signal. vip_hsync ae2 i 0-150 mb/s 3.3 video input port horizontal sync. vip_vsync ad4 i 0-150 mb/s 3.3 video input port vertical sync.
42 amd geode? lx processors data book signal definitions 33234h for additional electrical details on pins, refer to se ction 7.0 "electrical specifications" on page 597. 3.4.9 power and ground interface signals signal name (note 1) ball no. type f v description v core see table 3-6 on page 30 pwr n/a 1.2 core power connection (total of 32). v io see table 3-6 on page 30 pwr n/a 3.3 i/o power connection (total of 30) v mem see table 3-6 on page 30 pwr n/a 2.5 memory power connection (total of 33). v ss see table 3-6 on page 30 gnd n/a 0 ground connection (total of 128). note 1.for module specific power and ground signals see: section 3.4.2 "pll interface signals" on page 34 section 3.4.7 "crt display interface signals" on page 41
amd geode? lx processors data book 43 signal definitions 33234h table 3-7. signal behavior during and after reset signal name type behavior ad[31:0] pci tri-state during reset# low inta# pa r req# irdy# frame# gnt# devsel# trdy# stop# ba[1:0] ddr cas[1:0]# cbe[3:0]# cs[3:0]# dq[63:0] dqm[7:0] dqs[7:0] ma[13:0] ras[1:0]# sdclk[5:0]p sdclk[5:0]n tla[1:0] we[1:0]# tdo debug tdbgo vipsync (pd) vip irq13 system suspa# drgb[31:24] video pd during reset. vsync video driven low during reset# low hsync dispen dotclk drgb[23:0] ldemod vdden cke[1:0]# ddr vid[7:0] (pd) video inputs during reset# low vipclk cis system tdbgi debug tms tdi tclk syref system dotref power-up states after reset# drgb[31:24] video tri-state with pin pd: ? display filter can enable outputs to drive alpha (disables pds). ? vip can enable as inputs (disables pds). drgb[23:0] driven dotclk hsync vsync dispen vdden input with pd ldemod vid[7:0] vipclk vipsync input with pd: ? pd remains if pin is used as input. ? pd disables if vip drives pin. pw[1:0] system tri-state signal name type behavior
44 amd geode? lx processors data book signal definitions 33234h
amd geode? lx processors data book 45 4 geodelink? interface unit 33234h 4.0 geodelink? interface unit many traditional architectures use buses to connect mod- ules together, which usually requires unique addressing for each register in every module. this requires that some kind of house-keeping be done as new modules are designed and new devices are created from the module set. using module select signals to create the unique addresses can get cumbersome and requires that the module selects be sourced from some centralized location. to alleviate this issue, amd developed an internal bus architecture based on geodelink? technology. the geodelink architecture connects the internal modules of a device using the data ports provided by geodelink inter- face units (glius). using glius, all internal module port addresses are derived from the di stinct port that the mod- ule is connected to. in this way, a module?s model specific registers (msrs) do not have unique addresses until a device is defined. also, as defined by the geodelink archi- tecture, a module?s port address depends on the location of the module sourci ng the cycle, or source module (e.g., source module can be cpu core, glcp, and glpci; how- ever, under normal operating conditions, accessing msrs is from the cpu core). 4.1 msr set the amd geode? lx processor incorporates two glius into its device architecture. except for the configuration registers that are required for x86 compatibility, all internal registers are accessed throug h a model specific register (msr) set. msrs have a 32-bit address space and a 64-bit data space. the full 64-bit data space is always read or written when accessed. an msr can be read using the rdmsr instruction, opcode 0f32h. during an msr read, t he contents of the particular msr, specified by the ecx register, are loaded into the edx:eax registers. an msr can be written using the wrmsr instruction, opcode 0f30h. during an msr write, the contents of edx:eax are loaded into the msr speci- fied in the ecx register. the rdmsr and wrmsr instruc- tions are privileged instructions. table 4-1 shows the msr port address to access the mod- ules within the amd geode lx processor with the cpu core as the source module. table 4-1. msr addressing module name gliu port msr address (relative to cpu core) geodelink? interface unit 0 (gliu0) 0 0 1000xxxxh geodelink memory controller (glmc) 0 1 2000xxxxh cpu core (cpu core) 0 3 0000xxxxh display controller (dc) 0 4 8000xxxxh graphics processor (gp) 0 5 a000xxxxh geodelink interface unit 1 (gliu1) 1 0 4000xxxxh video processor (vp) 1 2 4800xxxxh geodelink control processor (glcp) 1 3 4c00xxxxh geodelink pci bridge (glpci) 1 4 5000xxxxh video input port (vip) 1 5 5400xxxxh security block (sb) 1 6 5800xxxxh
46 amd geode? lx processors data book geodelink? interface unit 33234h 4.1.1 port address each gliu has seven channels with channel 0 being the gliu itself and therefore not considered a physical port. figure 4-1 illustrates the geodelink architecture in a amd geode lx processor, showing how the modules are connected to the two glius. gliu0 has five channels con- nected, and gliu1 has six channels connected. to get msr address/data across the pci bus, the glpci converts the msr address into pci cycles and back again. an msr address is parsed into two fields, the port address (18 bits) and the index (14 bits). the port address is further parsed into six 3-bit channel address fields. each 3-bit field represents, from the perspective of the source module, the gliu channels that are used to get to the destination mod- ule, starting from the closest gliu to the source (left most 3-bit field) to the farthest gliu (right most 3-bit field). in an amd geode lx proces sor/cs5536 system, the com- panion device is connected to the processor via the pci bus. the internal architecture of the companion device uses the same geodelink architecture with one gliu being in that device. hence, in a amd geode lx proces- sor/cs5536 system there are a total of three glius: two in the processor and one in the companion device. therefore at most, only the two left mo st 3-bit fields of the base address field should be needed to access any module in the system. there are exceptio ns that require more; see section 4.1.2 "port addressing exceptions" on page 47. for the cpu core to access msr index 300h in the geodelink control processor (glcp) module, the address is 010_011_000_000_000_000b (six channel fields of the port address) + 300h (index), or 4c000300h. the 010b points to channel 2 of gliu0, which is the channel con- nected to gliu1. the 011b points to the gliu1 channel 3, which is the channel to the glcp module. from this point on, the port address is abbreviated by noting each channel address followed by a dot. from the above example, this is represented by 2.3.0.0.0.0. it is important to repeat here that the port address is derived from the perspective of the source module. for a module to access an msr within itself, the port address is zero. figure 4-1. geodelink? architecture glmc cpu core dc gliu1 7 6 1 3 4 5 2 0 gliu0 gp gliu0 1 2 3 5 4 6 7 0 gliu1 glpci glpci pci bus vp glcp vip not used not used sb not used (aes)
amd geode? lx processors data book 47 geodelink? interface unit 33234h 4.1.2 port addressing exceptions there are some exceptions to the port addressing rules. if a module accesses an msr fr om within its closest gliu (e.g., cpu core accessing a gliu0 msr), then, by con- vention, the port address should be 0.0.0.0.0.0. but this port address accesses an msr within the source module and not the gliu as desired. to get around this, if the port address contains a 0 in the first channel field and then con- tains a 1 in any of the other channel fields, the access goes to the gliu nearest the module sourcing the cycle. by con- vention, set the msb of the second channel field, 0.4.0.0.0.0. if the msr access is to a gliu farther removed from the module sourcing the cycle, then there is no con- vention conflict, so no exception is required for that situa- tion. if a module attempts to acce ss an msr to the channel that it is connected to, a gliu error results. this is called a reflective address attempt. an example of this case is the cpu core accessing 3.0.0.0.0.0. since the cpu core is connected to channel 3 of gliu0, the access causes a reflective address error. this exception is continued to the next gliu in the chain. the cpu core accessing 2.1.0.0.0.0 also causes a reflective address error. to access modules in the amd geode companion device, the port address must go through the glpci (pci control- ler) in the processor and through the glpci in the compan- ion device. the port address of the msrs in the processor?s glpci when accessed from the cpu core is 2.4.0.0.0.0. to get the port address to go through the glpci, the third field needs a non-zero value. by conven- tion, this is a 2. we now have a port address of 2.4.2.0.0.0. but this accesses the msrs in the glpci in the compan- ion device. the port to be accessed must be added in the fourth field, 2.4.2.5.0.0, to access the ac97 audio bus mas- ter, for example. to access the gliu in th e companion device, the same addressing exception occurs as with gliu0 due to the glpci?s address. a port addre ss of 2.4.2.0.0.0 accesses the companion device?s glpci, not the gliu. to solve this, a non-zero value must be in at least one of the two right- most port fields. by convention, a 4 in the left-most port field is used. to access the companion device?s gliu from the cpu core, the port address is 2.4.2.0.0.4. table 4-2 shows the msr port address to access all the modules in a amd geode lx processor/cs5536 system with the cpu core as the source module. included in the table is the msr port address for module access using the glcp and glpci as the source module. however, under normal operating conditions, accessing msrs is from the cpu core. therefore, all msr addresses in the following chapters of this data book are documented using the cpu core as the source. 4.1.3 memory and i/o mapping the gliu decodes the destination id of memory requests using a series of physical to device (p2d) descriptors. there can be up to 32 descriptors in each gliu. the gliu decodes the destination id of i/o requests using a series of i/o descriptors (iod). 4.1.3.1 memory routin g and translation memory addresses are routed and optionally translated from physical space to device space. physical space is the 32-bit memory address space that is shared between all geodelink devices. device space is the unique address space within a given device. for example, a memory con- troller may implement a 4 mb frame buffer region in the 12- 16 mb range of main memory. however, the 4 mb region may exist in the 4 gb region of physical space. the actual location of the frame buffer in the memory controller with respect to itself is a device address, while the address that all the devices see in the region of memory is in physical space. memory request routing and translation is performed with a choice of five descriptor types. each gliu may have any number of each descriptor type up to a total of 32. the p2d descriptor types satisfy different needs for various software models. table 4-2. msr mapping destination source (note 1) note 1. the xxxx contains the lowe r two bits of the 18 bits from the port fields plus the 14-bit msr offset. cpu core glcp glpci cpu core 0000xxxxh 2c00xxxxh 2c00xxxxh gliu0 1000xxxxh 2000xxxxh 2000xxxxh glmc 2000xxxxh 2400xxxxh 2400xxxxh gliu1 4000xxxxh 1000xxxxh 1000xxxxh glcp 4c00xxxxh 0000xxxxh 6000xxxxh glpci 5000xxxxh 8000xxxxh 0000xxxxh dc 8000xxxxh 3000xxxxh 3000xxxxh gp a000xxxxh 3400xxxxh 3400xxxxh vp 4800xxxxh 4000xxxxh 3800xxxxh vip 5400xxxxh security block 5800xxxxh companion device 51y0xxxxh (note 2) note 2. y is the hex value obtained from one bit (always a 0) plus the port number (#) of the six port field addresses [0+#]. example: # = 5, therefore the y value is [0+101] which is 5h, thus the address = 5150xxxxh. 8zk0xxxxh (note 3) note 3. zk are the hex values obtained from the concatenation of [10+#+000], where # is the port number from the six port field address. example # = 5, the zk value is [10+101+000] which is [1010,1000]. in hex. it is a8h; thus the address is 8a80xxxxh. na
48 amd geode? lx processors data book geodelink? interface unit 33234h each memory request is compared against all the p2d descriptors. if the memory request does not hit in any of the descriptors, the request is sent to the subtractive port. if the memory requests hit more than one descriptor, the results are undefined. the soft ware must provide a consis- tent non-overlapping address map. the way each descriptor checks if the request address hits its descriptor and how to route the request address to the device address is described in table 4-3. p2d base mask descriptor (p2d_bm) p2d_bm is the simplest descriptor. it usually maps a power of two size aligned region of memory to a destination id. p2d_bm performs no address translation. p2d base mask offset descriptor (p2d_bmo) p2d_bmo has the same routi ng features as p2d_bm with the addition of a 2s complement address translation to the most-significant bits of the address. p2d range descriptor (p2d_r) p2d_r maps a range of addresses to a device that is not a power of 2 size aligned. there is no address translation (see table 4-3). p2d range offset descriptor (p2d_ro) p2d_ro has the same address routing as p2d_r with the addition of address translatio n with a 2s complement off- set. p2d swiss cheese descriptor (p2d_sc) the p2d_sc maps a 256 kb region of memory in 16 kb chunks to a device or the subtractive decode port. the descriptor type is useful fo r legacy address mapping. the swiss cheese feature implies that the descriptor is used to ?poke holes? in memory. note: only one p2d can hit at a time for a given port. if the p2d descriptors are overlapping, the results are undefined. table 4-3. gliu memory descriptor address hit and routing description descriptor function description p2d_bm, p2d_bmo checks that the physical address suppl ied by the device?s request on address bits [31:12] with a logical and with pmask bits of the descriptor register bits [19:0] are equal to the pbase bits on the descriptor register (bits [39:20]). also checks that the bizzaro bit of the request is equal to the pcmp_biz bit of the descriptor register bit [60]. if the above matches, then the descriptor has a hit condition and it routes the received address to the programmed des- tination pdid1 of the descriptor register (bits [63:61]). for p2d_bm: device_addr = request address for p2d_bmo: device_addr [31:12] = [request address [31:12] + descriptor poffset] device_addr [11:0] = request address [11:0] p2d_r, p2d_ro checks that the physical address supplie d by the device?s request on address bi ts [31:12] are within the range speci- fied by pmin and pmask field bits [39:20] and [19:0], respecti ve of the descriptor register. pmin is the minimum address range and pmax is the maximum address range.the condi tion is: pmax > physical address [31:12] > pmin. also checks that the bizzaro bit of the request is equal to the pcmp_biz bit of the descriptor register bit [60]. if the above matches, then the descriptor has a hit conditi on and routes the received address to the programmed des- tination id, pdid1 of the descriptor register (bits [63:61]). for p2d_r: device_addr = request address for p2d_ro: device_addr [31:12] = [request address [31:12] + descriptor poffset] device_addr [11:0] = request address [11:0] p2d_sc checks that the physical address supplied by the device ?s request on address bits [31:18] are equal to the pbase field of descriptor register bits [13:0] and that the enable write or read conditions given by the descriptor register fields wen and ren in bits [47:32] and [31:16], respectively matches the request type and enable fields given on the physical address bits [17:14] of the device?s request. if the above matches, then the descriptor has a hit conditi on and routes the received address to the programmed des- tination id, pdid1 field of the descriptor register bits [63:61]. device_addr = request address
amd geode? lx processors data book 49 geodelink? interface unit 33234h 4.1.3.2 i/o routing and translation i/o addresses are routed and are never translated. i/o request routing is performed wit h a choice of two descriptor types. each gliu may have any number of each descriptor type. the iod types satisfy diff erent needs for various soft- ware models. each i/o request is compared against all the iod. if the i/o request does not hit in any of the descriptors, the request is sent to the subtractive port. if the i/o request hits more than one descriptor, the results are undefined. software must provide a consistent non-overlapping i/o address map. the methods of check and routing are described in table 4-4. iod base mask descriptors (iod_bm) iod_bm is the simplest descri ptor. it usually maps a power of two size aligned region of i/o to a destination id. iod swiss cheese descriptors (iod_sc) the iod_sc maps an 8-byte region of memory in 1 byte chunks to one of two devices. the descriptor type is useful for legacy address mapping. the swiss cheese feature implies that the descriptor is used to ?poke holes? in i/o. 4.1.3.3 special cycles pci special cycles are performed using i/o writes and set- ting the bizarro flag in the write request. the bizarro flag is treated as an additional address bit, providing unaliased i/o address. the i/o descriptors are set up to route the special cycles to th e appropriate device (i.e., glcp, glpci, etc.). the i/o descriptors are configured to default to the appropriate device on reset. the pci special cycles are mapped as: name bizzaro address shutdown 1 00000000h halt 1 00000001h x86 specific 1 00000002h 0003h-ffffh 1 00000002h-0000ffffh table 4-4. gliu i/o descriptor address hit and routing description descriptor function description iod_bm checks that the physical address supplied by the device on address bits [31:12] with a logic and with pmask bits of the register bits [19:0] are equal to the pbase bi ts of the descriptor register bits [39:20]. also checks that the bizzaro bit of the request is equal to the pcmp_piz bit of the descriptor register bit [60]. if the above matches, then the descriptor has a hit conditi on and routes the received address to the programmed des- tination of the p2d_bm register bit [63:61]. device_addr = request address iod_sc checks that the physical address supplied by the device ?s request on address bits [31:18] are equal to the pbase field of descriptor register bits [13:0] and that the enable write or read conditions given by the descriptor register fields wen and ren in bits [47:32] and [31:16], respectively matches the request type and enable fields given on the physical address bits [17:14] of the device?s request. if the above matches, then the descriptor has a hit conditi on and routes the received address to the programmed des- tination id, pdid1 field of the descriptor register bits [63:61]. device_addr = request address
50 amd geode? lx processors data book gliu register descriptions 33234h 4.2 gliu regist er descriptions all geodelink? interface unit (gliu) registers are model specific registers (msrs) a nd are accessed through the rdmsr and wrmsr instructions. the registers associated wit h the gliu are the standard geodelink device (gld) msrs, gliu specific msrs. gliu statistic and comparator msrs, p2d descriptor msrs, and i/o descriptor msrs. the tables that follow are register summary tables that include reset values and page references where the bit descriptions are provided. note: the msr address is derived from the perspective of the cpu core. see section 4.1 "msr set" on page 45 for more details on msr addressing. reserved (rsvd) fields do not have any meaningful stor- age elements. they always return 0. table 4-5. geodelink? devi ce standard msrs summary msr address type register name reset value reference gliu0: 10002000h gliu1: 40002000h ro gld capabilities msr (gld_msr_cap) 00000000_000014xxh page 55 gliu0: 10002001h gliu1: 40002001h r/w gld master configuration msr (gld_msr_config) gliu0: 00000000_00000002h gliu1: 00000000_00000004h page 55 gliu0: 10002002h gliu1: 40002002h r/w gld smi msr (gld_msr_smi) 00000000_00000001h page 56 gliu0: 10002003h gliu1: 40002003h r/w gld error msr (gld_msr_error) 00000000_00000000h page 57 gliu0: 10002004h gliu1: 40002004h r/w gld power management msr (gld_msr_pm) 00000000_00000000h page 59 gliu0: 10002005h gliu1: 40002005h r/w gld diagnostic msr (gld_msr_diag) 00000000_00000000h page 60 table 4-6. gliu specific msrs summary msr address type register name reset value reference gliu0: 10000080h gliu1: 40000080h r/w coherency (coh) configuration dependent page 60 gliu0: 10000081h gliu1: 40000081h r/w port active enable (pae) boot strap dependent page 61 gliu0: 10000082h gliu1: 40000082h r/w arbitration (arb) 10000000_00000000h page 62 gliu0: 10000083h gliu1: 40000083h r/w asynchronous smi (asmi) 00000000_00000000h page 62 gliu0: 10000084h gliu1: 40000084h r/w asynchronous err (aerr) 00000000_00000000h page 63 gliu0: 10000086h gliu1: 40000086h r/w gliu physical capabilities (phy_cap) gliu0: 20291830_010c1086h gliu1: 20311030_0100400ah page 65 gliu0: 10000087h gliu1: 40000087h ro n outstanding response (nout_resp) 00000000_00000000h page 66 gliu0: 10000088h gliu1: 40000088h ro n outstanding write data (nout_wdata) 00000000_00000000h page 67
amd geode? lx processors data book 51 gliu register descriptions 33234h gliu0: 10000089h gliu1: 40000089h ro slave_only gliu0: 00000000_00000010h gliu1: 00000000_00000100h page 67 gliu0: 1000008ah gliu1: 4000008ah ro reserved --- --- gliu0: 1000008bh gliu1: 4000008bh ro who am i (whoami) configuration dependent page 68 gliu0: 1000008ch gliu1: 4000008ch r/w gliu slave disable (gliu_slv) 00000000_00000000h page 69 gliu0: 1000008dh gliu1: 4000008dh r/w arbitration2 (arb2) 00000000_00000000h page 70 table 4-6. gliu specific msrs summary (continued) msr address type register name reset value reference table 4-7. gliu statistic and comparator msrs summary msr address type register reset value reference gliu0: 100000a0h gliu1: 400000a0h wo descriptor statistic counter (statistic_cnt[0]) 00000000_00000000h page 71 gliu0: 100000a1h gliu1: 400000a1h r/w descriptor statistic mask (statistic_mask[0]) 00000000_00000000h page 72 gliu0: 100000a2h gliu1: 400000a2h r/w descriptor statistic action (statistic_action[0]) 00000000_00000000h page 73 gliu0: 100000a3h gliu1: 400000a3h -- reserved -- -- gliu0: 100000a4h gliu1: 400000a4h wo descriptor statistic counter (statistic_cnt[1]) 00000000_00000000h page 71 gliu0: 100000a5h gliu1: 400000a5h r/w descriptor statistic mask (statistic_mask[1]) 00000000_00000000h page 72 gliu0: 100000a6h gliu1: 400000a6h r/w descriptor statistic action (statistic_action[1]) 00000000_00000000h page 73 gliu0: 100000a7h gliu1: 400000a7h -- reserved -- -- gliu0: 100000a8h gliu1: 400000a8h wo descriptor statistic counter (statistic_cnt[2]) 00000000_00000000h page 71 gliu0: 100000a9h gliu1: 400000a9h r/w descriptor statistic mask (statistic_mask[2]) 00000000_00000000h page 72 gliu0: 100000aah gliu1: 400000aah r/w descriptor statistic action (statistic_action[2]) 00000000_00000000h page 73 gliu0: 100000abh gliu1: 40000abh -- reserved -- -- gliu0: 100000ach gliu1: 400000ach wo descriptor statistic counter (statistic_cnt[3]) 00000000_00000000h page 71 gliu0: 100000adh gliu1: 400000adh r/w descriptor statistic mask (statistic_mask[3]) 00000000_00000000h page 72 gliu0: 100000aeh gliu1: 400000aeh r/w descriptor statistic action (statistic_action[3]) 00000000_00000000h page 73
52 amd geode? lx processors data book gliu register descriptions 33234h gliu0: 100000c0h gliu1: 400000c0h r/w request compare value (rq_compare_val[0]) 001fffff_fff fffffh page 74 gliu0: 100000c1h gliu1: 400000c1h r/w request compare mask (rq_compare_mask[0]) 00000000_00000000h page 75 gliu0: 100000c2h gliu1: 400000c2h r/w request compare value (rq_compare_val[1]) 001fffff_fff fffffh page 74 gliu0: 100000c3h gliu1: 400000c3h r/w request compare mask (rq_compare_mask[1]) 00000000_00000000h page 75 gliu0: 100000c4h gliu1: 400000c4h r/w request compare value (rq_compare_val[2]) 001fffff_fff fffffh page 74 gliu0: 100000c5h gliu1: 400000c5h r/w request compare mask (rq_compare_mask[2]) 00000000_00000000h page 75 gliu0: 100000c6h gliu1: 400000c6h r/w request compare value (rq_compare_val[3]) 001fffff_fff fffffh page 74 gliu0: 100000c7h gliu1: 400000c7h r/w request compare mask (rq_compare_mask[3]) 00000000_00000000h page 75 gliu0: 100000c9h gliu1: 400000cfh -- reserved -- -- gliu0: 100000d0h gliu1: 400000d0h r/w data compare value low (da_compare_val_lo[0]) 00001fff_ffffffffh page 76 gliu0: 100000d1h gliu1: 400000d1h r/w data compare value high (da_compare_val_hi[0]) 0000000f_ffffffffh page 77 gliu0: 100000d2h gliu1: 400000d2h r/w data compare mask low (da_compare_mask_lo[0]) 00000000_00000000h page 78 gliu0: 100000d3h gliu1: 400000d3h r/w data compare mask high (da_compare_mask_hi[0]) 00000000_00000000h page 79 gliu0: 100000d4h gliu1: 400000d4h r/w data compare value low (da_compare_val_lo[1]) 00001fff_ffffffffh page 76 gliu0: 100000d5h gliu1: 400000d5h r/w data compare value high (da_compare_val_hi[1]) 0000000f_ffffffffh page 77 gliu0: 100000d6h gliu1: 400000d6h r/w data compare mask low (da_compare_mask_lo[1]) 00000000_00000000h page 78 gliu0: 100000d7h gliu1: 400000d7h r/w data compare mask high (da_compare_mask_hi[1]) 00000000_00000000h page 79 gliu0: 100000dbh gliu1: 400000dbh r/w data compare value low (da_compare_val_lo[2]) 00000000_00000000h page 79 gliu0: 100000d9h gliu1: 400000d9h r/w data compare value high (da_compare_val_hi[2]) 0000000f_ffffffffh page 77 gliu0: 100000dah gliu1: 400000dah r/w data compare mask low (da_compare_mask_lo[2]) 00000000_00000000h page 78 gliu0: 100000dbh gliu1: 400000dbh r/w data compare mask high (da_compare_mask_hi[2]) 00000000_00000000h page 79 gliu0: 100000dch gliu1: 400000dch r/w data compare value low (da_compare_val_lo[3]) 00001fff_ffffffffh page 76 gliu0: 100000ddh gliu1: 400000ddh r/w data compare value high (da_compare_val_hi[3]) 0000000f_ffffffffh page 77 table 4-7. gliu statistic and comparator msrs summary (continued) msr address type register reset value reference
amd geode? lx processors data book 53 gliu register descriptions 33234h gliu0: 100000deh gliu1: 400000deh r/w data compare mask low (da_compare_mask_lo[3]) 00000000_00000000h page 78 gliu0: 100000dfh gliu1: 400000dfh r/w data compare mask high (da_compare_mask_hi[3]) 00000000_00000000h page 79 table 4-7. gliu statistic and comparator msrs summary (continued) msr address type register reset value reference table 4-8. gliu p2d descriptor msrs summary msr address type register reset value reference gliu0 10000020h- 10000025h r/w p2d base mask descriptor (p2d_bm): p2d_bm[5:0] 000000ff_fff00000h page 80 10000026h- 10000027h r/w p2d base mask offset descriptor (p2d_bmo): p2d_bmo[1:0] 00000ff0_fff00000h page 81 10000028h r/w p2d range descriptor (p2d_r: p2d_r[0] 00000000_000fffffh page 82 10000029h- 1000002bh r/w p2d range offset descriptor (p2d_ro): p2d_ro[2:0] 00000000_000fffffh page 83 1000002ch r/w p2d swiss cheese descriptor (p2d_sc): p2d_sc[0] 00000000_00000000h page 84 1000002dh- 1000003fh r/w p2d reserved descriptors --- --- gliu1 40000020h- 40000029h r/w p2d base mask descriptor (p2d_bm): p2d_bm[9:0] 000000ff_fff00000h page 80 4000002ah- 4000002dh r/w p2d range descriptor (p2d_r): p2d_r[3:0] 00000000_000fffffh page 82 4000002eh r/w p2d swiss cheese descriptor (p2d_sc): p2d_sc[0] 00000000_00000000h page 84 4000002fh- 4000003fh r/w p2d reserved descriptor (p2d_rsvd) 00000000_00000000h --- table 4-9. gliu reserved msrs summary msr address type register reset value reference gliu0: 10000006h- 1000000fh gliu1: 40000006h- 4000000fh r/w reserved for future use by amd. 00000000_00000000h --- gliu0: 10000040h- 1000004fh gliu1: 40000040h- 4000004fh r/w reserved for future use by amd. 00000000_00000000h --- gliu0: 10000050h- 1000007fh gliu1: 40000050h- 4000007fh r/w reserved for future use by amd. 00000000_00000000h ---
54 amd geode? lx processors data book gliu register descriptions 33234h table 4-10. gliu iod descriptor msrs summary msr address type register reset value reference gliu0 100000e0h- 100000e2h r/w iod base mask descriptor s (iod_bm) 000000ff_fff00000h page 86 100000e3h- 100000e8h r/w iod swiss cheese descriptors (iod_sc) 00000000_00000000h page 87 100000e9h- 100000ffh r/w iod reserved descriptors --- --- gliu1 400000e0h- 400000e2h r/w iod base mask descriptor s (iod_bm) 000000ff_fff00000h page 86 400000e3h- 400000e6h r/w iod swiss cheese descriptors (iod_sc) 00000000_00000000h page 87 400000e7h- 400000ffh r/w iod reserved descriptors --- ---
amd geode? lx processors data book 55 gliu register descriptions 33234h 4.2.1 standard geodelink? device (gld) msrs 4.2.1.1 gld capabilities msr (gld_msr_cap) 4.2.1.2 gld master configur ation msr (gld_msr_config) msr address gliu0: 10002000h gliu1: 40002000h ty p e r o reset value 00000000_000014xxh gld _msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id gld _msr_cap bit descriptions bit name description 63:24 rsvd reserved. 23:8 dev_id device id. identifies device (0014h). 7:0 rev_id revision id. identifies device revision. see amd geode? lx processors specification update document for value msr address gliu0: 10002001h gliu1: 40002001h ty p e r / w reset value gliu0: 00000000_00000002h gliu1: 00000000_00000004h gld _msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 subp gld _msr_config bit descriptions bit name description 63:3 rsvd reserved. 2:0 subp subtractive port. subtractive port assignment for all negative decode requests. 000: port 0 (gliu0 = gliu; gliu1 = gliu) 001: port 1 (gliu0 = glmc; gliu1 = interface to gliu0) 010: port 2 (gliu0 = interface to gliu1; gliu1 = vp) 011: port 3 (gliu0 = cpu core; gliu1 = glcp) 100: port 4 (gliu0 = dc; gliu1 = glpci) 101: port 5 (gliu0 = gp; gliu1 = vip) 110: port 6 (gliu0 = not used; gliu1 = sb) 111: port 7 (gliu0 = not used; gliu1 = not used)
56 amd geode? lx processors data book gliu register descriptions 33234h 4.2.1.3 gld smi msr (gld_msr_smi) the flags are set with internal conditions. the internal conditio ns are always capable of setting the flag, but if the mask is 1, the flagged condition will not trigger the smi signal. reads to t he flags return the value. write = 1 to the flag, clears the value. write = 0 has no effect on the flag. msr address gliu0: 10002002h gliu1: 40002002h ty p e r / w reset value 00000000_00000001h gld _msr_smi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd sflag4 sflag3 sflag2 sflag1 sflag0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd smask4 smask3 smask2 smask1 smask0 gld _msr_smi bit descriptions bit name description 63:37 rsvd reserved. 36 sflag4 smi flag4. if high, records that an smi was generated due to a statistic counter 3 (gliu0 msr 100000ach, gliu1 msr 400000ach) event. write 1 to clear; writing 0 has no effect. smask4 (bit 4) must be low to generate smi and set flag. 35 sflag3 smi flag3. if high, records that an smi was generated due to a statistic counter 2 (gliu0 msr 100000a8h, gliu1 msr 400000a8h) event. write 1 to clear; writing 0 has no effect. smask3 (bit 3) must be low to generate smi and set flag. 34 sflag2 smi flag2. if high, records that an smi was generated due to a statistic counter 1 (gliu0 msr 100000a4h, gliu1 msr 400000a4h) event. write 1 to clear; writing 0 has no effect. smask2 (bit 2) must be low to generate smi and set flag. 33 sflag1 smi flag1. if high, records that an smi was generated due to a statistic counter 0 (gliu0 msr 100000a0h, gliu1 msr 400000a0h) event. write 1 to clear; writing 0 has no effect. smask1 (bit 1) must be low to generate smi and set flag. 32 sflag0 smi flag0. unexpected type (hw emulation). 31:5 rsvd reserved. 4 smask4 smi mask4. write 0 to enable sflag4 (bit 37) and to allow a statistic counter 3 (gliu0 msr 100000ach, gliu1 msr 400000ach) event to generate an smi. 3 smask3 smi mask3. write 0 to enable sflag3 (bit 36) and to allow a statistic counter 2 (gliu0 msr 100000a8h, gliu1 msr 400000a8h) event to generate an smi. 2 smask2 smi mask2. write 0 to enable sflag2 (bit 34) and to allow a statistic counter 1 (gliu0 msr 100000a4h, gliu1 msr 400000a4h) event to generate an smi. 1 smask1 smi mask1. write 0 to enable sflag1 (bit 33) and to allow a statistic counter 0 (gliu0 msr 100000a0h, gliu1 msr 400000a0h) event to generate an smi. 0 smask0 smi mask0. unexpected type (hw emulation).
amd geode? lx processors data book 57 gliu register descriptions 33234h 4.2.1.4 gld error msr (gld_msr_error) the flags are set with internal conditions. the internal conditio ns are always capable of setting the flag, but if the mask is 1, the flagged condition will not trigger the err signal. reads to the flags return the value. write = 1 to the flag, clears the value. write = 0 has no effect on the flag. msr address gliu0: 10002003h gliu1: 40002003h ty p e r / w reset value 00000000_00000000h gld _msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd eflag14 eflag13 eflag12 eflag11 eflag10 eflag9 eflag8 eflag7 eflag6 eflag5 eflag4 eflag3 eflag2 eflag1 eflag0 313029282726252423222120191817161514131211109876543210 rsvd emask14 emask13 emask12 emask11 emask10 emask9 emask8 emask7 emask6 emask5 emask4 emask3 emask2 emask1 emask0 gld _msr_error bit descriptions bit name description 63:47 rsvd reserved. 46 eflag14 data comparator error flag 3 . if high, records that an err was generated due to a data comparator 3 (da_compare_val_lo3/da_compare_val_hi3, gliu0 msr 100000dch/100000ddh, gliu1 msr 400000dch/400000ddh) event. write 1 to clear; writing 0 has no effect. emask14 (bit 14) mu st be low to generate err and set flag. 45 eflag13 data comparator error flag 2. if high, records that an err was generated due to a data comparator 2 (da_compare_val_lo2/da_compare_val_hi2, gliu0 msr 100000d8h/100000d9h, gliu1 msr 400000d8h/400000d9h) event. write 1 to clear; writing 0 has no effect. emask13 (bit 13) mu st be low to generate err and set flag. 44 eflag12 data comparator error flag 1. if high, records that an err was generated due to a data comparator 1 (da_compare_val_lo1/da_compare_val_hi1, gliu0 msr 100000d4h/100000d5h, gliu1 msr 400000d4h/400000d5h) event. write 1 to clear; writing 0 has no effect. emask12 (bit 12) mu st be low to generate err and set flag. 43 eflag11 data comparator error flag 0. if high, records that an err was generated due to a data comparator 0 (da_compare_val_lo0/da_compare_val_hi0, gliu0 msr 100000d0h/100000d1h, gliu1 msr 400000d0h/400000d1h) event. write 1 to clear; writing 0 has no effect. emask11(bit 11) mu st be low to generate err and set flag. 42 eflag10 request comparator error flag 3 . if high, records that an err was generated due to a request comparator 3 (rq_compare_val3, gliu0 msr 100000c6h, gliu1 msr 400000c6h) event. write 1 to clear; writing 0 has no effect. emask1 0 (bit 10) must be low to generate err and set flag. 41 eflag9 request comparator error flag 2. if high, records that an err was generated due to a request comparator 2 (rq_compare_val2, gliu0 msr 100000c4h, gliu1 msr 400000c4h) event. write 1 to clear; writing 0 has no effect. emask9 (bit 9) must be low to generate err and set flag. 40 eflag8 request comparator error flag 1. if high, records that an err was generated due to a request comparator 1 (rq_compare_val1, gliu0 msr 100000c2h, gliu1 msr 400000c2h) event. write 1 to clear; writing 0 has no effect. emask8 (bit 8) must be low to generate err and set flag.
58 amd geode? lx processors data book gliu register descriptions 33234h 39 eflag7 request comparator error flag 0. if high, records that an err was generated due to a request comparator 0 (rq_compare_val0, gliu0 msr 100000c0h, gliu1 msr 400000c0h) event. write 1 to clear; writing 0 has no effect. emask7 (bit 7) must be low to generate err and set flag. 38 eflag6 statistic counter error flag 3. if high, records that an err was generated due to a statistic counter 3 (gliu0 msr 100000ach, gliu1 msr 400000ach) event. write 1 to clear; writing 0 has no effect. emask6 (bit 6) must be low to generate err and set flag. 37 eflag5 statistic counter error flag 2 . if high, records that an err was generated due to a statistic counter 2 (gliu0 msr 100000a8h, gliu1 msr 400000a8h) event. write 1 to clear; writing 0 has no effect. emask5 (bit 5) must be low to generate err and set flag. 36 eflag4 statistic counter error flag 1. if high, records that an err was generated due to a statistic counter 1 (gliu0 msr 100000a4h, gliu1 msr 400000a4h) event. write 1 to clear; writing 0 has no effect. emask4 (bit 4) must be low to generate err and set flag. 35 eflag3 statistic counter error flag 0. if high, records that an err was generated due to a statistic counter 0 (gliu0 msr 100000a0h, gliu1 msr 400000a0h) event. write 1 to clear; writing 0 has no effect. emask3 (bit 3) must be low to generate err and set flag. 34 eflag2 unhandled smi error flag. if high, records that an err was generated due an unhan- dled ssmi (synchronous error). write 1 to cl ear; writing 0 has no effect. emask2 (bit 2) must be low to generate err and set flag unhandled smi. 33 eflag1 unexpected address error flag. if high, records that an err was generated due an unexpected address (synchronous error). writ e 1 to clear; writing 0 has no effect. emask1 (bit 1) must be low to generate err and set flag. 32 eflag0 unexpected type error flag. if high, records that an err was generated due an unex- pected type (synchronous error). write 1 to cl ear; writing 0 has no effect. emask0 (bit 0) must be low to generate err and set flag. 31:15 rsvd reserved. 14 emask14 data comparator error mask 3. write 0 to enable eflag14 (bit 46) and to allow a data comparator 3 (da_compare_val_lo3/da_compare_val_hi3, gliu0 msr 100000dch/100000ddh, gliu1 msr 400000dch/400000ddh) event to generate an err and set flag. 13 emask13 data comparator error mask 2. write 0 to enable eflag13 (bit 45) and to allow a data comparator 2 (da_compare_val_lo2/da_compare_val_hi2, gliu0 msr 100000d8h/100000d9h, gliu1 msr 400000d 8h/400000d9h) event to generate an err and set flag. 12 emask12 data comparator error mask 1. write 0 to enable eflag12 (bit 44) and to allow a data comparator 1 (da_compare_val_lo1/da_compare_val_hi1, gliu0 msr 100000d4h/100000d5h, gliu1 msr 400000d 4h/400000d5h) event to generate an err and set flag. 11 emask11 data comparator error mask 0. write 0 to enable eflag11 (bit 43) and to allow a data comparator 0 (da_compare_val_lo0/da_compare_val_hi0, gliu0 msr 100000d4h/100000d5h, gliu1 msr 400000d 4h/400000d5h) event to generate an err and set flag. 10 emask10 request comparator error mask 3. write 0 to enable eflag10 (bit 42) and to allow a request comparator 3 (rq_compare_val3, gliu0 msr 100000c6h, gliu1 msr 400000c6h) event to generate an err 9 emask9 request comparator error mask 2 . write 0 to enable eflag9 (bit 41) and to allow a request comparator 2 (rq_compare_val2, gliu0 msr 100000c4h, gliu1 msr 400000c4h) event to generate an err. gld _msr_error bit descriptions (continued) bit name description
amd geode? lx processors data book 59 gliu register descriptions 33234h 4.2.1.5 gld power management msr (gld_msr_pm) 8 emask8 request comparator error mask 1 . write 0 to enable eflag8 (bit 40) and to allow a request comparator 1 (rq_compare_val1, gliu0 msr 100000c2h, gliu1 msr 400000c2h) event to generate an err 7 emask7 request comparator error mask 0 . write 0 to enable eflag7 (bit 39) and to allow a request comparator 0 (rq_compare_val0, gliu0 msr 100000c0h, gliu1 msr 400000c0h) event to generate an err 6 emask6 statistic counter error mask 3 . write 0 to enable eflag6 (bit 38) and to allow a statis- tic counter 3 (gliu0 msr 100000ach, gliu1 msr 400000ach) event to generate an err. 5 emask5 statistic counter error mask 2 . write 0 to enable eflag5 (bit 37) and to allow a statis- tic counter 2 (gliu0 msr 100000a8h, gliu 1 msr 400000a8h) event to generate an err. 4 emask4 statistic counter error mask 1 . write 0 to enable eflag4 (bit 36) and to allow a statis- tic counter 1 (gliu0 msr 100000a4h, gliu 1 msr 400000a4h) event to generate an err. 3 emask3 statistic counter error mask 0 . write 0 to enable eflag3 (bit 35) and to allow a statis- tic counter 0 (gliu0 msr 100000a0h, gliu 1 msr 400000a0h) event to generate an err. 2 emask2 unhandled smi error mask 2. write 0 to enable eflag2 (bit 34) and to allow the unhandled ssmi (synchronous error) event to generate an err. 1 emask1 unexpected address error mask 1. as write 0 to enable eflag1 (bit 33) and to allow the unexpected address (synchronous error) event to generate an err. 0 emask0 unexpected type error mask 0. write 0 to enable eflag0 (bit 32) and to allow the unexpected type (synchronous error) event to generate an err. msr address gliu0: 10002004h gliu1: 40002004h ty p e r / w reset value 00000000_00000000h gld _msr_error bit descriptions (continued) bit name description gld _msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pmode_1 pmode_0
60 amd geode? lx processors data book gliu register descriptions 33234h 4.2.1.6 gld diagnostic msr (gld_msr_diag) this register is reserved for internal use by amd and should not be written to. 4.2.2 gliu specific registers 4.2.2.1 coherency (coh) gld _msr_pm bit descriptions bit name description 63:4 rsvd reserved. 3:2 pmode_1 power mode 1. statistics and time slice counters. 00: disable clock gating. clocks are always on. 01: enable hardware clock gating. clock goes off whenever this module?s circuits are not busy. 10, 11: reserved. 1:0 pmode_0 power mode 0. online gliu logic. 00: disable clock gating. clocks are always on. 01: enable hardware clock gating. clock goes off whenever this module?s circuits are not busy. 10, 11: reserved. msr address gliu0: 10002005h gliu1: 40002005h ty p e r / w reset value 00000000_00000000h msr address gliu0: 10000080h gliu1: 40000080h ty p e r / w reset value configuration dependent coh register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd cohp coh bit descriptions bit name description 63:3 rsvd reserved. 2:0 cohp coherent device port. the port that coherents snoops are routed to. if the coherent device is on the other side of a bridge, the cohp points to the bridge.
amd geode? lx processors data book 61 gliu register descriptions 33234h 4.2.2.2 port active enable (pae) ports that are not implemented return 00 (rsvd). ports that are slave only return 11. master/slave ports return the values as stated. gliu0 will reset all pae to 11 (on) except that gliu0 pae3 re sets to 00 when the debug stall bootstrap is active (cpu port resets inactive for debug stall). msr address gliu0: 10000081h gliu1: 40000081h ty p e r / w reset value boot strap dependent pae register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pae0 pae7 pae6 pae5 pae4 pae3 pae2 pae1 pae bit descriptions bit name description 63:16 rsvd reserved. 15:14 pae0 port active enable for port 0. (gliu0 = gliu; gliu1 = gliu.) 00: off - master transactions are disabled. 01: low - master transactions limited to 1 outstanding transaction. 10: reserved. 11: on - master transactions enabled with no limitations. 13:12 pae7 port active enable for port 7. (gliu0 = not used; gliu1 = not used.) see bits [15:14] for decode. 11:10 pae6 port active enable for port 6. (gliu0 = not used; gliu1 = sb.) see bits [15:14] for decode. 9:8 pae5 port active enable for port 5. (gliu0 = gp; gliu1 = vip.) see bits [15:14] for decode. 7:6 pae4 port active enable for port 4. (gliu0 = dc; gliu1 = glpci.) see bits [15:14] for decode. 5:4 pae3 port active enable for port 3. (gliu0 = cpu core; gliu1 = glcp.) see bits [15:14] for decode. 3:2 pae2 port active enable for port 2. (gliu0 = interface to gliu1; gliu1 = vp.) see bits [15:14] for decode. 1:0 pae1 port active enable for port 1. (gliu0 = glmc; gliu1 = interface to gliu0.) see bits [15:14] for decode.
62 amd geode? lx processors data book gliu register descriptions 33234h 4.2.2.3 arbitration (arb) 4.2.2.4 asynchronous smi (asmi) asmi is a condensed version of the port asmi signals. the mask bits can be used to prevent a device from issuing an asmi. if the mask = 1, the device?s asmi is disabled. msr address gliu0: 10000082h gliu1: 40000082h ty p e r / w reset value 10000000_00000000h arb register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 quack_en pipe_dis rsvd dack_en rsvd 313029282726252423222120191817161514131211109876543210 rsvd arb bit descriptions bit name description 63 quack_en quadruple acknow ledge enabled. allow four acknowledgements in a row before advancing round-robin arbitration. only appl ies when arbitrating matching priorities. 0: disable. 1: enable. 62 pipe_dis pipelined arbitration disabled . 0: pipelined arbitration enabled and gliu is not limited to one outstanding transaction. 1: limit the entire gliu to one outstanding transaction. 61 rsvd reserved. 60 dack_en double acknowledge enabled. allow two acknowledgements in a row before advanc- ing round-robin arbitration. only applies when arbitrating matching priorities. 0: disable. 1: enable. 59:0 rsvd reserved. msr address gliu0: 10000083h gliu1: 40000083h ty p e r / w reset value 00000000_00000000h asmi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd asmi_mask7 asmi_mask6 asmi_mask5 asmi_mask4 asmi_mask3 asmi_mask2 asmi_mask1 asmi_mask0 asmi_flag7 asmi_flag6 asmi_flag5 asmi_flag4 asmi_flag3 asmi_flag2 asmi_flag1 asmi_flag0
amd geode? lx processors data book 63 gliu register descriptions 33234h 4.2.2.5 asynchron ous err (aerr) aerr is a condensed version of the port err signals. the mask bits can be used to prevent a device from issuing an aerr. if the mask = 1, the device?s aerr is disabled. asmi bit descriptions bit name description 63:16 rsvd reserved. 15 asmi_mask7 asynchronous smi mask for port 7. (gliu0 = not used; gliu1 = not used.) write 0 to allow port 7 to generate an asmi. asmi status is reported in bit 7. 14 asmi_mask6 asynchronous smi mask for port 6. (gliu0 = not used; gliu1 = sb.) write 0 to allow port 6 to generate an asmi. asmi status is reported in bit 6. 13 asmi_mask5 asynchronous smi mask for port 5. (gliu0 = gp; gliu1 = vip.) write 0 to allow port 5 to generate an asmi. asmi st atus is reported in bit 5. 12 asmi_mask4 asynchronous smi mask for port 4. (gliu0 = dc; gliu1 = glpci.) write 0 to allow port 4 to generate an asmi. asmi status is reported in bit 4. 11 asmi_mask3 asynchronous smi mask for port 3. (gliu0 = cpu core; gliu1 = glcp.) write 0 to allow port 3 to generate an asmi. asmi status is reported in bit 3. 10 asmi_mask2 asynchronous smi mask for port 2. (gliu0 = interface to gliu1; gliu1 = vp.) write 0 to allow port 2 to generate an asmi. asmi status is reported in bit 2. 9 asmi_mask1 asynchronous smi mask for port 1. (gliu0 = glmc; gliu1 = interface to gliu0.) write 0 to allow port 1 to generate an asmi. asmi status is reported in bit 1. 8 asmi_mask0 asynchronous smi mask for port 0. (gliu0 = gliu; gliu1 = gliu.) write 0 to allow port 0 to generate an asmi. asmi status is reported in bit 0. 7 asmi_flag7 (ro) asynchronous smi flag for port 7 (read only). (gliu0 = not us ed; gliu1 = not used.). if 1, this bit indicates that an asmi was generated by port 7. cleared by source. 6 asmi_flag6 (ro) asynchronous smi flag for port 6 (read only). (gliu0 = not used; gliu1 = sb.) if 1, this bit indicates that an asmi was generated by port 6. cleared by source. 5 asmi_flag5 (ro) asynchronous smi flag for port 5 (read only). (gliu0 = gp; gliu1 = vip.) if 1, this bit indicates that an asmi was generated by port 5. cleared by source. 4 asmi_flag4 (ro) asynchronous smi flag for port 4 (read only). (gliu0 = dc; gliu1 = glpci.) if 1, this bit indicates that an asmi was generated by port 4. cleared by source. 3 asmi_flag3 (ro) asynchronous smi flag for port 3 (read only). (gliu0 = cpu core; gliu1 = glcp.) if 1, this bit indicates that an asmi was generated by port37. cleared by source. 2 asmi_flag2 (ro) asynchronous smi flag for port 2 (read only). (gliu0 = interface to gliu1; gliu1 = vp.) if 1, this bit indicates that an asm i was generated by port 2. cleared by source. 1 asmi_flag1 (ro) asynchronous smi flag for port 1 (read only). (gliu0 = glmc; gliu1 = interface to gliu0.) if 1, this bit indicates that an asm i was generated by port 1. cleared by source. 0 asmi_flag0 (ro) asynchronous smi flag for port 0 (read only). (gliu0 = gliu; gliu1 = gliu.) if 1, this bit indicates that an asmi was generated by port 0. cleared by source. msr address gliu0: 10000084h gliu1: 40000084h ty p e r / w reset value 00000000_00000000h
64 amd geode? lx processors data book gliu register descriptions 33234h aerr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd aerr_mask7 aerr_mask6 aerr_mask5 aerr_mask4 aerr_mask3 aerr_mask2 aerr_mask1 aerr_mask0 aerr7 aerr6 aerr5 aerr4 aerr3 aerr2 aerr1 aerr0 aerr bit descriptions bit name description 63:16 rsvd reserved . 15 aerr_mask7 asynchronous error mask for port 7. (gliu0 = not used; gliu1 = not used.) write 0 to allow port 7 to generate an aerr. aerr status is reported in bit 7. 14 aerr_mask6 asynchronous error mask for port 6. (gliu0 = not used; gliu1 = sb.) write 0 to allow port 6 to generate an aerr. aerr status is reported in bit 6. 13 aerr_mask5 asynchronous error mask for port 5. (gliu0 = gp; gliu1 = vip.) write 0 to allow port 5 to generate an aerr. aerr status is reported in bit 5. 12 aerr_mask4 asynchronous error mask for port 4. (gliu0 = dc; gliu1 = glpci.) write 0 to allow port 4 to generate an aerr. aerr status is reported in bit 4. 11 aerr_mask3 asynchronous error mask for port 3. (gliu0 = cpu core; gliu1 = glcp.) write 0 to allow port 3 to generate an aerr. aerr status is reported in bit 3. 10 aerr_mask2 asynchronous error mask for port 2. (gliu0 = interface to gl iu1; gliu1 = vp.) write 0 to allow port 2 to generate an aerr. aerr status is reported in bit 2. 9 aerr_mask1 asynchronous error mask for port 1. (gliu0 = glmc; gliu1 = interface to gliu0.) write 0 to allow port 1 to generate an aerr. aerr status is reported in bit 1. 8 aerr_mask0 asynchronous error mask for port 0. (gliu0 = gliu; gliu1 = gliu.) write 0 to allow port 0 to generate an aerr. aerr status is reported in bit 0. 7 aerr_flag7 (ro) asynchronous error for port 7 (read only). (gliu0 = not used; gliu1 = not used.) if 1, indicates that an aerr was generat ed by port 7. cleared by source. 6 aerr_flag6 (ro) asynchronous error for port 6 (read only). (gliu0 = not used; gliu1 = sb.) if 1, indicates that an aerr was generated by port 6. cleared by source. 5 aerr_flag5 (ro) asynchronous error for port 5 (read only). (gliu0 = gp; gliu1 = vip.) if 1, indicates that an aerr was generated by port 5. cleared by source. 4 aerr_flag4 (ro) asynchronous error for port 4 (read only). (gliu0 = dc; gliu1 = glpci.) if 1, indi- cates that an aerr was generated by port 4. cleared by source. 3 aerr_flag3 (ro) asynchronous error for port 3 (read only). (gliu0 = cpu core; gliu1 = glcp.) if 1, indicates that an aerr was generated by port 3. cleared by source. 2 aerr_flag2 (ro) asynchronous error for port 2 (read only). (gliu0 = interface to gliu1; gliu1 = vp.) if 1, indicates that an aerr was g enerated by port 2. cleared by source. 1 aerr_flag1 (ro) asynchronous error for port 1 (read only). (gliu0 = glmc; gliu 1 = interface to gliu0.) if 1, indicates that an aerr was g enerated by port 1. cleared by source. 0 aerr_flag0 (ro) asynchronous error for port 0 (read only). (gliu0 = gliu; gliu1 = gliu.) if 1, indi- cates that an aerr was generated by port 0. cleared by source.
amd geode? lx processors data book 65 gliu register descriptions 33234h 4.2.2.6 gliu physical capabilities (phy_cap) msr address gliu0: 10000086h gliu1: 40000086h ty p e r / w reset value gliu0: 20291830_010c1086h gliu1: 20311030_0100400ah phy_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd nstat_cnt ndbg_da_cmp ndbg_rq_cmp nports ncoh niod_sc niod_bm np2d_bmk 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 np2d_bmk np2d_sc np2d_ro np2d_r np2d_bmo np2d_bm phy_cap bit descriptions bit name description 63 rsvd reserved. 62:60 nstat_cnt number of statistic counters. 59:57 ndbg_da_cmp number of data comparators. 56:54 ndbg_rq_cmp number of request comparators. 53:51 nports number of ports on the gliu. 50:48 ncoh number of coherent devices. 47:42 niod_sc number of iod_sc descriptors. 41:36 niod_bm number of iod_bm descriptors. 35:30 np2d_bmk number of p2d_bmk descriptors. 29:24 np2d_sc number of p2d_sc descriptors. 23:18 np2d_ro number of p2d_ro descriptors. 17:12 np2d_r number of p2d_r descriptors. 11:6 np2d_bmo number of p2d_bmo descriptors. 5:0 np2d_bm number of p2d_bm descriptors.
66 amd geode? lx processors data book gliu register descriptions 33234h 4.2.2.7 n outstanding response (nout_resp) msr address gliu0: 10000087h gliu1: 40000087h ty p e r o reset value 00000000_00000000h nout_resp register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 nout_resp7 nout_resp6 nout_resp5 nout_resp4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nout_resp3 nout_resp2 nout_resp1 nout_resp9 nout_resp bit descriptions bit name description 63:56 noout_resp7 number of outstanding responses on port 7. (gliu0 = not used; gliu1 = not used.) 55:48 noout_resp6 number of outstanding responses on port 6. (gliu0 = not used; gliu1 = sb.) 47:40 noout_resp5 number of outstanding responses on port 5. (gliu0 = gp; gliu1 = vip.) 39:32 noout_resp4 number of outstanding responses on port 4. (gliu0 = dc; gliu1 = glpci.) 31:24 noout_resp3 number of outstanding responses on port 3. (gliu0 = cpu core; gliu1 = glcp.) 23:16 noout_resp2 number of outstanding responses on port 2. (gliu0 = interface to gliu1; gliu1 = vp.) 15:8 noout_resp1 number of outstanding responses on port 1. (gliu0 = glmc; gliu1 = interface to gliu0.) 7:0 noout_resp0 number of outstanding responses on port 0. (gliu0 = gliu; gliu1 = gliu.)
amd geode? lx processors data book 67 gliu register descriptions 33234h 4.2.2.8 n outstanding write data (nout_wdata) 4.2.2.9 slave_only msr address gliu0: 10000088h gliu1: 40000088h ty p e r o reset value 00000000_00000000h nout_wdata register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 nout_wdata7 nout_wdata6 nout_wdata5 nout_wdata4 313029282726252423222120191817161514131211109876543210 nout_wdata3 nout_wdata2 nout_wdata1 nout_wdata0 nout_wdata bit descriptions bit name description 63:56 noout_wdata7 number of outstanding write data on port 7. (gliu0 = not used; gliu1 = not used.) 55:48 noout_wdata6 number of outstanding write data on port 6. (gliu0 = not used; gliu1 = sb.) 47:40 noout_wdata5 number of outstanding write data on port 5. (gliu0 = gp; gliu1 = vip.) 39:32 noout_wdata4 number of outstanding write data on port 4. (gliu0 = dc; gliu1 = glpci.) 31:24 noout_wdata3 number of outstanding write data on port 3. (gliu0 = cpu core; gliu1 = glcp.) 23:16 noout_wdata2 number of outstanding write data on port 2. (gliu0 = interface to gliu1; gliu1 = vp.) 15:8 noout_wdata1 number of outstanding write data on port 1. (gliu0 = glmc; gliu1 = interface to gliu0.) 7:0 noout_wdata0 number of outstanding write data on port 0. (gliu0 = gliu; gliu1 = gliu.) msr address gliu0: 10000089h gliu1: 40000089h ty p e r o reset value gliu0: 00000000_00000010h gliu1: 00000000_00000100h slave_only register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd slave_only slave_only bit descriptions bit name description 63:8 rsvd reserved. 7 p7_slave_only port 7 slave only. (gliu0 = not used; gliu1 = not used.) if high, indicates that port 7 is a slave port. if low, port 7 is a master/slave port.
68 amd geode? lx processors data book gliu register descriptions 33234h 4.2.2.10 who am i (whoami) 6 p6_slave_only port 6 slave only. (gliu0 = not used; gliu1 = sb.) if high, indicates that port 6 is a slave port. if low, port 6 is a master/slave port. 5 p5_slave_only port 5 slave only. (gliu0 = gp; gliu1 = vip.) if high, indicates that port 5 is a slave port. if low, port 5 is a master/slave port. 4 p4_slave_only port 4 slave only. (gliu0 = dc; gliu1 = glpci.) if hi gh, indicates that port 4 is a slave port. if low, port 4 is a master/slave port. 3 p3_slave_only port 3 slave only. (gliu0 = cpu core; gliu1 = glcp.) if high, indicates that port 3 is a slave port. if low, port 3 is a master/slave port. 2 p2_slave_only port 2 slave only. (gliu0 = interface to gliu1; gliu 1 = vp.) if high, indicates that port 2 is a slave port. if low, port 2 is a master/slave port. 1 p1_slave_only port 1 slave only. (gliu0 = glmc; gliu1 = interface to gliu0.) if high, indicates that port 1 is a slave port. if low, port 1 is a master/slave port. 0 p0_slave_only port 0 slave only. (gliu0 = gliu; gliu1 = gliu.) if high, indicates that port 0 is a slave port. if low, port 0 is a master/slave port. msr address gliu0: 1000008bh gliu1: 4000008bh ty p e r o reset value configuration dependent slave_only bit descriptions (continued) bit name description who am i register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd dsid who am i bit descriptions bit name description 63:3 rsvd reserved. 2:0 dsid source id of the initiating device. used to prevent self referencing transactions. 000: port 0 (gliu0 = gliu; gliu1 = gliu.) 001: port 1 (gliu0 = glmc; gliu1 = interface to gliu0.) 010: port 2 (gliu0 = interface to gliu1; gliu1 = vp.) 011: port 3 (gliu0 = cpu core; gliu1 = glcp.) 100: port 4 (gliu0 = dc; gliu1 = glpci.) 101: port 5 (gliu0 = gp; gliu1 = vip.) 110: port 6 (gliu0 = not used; gliu1 = sb.) 111: port 7 (gliu0 = not used; gliu1 = not used.)
amd geode? lx processors data book 69 gliu register descriptions 33234h 4.2.2.11 gliu slave disable (gliu_slv) the slave disable registers are available for the number of ports on the gliu. the unused ports return 0. msr address gliu0: 1000008ch gliu1: 4000008ch ty p e r / w reset value 00000000_00000000h gliu_slv register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd slave_dis7 slave_dis6 slave_dis5 slave_dis4 slave_dis3 slave_dis2 slave_dis1 slave_dis0 gliu_slv bit descriptions bit name description 63:8 rsvd reserved. 7 slave_dis7 slave transactions disable for port 7. (gliu0 = not used; gliu1 = not used.) write 1 to disable slave transactions to port 7. 6 slave_dis6 slave transactions disable for port 6. (gliu0 = not used; gliu1 = sb.) write 1 to disable slave transactions to port 6. 5 slave_dis5 slave transactions disable for port 5. (gliu0 = gp; gliu1 = vip.) write 1 to disable slave transactions to port 5. 4 slave_dis4 slave transactions disable for port 4. (gliu0 = dc; gliu1 = glpci.) write 1 to dis- able slave transactions to port 4. 3 slave_dis3 slave transactions disable for port 3. (gliu0 = cpu core; gliu1 = glcp.) write 1 to disable slave transactions to port 3. 2 slave_dis2 slave transactions disable for port 2. (gliu0 = interface to gliu1; gliu1 = vp.) write 1 to disable slave transactions to port 2. 1 slave_dis1 slave transactions disable for port 1. (gliu0 = glmc; gliu1 = interface to gliu0.) write 1 to disable slave transactions to port 1. 0 slave_dis0 slave transactions disable for port 0. (gliu0 = gliu; gliu1 = gliu.) write 1 to dis- able slave transactions to port 0.
70 amd geode? lx processors data book gliu register descriptions 33234h 4.2.2.12 arbitration2 (arb2) msr address gliu0: 1000008dh gliu1: 4000008dh ty p e r / w reset value 00000000_00000000h arb2 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd throt_en thresh arb2 bit descriptions bit name description 63:4 rsvd reserved. 3throt_en arbitration throttling enable. when set, arbitration is prevented in this gliu if the other gliu is retreating a priority above the thresh priority. 2:0 thresh priority threshold. see throt_en description. priority threshold value must be 4 or less. 0: disable. 1: enable.
amd geode? lx processors data book 71 gliu register descriptions 33234h 4.2.3 gliu statistic and comparator msrs 4.2.3.1 descriptor statistic counter (statistic_cnt[0:3]) descriptor statistic co unter (statistic_cnt[0]) descriptor statistic co unter (statistic_cnt[1]) descriptor statistic co unter (statistic_cnt[2]) descriptor statistic co unter (statistic_cnt[3]) msr address gliu0: 100000a0h gliu1: 400000a0h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000a4h gliu1: 400000a4h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000a8h gliu1: 400000a8h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000ach gliu1: 400000ach ty p e r / w reset value 00000000_00000000h statistic_cnt[0:3] registers map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 load_val 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cnt statistic_cnt[0:3 ] bit descriptions bit name description 63:32 load_val counter load value. the value loaded here is used as the initial statistics counter value when a load action occurs or is commanded. 31:0 cnt counter value. these bits provide the current counter value when read.
72 amd geode? lx processors data book gliu register descriptions 33234h 4.2.3.2 statistic mask (statistic_mask[0:3] descriptor statistic m ask (statistic_mask[0]) descriptor statistic mask (statistic_mask[1]) descriptor statistic mask (statistic_mask[2]) descriptor statistic mask (statistic_mask[3]) msr address gliu0: 100000a1h gliu1: 400000a1h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000a5h gliu1: 400000a5h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000a9h gliu1: 400000a9h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000adh gliu1: 400000adh ty p e r / w reset value 00000000_00000000h statistic_mask[0:3] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 iod_mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p2d mask statistic_mask[0:3] bit descriptions bit name description 63:32 iod_mask mask for hits to each iod. hits are determined after the re quest is arbitrated. a hit is determined by the following logical eq uation: hit = |(iod_mask[n-1:0] & rq_desc_hit[n-1:0] && is_io) | |(p2 d_mask[n-1:0] & rq _desc_hit[n-1:0] && is_mem). 31:0 p2d_mask mask for hits to each p2d. a hit is determined by the foll owing logical equation: hit = |(iod_mask[n-1:0] & rq_desc_hit[n-1:0] && is_io) | |( p2d_mask[n-1:0] & rq_desc_hit[n-1:0] && is_mem).
amd geode? lx processors data book 73 gliu register descriptions 33234h 4.2.3.3 statistic action (statistic_action[0:3] descriptor statistic acti on (statistic_action[0]) descriptor statistic acti on (statistic_action[1]) descriptor statistic acti on (statistic_action[2]) descriptor statistic acti on (statistic_action[3]) msr address gliu0: 100000a2h gliu1: 400000a2h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000a6h gliu1: 400000a6h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000aah gliu1: 400000aah ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000aeh gliu1: 400000aeh ty p e r / w reset value 00000000_00000000h statistic_action[0:3] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd prediv wrap zero_aerr zxero_asmi always_dec hit_aerr hit_asmi hit_dec hit_lden statistic_action[0:3 ] bit descriptions bit name description 63:24 rsvd reserved. 23:8 prediv pre divider. used if always_dec (bit 4) is set. the predivider is free running and extends the depth of the counter. 7wrap decrement counter beyond zero and wrap. 0: disable wrap; counter stops when it reaches zero. 1: enable wrap; counter decrements through 0 to all ones. 6 zero_aerr assert aerr on cnt = 0. assert aerr when statistic_cnt[x] reaches 0. 0: disable. 1: enable. 5 zero_asmi assert asmi on cnt = 0 . assert asmi when statistic_cnt[x] reaches 0. 0: disable. 1: enable. 4 always_dec always decrement counter . if enabled, the counter decrements on every memory clock subject to the prescaler value prediv (bits [23:8]). decrementing continues unless loading is occurring due to another action, or if the counter reaches zero and wrap is disabled (bit 7). 0: disable. 1: enable 3 hit_aerr assert aerr on descirptor hit. the descriptor hits are anded with the masks and then all ored together. 0: disable. 1: enable
74 amd geode? lx processors data book gliu register descriptions 33234h 4.2.3.4 request compare va lue (rq_compare_val[0:3] the rq compare value and the rq compare mask enable traps on specific transactions. a hit to the rq compare is determined by hit = (rq_in & rq_com pare_mask) == rq_compare_val). a hit can trigger the rq_cmp error sources when they are enabled. the value is compared only after the packet is arbitrated. request compare valu e (rq_compare_val[0]) request compare valu e (rq_compare_val[1]) request compare valu e (rq_compare_val[2]) request compare valu e (rq_compare_val[3]) 2 hit_asmi assert asmi on descriptor hit. the descriptor hits are anded with the masks and then all ored together. 0: disable. 1: enable. 1hit_dec decrement counter on descriptor hit. the descriptor hi ts are anded with the masks and then all ored together. 0: disable. 1: enable. 0hit_lden load counter on descriptor hit. the descriptor hits are anded with the masks and then all ored together. 0: disable. 1: enable. statistic_action[0:3 ] bit descriptions bit name description msr address gliu0: 100000c0h gliu1: 400000c0h ty p e r / w reset value 001fffff_ffffffffh msr address gliu0: 100000c2h gliu1: 400000c2h ty p e r / w reset value 001fffff_ffffffffh msr address gliu0: 100000c4h gliu1: 400000c4h ty p e r / w reset value 001fffff_ffffffffh msr address gliu0: 100000c6h gliu1: 400000c6h ty p e r / w reset value 001fffff_ffffffffh rq_compare_val[0:3] register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd rq_val 313029282726252423222120191817161514131211109876543210 rq_val rq_compare_val[0:3] bit descriptions bit name description 63:53 rsvd reserved. 52:0 rq_val request packet value. this is the value compared agai nst the logical bit-wise and of the incoming request packet and the rq_c ompmask in order to determine a ?hit?.
amd geode? lx processors data book 75 gliu register descriptions 33234h 4.2.3.5 request compare ma sk (rq_compare_mask[0:3] the rq compare value and the rq compare mask enable traps on specific transactions. a hit to the rq compare is determined by hit = (rq_in & rq_com pare_mask) == rq_compare_val). a hit can trigger the rq_cmp error sources when they are enabled. the value is compared only after the packet is arbitrated. request compare mask (rq_compare_mask[0]) request compare mask (rq_compare_mask[1]) request compare mask (rq_compare_mask[2]) request compare mask (rq_compare_mask[3]) msr address gliu0: 100000c1h gliu1: 400000c1h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000c3h gliu1: 400000c3h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000c5h gliu1: 400000c5h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000c7h gliu1: 400000c7h ty p e r / w reset value 00000000_00000000h rq_compare_mask[0:3] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd rq_mask 313029282726252423222120191817161514131211109876543210 rq_mask rq_compare_mask[0:3] bit descriptions bit name description 63:53 rsvd reserved. 52:0 rq_mask request packet mask. this field is bit-wise logically anded with the incoming request packet before it is compared to the rq_compval.
76 amd geode? lx processors data book gliu register descriptions 33234h 4.2.3.6 da compare value lo w (da_compare_val_lo[0:3] the da compare value and the da compare mask enable traps on sp ecific transactions. a hit to the da compare is deter- mined by hit = (da_in & da_compare_mask) == da_compa re_val). a hit can trigger the da_cmp error sources when they are enabled. the value is compared only after the packet is arbitrated. data compare value low (da_compare_val_lo[0]) data compare value low (da_compare_val_lo[1]) data compare value low (da_compare_val_lo[2]) data compare value low (da_compare_val_lo[3]) msr address gliu0: 100000d0h gliu1: 400000d0h ty p e r / w reset value 00001fff_ffffffffh msr address gliu0: 100000d4h gliu1: 400000d4h ty p e r / w reset value 00001fff_ffffffffh msr address gliu0: 100000d8h gliu1: 400000d8h ty p e r / w reset value 00001fff_ffffffffh msr address gliu0: 100000dch gliu1: 400000dch ty p e r / w reset value 00001fff_ffffffffh da_compare_val_lo[0:3] register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd dalo_val 313029282726252423222120191817161514131211109876543210 dalo_val da_compare_val_lo[0:3] bit descriptions bit name description 63:45 rsvd reserved. 44:0 dalo_val da packet compare value [44:0]. this field forms the lower portion of the data value, which is compared to the logical bit-wise and of the incoming data value and the data value compare mask in order to determine a ?h it?. the ?hi? and ?lo? portions of the incoming data, the compare value, and the co mpare mask, are assembled into complete bit patterns before these operations occur.
amd geode? lx processors data book 77 gliu register descriptions 33234h 4.2.3.7 da compare value high (da_compare_val_hi[0:3] the da compare value and the da compare mask enable traps on sp ecific transactions. a hit to the da compare is deter- mined by hit = (da_in & da_compare_mask) == da_compa re_val). a hit can trigger the da_cmp error sources when they are enabled. the value is compared only after the packet is arbitrated. data compare value high (da_compare_val_hi[0]) data compare value high (da_compare_val_hi[1]) data compare value high (da_compare_val_hi[2]) data compare value high (da_compare_val_hi[3]) msr address gliu0: 100000d1h gliu1: 400000d1h ty p e r / w reset value 0000000f_ffffffffh msr address gliu0: 100000d5h gliu1: 400000d5h ty p e r / w reset value 0000000f_ffffffffh msr address gliu0: 100000d9h gliu1: 400000d9h ty p e r / w reset value 0000000f_ffffffffh msr address gliu0: 100000ddh gliu1: 400000ddh ty p e r / w reset value 0000000f_ffffffffh da_compare_val_hi[0:3] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd dahi_val 313029282726252423222120191817161514131211109876543210 dahi_val da_compare_val_hi[0:3] bit descriptions bit name description 63:36 rsvd reserved. 35:0 dahi_val da packet compare value [80:45]. this field forms the upper portion of the data value which is compared to the logical bit-wise a nd of the incoming data value and the data value compare mask in order to determine a ?h it?. the ?hi? and ?lo? portions of the incoming data, the compare value, and the co mpare mask, are assembled into complete bit patterns before these operations occur.
78 amd geode? lx processors data book gliu register descriptions 33234h 4.2.3.8 da compare mask low (da_compare_mask_lo[0:3]) data compare mask low (da_compare_mask_lo[0]) data compare mask low (da_compare_mask_lo[1]) data compare mask low (da_compare_mask_lo[2]) data compare mask low (da_compare_mask_lo[3]) the da compare value and the da compare mask enable traps on sp ecific transactions. a hit to the da compare is deter- mined by hit = (da_in & da_compare_mask) == da_compa re_val). a hit can trigger the da_cmp error sources when they are enabled. the value is compared only after the packet is arbitrated. msr address gliu0: 100000d2h gliu1: 400000d2h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000d6h gliu1: 400000d6h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000dah gliu1: 400000dah ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000deh gliu1: 400000deh ty p e r / w reset value 00000000_00000000h da_compare_val_hi[0:3] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd dalo_mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dalo_mask da_compare_mask_lo[0:3] bit descriptions bit name description 63:45 rsvd reserved. 44:0 dalo_mask da packet compare value [44:0]. this field forms the lower portion of the data comp- mask value, which is then bit-wise logicall y anded with the incoming data value before it is compared to the da_compval. the ?hi? and ?lo? portions of the incoming data, the compare value, and the compare mask, are assembled into complete bit patterns before these operations occur.
amd geode? lx processors data book 79 gliu register descriptions 33234h 4.2.3.9 da compar e mask high ( da_compare_mask_hi[0:3]) data compare mask high (da_compare_mask_hi[0]) data compare mask high (da_compare_mask_hi[1]) data compare mask high (da_compare_mask_hi[2]) data compare mask high (da_compare_mask_hi[3]) msr address gliu0: 100000d3h gliu1: 400000d3h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000d7h gliu1: 400000d7h ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000dbh gliu1: 400000dbh ty p e r / w reset value 00000000_00000000h msr address gliu0: 100000dfh gliu1: 400000dfh ty p e r / w reset value 00000000_00000000h da_compare_mask_hi[0:3] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd dahi_mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dahi_mask da_compare_mask_hi[0:3] bit descriptions bit name description 63:36 rsvd reserved. 35:0 dahi_mask da packet compare mask [80:45]. this field forms the upper portion of the data compmask value, which is then bit-wise l ogically anded with t he incoming data value before it is compared to the da_compval.the ?hi? and ?lo? portions of the incoming data. the compare value, and the compare mask, are assembled into complete bit pat- terns before these operations occur.
80 amd geode? lx processors data book gliu register descriptions 33234h 4.2.4 p2d descriptor registers p2d descriptors are ordered p2d_bm, p2d_bmo, p2d_r, p2d_ro, p2d_sc, p2 d_bmk. for example if np2d_bm=3 and np2d_bm0=2, imsr eo = p2d_bm[0], msr e3 = p2d_sc[0]. 4.2.4.1 p2d base mask descriptor (p2d_bm) see table 4.1.3.1 "memory routing and translatio n" on page 47 for details on the descriptor usage. gliu0 p2d_bm[5:0] msr address 10000020h-10000025h ty p e r / w reset value 000000ff_fff00000h gliu1 p2d_bm[9:0] msr address 40000020h-40000029h ty p e r / w reset value 000000ff_fff00000h p2d_bm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 pdid1 pcmp_biz rsvd pbase 313029282726252423222120191817161514131211109876543210 pbase pmask p2d_bm bit descriptions bit name description 63:61 pdid1 descriptor destination id. these bits define which port to route the request to, if it is a ?hit? based on the other settings in this register. 000: port 0 (gliu0 = gliu; gliu1 = gliu.) 001: port 1 (gliu0 = glmc; gliu1 = interface to gliu0.) 010: port 2 (gliu0 = interface to gliu1; gliu1 = vp.) 011: port 3 (gliu0 = cpu core; gliu1 = glcp.) 100: port 4 (gliu0 = dc; gliu1 = glpci.) 101: port 5 (gliu0 = gp; gliu1 = vip.) 110: port 6 (gliu0 = not used; gliu1 = sb.) 111: port 7 (gliu0 = not used; gliu1 = not used.) 60 pcmp_biz compare bizzaro flag. 0: consider only transactions whose bizzaro flag is low as a potentially valid address hit. a low bizzaro flag indicates a normal trans action cycle such as a memory or i/o. 1: consider only transactions whose bizzaro flag is high as a potentially valid address hit. a high bizzaro flag indicates a ?special? transaction, such as a pci shutdown or halt cycle. 59:40 rsvd reserved. 39:20 pbase physical memory address base. these bits form the matching value against which the masked value of the physical address, bits [31:12] are directly compared. if a match is found, then a ?hit? is declared, depending on the setting of the bizzaro flag comparator. 19:0 pmask physical memory address mask. these bits are used to mask address bits [31:12] for the purposes of this ?hit? detection.
amd geode? lx processors data book 81 gliu register descriptions 33234h 4.2.4.2 p2d base mask offset descriptor (p2d_bmo) see table 4.1.3.1 "memory routing and translatio n" on page 47 for details on the descriptor usage. gliu0 p2d_bmo[1:0] msr address 10000026h-10000027h ty p e r / w reset value 00000ff0_fff00000h p2d_bmo register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 pdid1 pcmp_biz poffset pbase 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pbase pmask p2d_bmo bit descriptions bit name description 63:61 pdid1 descriptor destination id. these bits define which port to route the request to, if it is a ?hit? based on the other settings in this register. 000: port 0 (gliu0 = gliu; gliu1 = gliu.) 001: port 1 (gliu0 = glmc; gliu1 = interface to gliu0.) 010: port 2 (gliu0 = interface to gliu1; gliu1 = vp.) 011: port 3 (gliu0 = cpu core; gliu1 = glcp.) 100: port 4 (gliu0 = dc; gliu1 = glpci.) 101: port 5 (gliu0 = gp; gliu1 = vip.) 110: port 6 (gliu0 = not used; gliu1 = sb.) 111: port 7 (gliu0 = not used; gliu1 = not used.) 60 pcmp_biz compare bizzaro flag. 0: consider only transactions whose bizzaro flag is low as a potentially valid address hit. a low bizzaro flag indicates a normal transaction cycle such as a memory or i/o. 1: consider only transactions whose bizzaro flag is high as a potentially valid address hit. a high bizzaro flag indicates a ?special? transaction, such as a pci shutdown or halt cycle. 59:40 poffset physical memory address 2s comp offset. 2s complement offset that is added to physical address on a hit. 39:20 pbase physical memory address base. these bits form the matching value against which the masked value of the physical address, bits [3 1:12] are directly compared. if a match is found, then a ?hit? is declared, depending on t he setting of the bizzaro flag comparator. 19:0 pmask physical memory address mask. these bits are used to mask address bits [31:12] for the purposes of this ?hit? detection.
82 amd geode? lx processors data book gliu register descriptions 33234h 4.2.4.3 p2d range descriptor (p2d_r) see table 4.1.3.1 "memory routing and translatio n" on page 47 for details on the descriptor usage. gliu0 p2d_r[0] msr address 10000028h ty p e r / w reset value 00000000_000fffffh gliu1 p2d_r[3:0] msr address 4000002ah-4000002dh ty p e r / w reset value 00000000_000fffffh p2d_r register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 pdid1 pcmp_biz rsvd pmax 313029282726252423222120191817161514131211109876543210 pmax pmin p2d_r bit descriptions bit name description 63:61 pdid1 descriptor destination id. these bits define which port to route the request to, if it is a ?hit? based on the other settings in this register. 000: port 0 (gliu0 = gliu; gliu1 = gliu.) 001: port 1 (gliu0 = glmc; gliu1 = interface to gliu0.) 010: port 2 (gliu0 = interface to gliu1; gliu1 = vp.) 011: port 3 (gliu0 = cpu core; gliu1 = glcp.) 100: port 4 (gliu0 = dc; gliu1 = glpci.) 101: port 5 (gliu0 = gp; gliu1 = vip.) 110: port 6 (gliu0 = not used; gliu1 = sb.) 111: port 7 (gliu0 = not used; gliu1 = not used.) 60 pcmp_biz compare bizzaro flag. 0: consider only transactions whose bizzaro flag is low as a potentially valid address hit. a low bizzaro flag indicates a normal trans action cycle such as a memory or i/o. 1: consider only transactions whose bizzaro flag is high as a potentially valid address hit. a high bizzaro flag indicates a ?special? transaction, such as a pci shutdown or halt cycle. 59:40 rsvd reserved. 39:20 pmax physical memory address max. these bits form the value denoting the upper (ending) address of the physical memory, which is compared to determine a hit. 19:0 pmin physical memory address min. these bits form the value den oting the lower (starting) address of the physical memory, which is compared to determine a hit. hence, a hit occurs if the physical address [31:12] >= pmin and <= pmax.
amd geode? lx processors data book 83 gliu register descriptions 33234h 4.2.4.4 p2d range offset descriptor (p2d_ro) see table 4.1.3.1 "memory routing and translatio n" on page 47 for details on the descriptor usage. gliu0 p2d_ro[2:0] msr address 10000029h-1000002bh ty p e r / w reset value 00000000_000fffffh p2d_ro register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 pdid1 pcmp_biz offset pmax 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pmax pmin p2d_ro bit descriptions bit name description 63:61 pdid1 descriptor destination id. these bits define which port to route the request to, if it is a ?hit? based on the other settings in this register. 000: port 0 (gliu0 = gliu; gliu1 = gliu.) 001: port 1 (gliu0 = glmc; gliu1 = interface to gliu0.) 010: port 2 (gliu0 = interface to gliu1; gliu1 = vp.) 011: port 3 (gliu0 = cpu core; gliu1 = glcp.) 100: port 4 (gliu0 = dc; gliu1 = glpci.) 101: port 5 (gliu0 = gp; gliu1 = vip.) 110: port 6 (gliu0 = not used; gliu1 = sb.) 111: port 7 (gliu0 = not used; gliu1 = not used.) 60 pcmp_biz compare bizzaro flag. 0: consider only transactions whose bizzaro flag is low as a potentially valid address hit. a low bizzaro flag indicates a normal trans action cycle such as a memory or i/o. 1: consider only transactions whose bizzaro flag is high as a potentially valid address hit. a high bizzaro flag indicates a ?special? transaction, such as a pci shutdown or halt cycle. 59:40 poffset physical memory address 2?s comp offset. 2s complement offset that is added to physical address on a hit. 39:20 pmax physical memory address max. these bits form the value denoting the upper (ending) address of the physical memory, which is compared to determine a hit. 19:0 pmin physical memory address min. these bits form the value den oting the lower (starting) address of the physical memory, which is compared to determine a hit. hence, a hit occurs if the physical address [31:12] >= pmin and <= pmax.
84 amd geode? lx processors data book gliu register descriptions 33234h 4.2.4.5 p2d swiss chees e descriptor (p2d_sc) see table 4.1.3.1 "memory routing and translatio n" on page 47 for details on the descriptor usage. gliu0 p2d_sc[0] msr address 1000002ch ty p e r / w reset value 00000000_00000000h gliu1 p2d_sc[0] msr address 4000002eh ty p e r / w reset value 00000000_00000000h p2d_sc register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 pdid1 pcmp_biz rsvd wen 313029282726252423222120191817161514131211109876543210 ren rsvd pscbase p2d_sc bit descriptions bit name description 63:61 pdid1 descriptor destination id 1. these bits define which port to route the request to, if it is a ?hit? based on the other settings in this register. 000: port 0 (gliu0 = gliu; gliu1 = gliu.) 001: port 1 (gliu0 = glmc; gliu1 = interface to gliu0.) 010: port 2 (gliu0 = interface to gliu1; gliu1 = vp.) 011: port 3 (gliu0 = cpu core; gliu1 = glcp.) 100: port 4 (gliu0 = dc; gliu1 = glpci.) 101: port 5 (gliu0 = gp; gliu1 = vip.) 110: port 6 (gliu0 = not used; gliu1 = sb.) 111: port 7 (gliu0 = not used; gliu1 = not used.) 60 pcmp_biz compare bizzaro flag. 0: consider only transactions whose bizzaro flag is low as a potentially valid address hit. a low bizzaro flag indicates a normal trans action cycle such as a memory or i/o. 1: consider only transactions whose bizzaro flag is high as a potentially valid address hit. a high bizzaro flag indicates a ?special? transaction, such as a pci shutdown or halt cycle. 59:48 rsvd reserved. 47:32 wen enable hits to the base for the ith 16k page for writes. when set to 1, causes the incoming request to be routed to the port spec ified in pdid1 if the incoming request is a write type. 31:16 ren enable hits to the base for the ith 16k page for reads. when set to 1, causes the incoming request to be routed to the port spec ified in pdid1 if the incoming request is a read type. 15:14 rsvd reserved. 13:0 pbase physical memory address base for hit. these bits form the basis of comparison with incoming checks that the physical address s upplied by the device?s request on address bits [31:18] are equal to pbase. bits [17: 14] of the physical addre ss are used to choose the ith 16k region of wen/ren for a hit.
amd geode? lx processors data book 85 gliu register descriptions 33234h 4.2.5 spare msrs (spare_msr[0:9], a:f) msr address gliu0: 10000040h-1000004fh gliu1: 40000040h-4000004fh ty p e r / w reset value 00000000_00000000h spare_msr[x] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 spare_msr 313029282726252423222120191817161514131211109876543210 spare_msr spare_msr[x] bit descriptions bit name description 63:0 spare_msr spare msr.
86 amd geode? lx processors data book gliu register descriptions 33234h 4.2.6 i/o descriptors i/o descriptors are ordered iod_bm, iod_sc. for exampl e if niod_bm = 3 and niod_sc = 2, msr 100000eoh = iod_bm[0] and msr 100000e3h = iod_sc[0]. 4.2.6.1 iod base mask descriptors (iod_bm) see table 4.1.3.1 "memory routing and translatio n" on page 47 for details on the descriptor usage. gliu0 iod_bm[0:3] msr address 100000e0h-100000e2h ty p e r / w reset value 000000ff_fff00000h gliu1 iod_bm[0:3] msr address 400000e0h-400000e2h ty p e r / w reset value 000000ff_fff00000h iod_bm[x] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 idid icmp_biz rsvd ibase 313029282726252423222120191817161514131211109876543210 ibase imask iod_bm[x] bit descriptions bit name description 63:61 idid i/o descriptor destination id. these bits define which port to route the request to, if it is a ?hit? based on the other settings in this register. 000: port 0 (gliu0 = gliu; gliu1 = gliu.) 001: port 1 (gliu0 = glmc; gliu1 = interface to gliu0.) 010: port 2 (gliu0 = interface to gliu1; gliu1 = vp.) 011: port 3 (gliu0 = cpu core; gliu1 = glcp.) 100: port 4 (gliu0 = dc; gliu1 = glpci.) 101: port 5 (gliu0 = gp; gliu1 = vip.) 110: port 6 (gliu0 = not used; gliu1 = sb.) 111: port 7 (gliu0 = not used; gliu1 = not used.) 60 icmp_biz compare bizzaro flag. 0: consider only transactions whose bizzaro flag is low as a potentially valid address hit. a low bizzaro flag indicates a normal trans action cycle such as a memory or i/o. 1: consider only transactions whose bizzaro flag is high as a potentially valid address hit. a high bizzaro flag indicates a ?special? transaction, such as a pci shutdown or halt cycle. 59:40 rsvd reserved. 39:20 ibase physical i/o address base. these bits form the matching value against which the masked value of the physical address, bits [19: 0] are directly compared. if a match is found, then a ?hit? is declared, depending on the setting of the bizzaro flag comparator. 19:0 imask physical i/o address mask. these bits are used to mask address bits [31:12] for the purposes of this ?hit? detection.
amd geode? lx processors data book 87 gliu register descriptions 33234h 4.2.6.2 iod swiss chees e descriptors (iod_sc) see table 4.1.3.1 "memory routing and translatio n" on page 47 for details on the descriptor usage. gliu0 iod_sc[0:5] msr address 100000e3h-100000e8h ty p e r / w reset value 00000000_00000000h gliu1 iod_sc[0:3] msr address 400000e3h-400000e6h ty p e r / w reset value 00000000_00000000h iod_sc[x] register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 idid1 icmp_biz rsvd 313029282726252423222120191817161514131211109876543210 en rsvd wen ren ibase rsvd iod_sc[x] bit descriptions bit name description 63:61 idid1 descriptor destination id 1. encoded port number of the destination of addresses which produce a ?hit? based on the other fields in this descriptor. 60 icmp_biz compare bizzaro flag. used to check that the bizzaro flag of the request is equal to the picmp_biz_sc bit (this bit). if a matc h does not occur, then the incoming request cannot generate a hit. the bizzaro flag, if set in the incoming request, signifies a ?spe- cial? cycle such as a pc i shutdown or halt. 59:32 rsvd reserved. write as read. 31:24 en enable for hits to idid1 or else subp. setting these bits enables hits to idid1. if not enabled, subtractive port is selected per gld_msr_config, bits [2:0] (msr gliu0: 10002001h; gliu1: 40002001h). (see section 4.2.1.2 "gld master configuration msr (gld_msr_config)" on page 55 for bit descriptions). 23:22 rsvd reserved. 21 wen descriptor hits idid1 on write request types else subp. if set, causes the incom- ing request to be routed to the port specified in idid1 if the incoming request is a write type. if not set, subtractive port is sele cted per gld_msr_config, bits [2:0] (msr gliu0: 10002001h; gliu1: 40002001h). (see se ction 4.2.1.2 "gld master configura- tion msr (gld_msr_config)" on page 55 for bit descriptions). 20 ren descriptors hit idid1 on read request types else subp. if set, causes the incom- ing request to be routed to the port specified in idid1 if the incoming request is a read type. if not set, subtractive port is sele cted per gld_msr_config, bits [2:0] (msr gliu0: 10002001h; gliu1: 40002001h). (see se ction 4.2.1.2 "gld master configura- tion msr (gld_msr_config)" on page 55 for bit descriptions). 19:3 ibase i/o memory base. this field forms the basis of comparison with the incoming checks that the physical address supplied by the de vice?s request on address bits [31:18] are equal to the pbase field of descriptor register bits [13:0]. 2:0 rsvd reserved. write as read.
88 amd geode? lx processors data book gliu register descriptions 33234h
amd geode? lx processors data book 89 5 cpu core 33234h 5.0 cpu core this section describes the internal operations of the amd geode? lx processor?s cpu core from a program- mer?s point of view. it includes a description of the tradi- tional ?core? processing and fpu operations. the integrated function registers are described in the next chapter. the primary register sets within the processor core include: ? application register set ? system register set 5.1 core processor initialization the cpu core is initialized when the reset# (reset) sig- nal is asserted. the cpu core is placed in real mode and the registers listed in table 5-1 are set to their initialized values. reset# invalidates a nd disables the cpu cache, and turns off paging. when reset# is asserted, the cpu terminates all local bus activity and all internal execution. while reset# is asserted, the internal pipeline is flushed and no instruction execution or bus activity occurs. approximately 150 to 250 external clock cycles after reset# is de-asserted, the processor begins executing instructions at the top of ph ysical memory (address location fffffff0h). the actual number of clock cycles depends on the clock scaling in use. also, before execution begins, an additional 2 20 clock cycles are needed when self-test is requested. typically, an intersegment jump is placed at fffffff0h. this instruction forces the processor to begin execution in the lowest 1 mb of address space. table 5-1 lists the cpu core registers and illustrates how they are initialized. table 5-1. initialized core register controls register register name initialized contents (note 1) comments eax accumulator xxxxxxxxh 00000000h i ndicates self-test passed. ebx base xxxxxxxxh ecx count xxxxxxxxh edx data xxxx 04 [dir0]h dir0 = device id ebp base pointer xxxxxxxxh esi source index xxxxxxxxh edi destination index xxxxxxxxh esp stack pointer xxxxxxxxh eflags extended flags 00000002h see table 5-4 on page 93 for bit definitions. eip instruction pointer 0000fff0h es extra segment 0000h base address set to 00000000h. limit set to ffffh. cs code segment f000h base address set to ffff0000h. limit set to ffffh. ss stack segment 0000h base address set to 00000000h. limit set to ffffh. ds data segment 0000h base address set to 00000000h. limit set to ffffh. fs extra segment 0000h base address set to 00000000h. limit set to ffffh. gs extra segment 0000h base address set to 00000000h. limit set to ffffh. idtr interrupt descriptor table register base = 0, limit = 3ffh gdtr global descriptor table register xxxxxxxxh ldtr local descriptor table register xxxxh tr task register xxxxh cr0 control register 0 60000010h see table 5-10 on page 96 for bit descriptions. cr2 control register 2 xxxxxxxxh see table 5-9 on page 96 for bit descriptions. cr3 control register 3 xxxxxxxxh see table 5-8 on page 96 for bit descriptions. cr4 control register 4 00000000h see table 5-7 on page 96 for bit descriptions. note 1. x = undefined value.
90 amd geode? lx processors data book cpu core 33234h 5.2 instruction set overview the cpu core instruction set can be divided into nine types of operations: ? arithmetic ? bit manipulation ? shift/rotate ? string manipulation ? control transfer ? data transfer ? floating point ? high-level language support ? operating system support the instructions operate on as few as zero operands and as many as three operands. a nop (no operation) instruc- tion is an example of a zero-operand instruction. two-oper- and instructions allow the specification of an explicit source and destination pair as part of the instruction. these two- operand instructions can be divided into ten groups accord- ing to operand types: ? register to register ? register to memory ? memory to register ? memory to memory ? register to i/o ? i/o to register ? memory to i/o ? i/o to memory ? immediate data to register ? immediate data to memory an operand can be held in the instruction itself (as in the case of an immediate operand), in one of the processor?s registers or i/o ports, or in memory. an immediate operand is fetched as part of the opcode for the instruction. operand lengths of 8, 16, 32 or 48 bits are supported as well as 64 or 80 bits associated with floating-point instruc- tions. operand lengths of 8 or 32 bits are generally used when executing code written for 386- or 486-class (32-bit code) processors. operand lengths of 8 or 16 bits are gen- erally used when executing existing 8086 or 80286 code (16-bit code). the default length of an operand can be overridden by placing one or more instruction prefixes in front of the opcode. for example, the use of prefixes allows a 32-bit operand to be used with 16-bit code or a 16-bit operand to be used with 32-bit code. the processor core instruction set (see table 8-26 on page 634) contains the clock count table that lists each instruction in the cpu instruction set. included in the table are the associated opcodes, execution clock counts, and effects on the eflags register. 5.2.1 lock prefix the lock prefix may be placed before certain instructions that read, modify, then write back to memory. the pci will not be granted access in the middle of locked instructions. the lock prefix can be used with the following instructions only when the result is a write operation to memory. ? bit test instructions (bts, btr, btc) ? exchange instructions (xadd, xchg, cmpxchg) ? one-operand arithmetic and logical instructions (dec, inc, neg, not) ? two-operand arithmetic and logical instructions (adc, add, and, or, sbb, sub, xor). an invalid opcode exception is generated if the lock pre- fix is used with any other instruction or with one of the instructions above when no write operation to memory occurs (for example, when the destination is a register). 5.2.2 register sets the accessible registers in the processor are grouped into two sets: 1) the application register set contains the registers frequently used by application programmers. table 5-2 on page 91 shows the general purpose, segment, instruction pointer and eflags registers. 2) the system register set contains the registers typi- cally reserved for operating systems programmers: control, system address, debug, configuration, and test registers. all accesses to the these registers use special cpu instructions. both of these register sets are discussed in detail in the subsections that follow.
amd geode? lx processors data book 91 cpu core 33234h 5.3 application register set the application register set consists of the registers most often used by the applicati ons programmer. these regis- ters are generally accessible, although some bits in the eflags registers are protected. the general purpose register contents are frequently modified by instructions and typically contain arithmetic and logical instruction operands. in real mode, segment registers contain the base address for each segment. in protected mode, the seg- ment registers contain segment selectors. the segment selectors provide indexing for tables (located in memory) that contain the base address for each segment, as well as other memory addressing information. the instruction pointer register points to the next instruc- tion that the processor will execute. this register is auto- matically incremented by the processor as execution progresses. the eflags register contains control bits used to reflect the status of previously execut ed instructions. this register also contains control bits that affect the operation of some instructions. table 5-2. application register set 313029282726252423222120191817161514131211109876543210 general purpose registers ax ah al eax (extended a register) bx bh bl ebx (extended b register) cx ch cl ecx (extended c register) dx dh dl edx (extended d register) si (source index) esi (extended source index) di (destination index) edi (extended destination index) bp (base pointer) ebp (extended base pointer) sp (stack pointer) esp (extended stack pointer) segment (selector) registers cs (code segment) ss (stack segment) ds (d data segment) es (e data segment) fs (f data segment) gs (g data segment) instruction pointer and eflags registers eip (extended instruction pointer) esp (extended eflags register)
92 amd geode? lx processors data book cpu core 33234h 5.3.1 general purpose registers the general purpose registers are divided into four data registers, two pointer registers, and two index registers as shown in table 5-2 on page 91. the data registers are used by the applications program- mer to manipulate data structures and to hold the results of logical and arithmetic operations. different portions of gen- eral data registers can be addressed by using different names. an ?e? prefix identifies the complete 32-bit register. an ?x? suffix without the ?e? prefix id entifies the lower 16 bits of the register. the lower two bytes of a data register are addressed with an ?h? suffix (identifies the upper byte) or an ?l? suffix (identi- fies the lower byte). these _l and _h portions of the data registers act as independent registers. for example, if the ah register is written to by an instruction, the al register bits remain unchanged. the pointer and index registers are listed below. si or esi source index di or edi destination index sp or esp stack pointer bp or ebp base pointer these registers can be addressed as 16- or 32-bit registers, with the ?e? prefix indicating 32 bits. the pointer and index registers can be used as ge neral purpose registers; how- ever, some instructions use a fixed assignment of these registers. for example, repeated string operations always use esi as the source pointer, edi as the destination pointer, and ecx as a counter. the instructions that use fixed registers include multiply and divide, i/o access, string operations, stack operations, loop, variable shift and rotate, and translate instructions. the cpu core implements a st ack using the esp register. this stack is accessed during the push and pop instruc- tions, procedure calls, procedure returns, interrupts, excep- tions, and interrupt/exception returns. the geode lx processor automatically adjus ts the value of the esp dur- ing operations that result from these instructions. the ebp register may be used to refer to data passed on the stack during procedure calls. local data may also be placed on the stack and accessed with bp. this register provides a mechanism to access stack data in high-level languages. 5.3.2 segment registers the 16-bit segment registers are part of the main memory addressing mechanism. the six segment registers are: cs - code segment ds - data segment ss - stack segment es - extra segment fs - additional data segment gs - additional data segment the segment registers are us ed to select segments in main memory. a segment acts as private memory for differ- ent elements of a program such as code space, data space and stack space. there are two segment mechanisms, one for real and virtual 8086 operating modes and one for pro- tected mode. the active segment register is selected according to the rules listed in table 5-3 and the type of instruction being currently processed. in general, the ds register selector is used for data references. stack references use the ss reg- ister, and instruction fetches use the cs register. while some selections may be overridden, instruction fetches, stack operations, and the destination write operation of string operations cannot be overridden. special segment- override instruction prefixes a llow the use of alternate seg- ment registers. these segment registers include the es, fs, and gs registers. 5.3.3 instruction pointer register the instruction pointer (eip) register contains the offset into the current code segment of the next instruction to be executed. the register is normally incremented by the length of the current instruct ion with each instruction exe- cution unless it is implicitly modified through an interrupt, exception, or an instruction that changes the sequential execution flow (for example jmp and call). table 5-3. segment register selection rules type of memory reference implied (default) segment segment-override prefix code fetch cs none destination of push, pushf, int, call, pusha instructions ss none source of pop, popa, popf, iret, ret instructions ss none destination of stos, movs, rep stos, rep movs instructions es none other data references with effective address using base registers of: eax, ebx, ecx, edx, esi, edi, ebp, esp ds ss cs, es, fs, gs, ss cs, ds, es, fs, gs
amd geode? lx processors data book 93 cpu core 33234h 5.3.4 eflags register the eflags register contains status information and con- trols certain operations on the geode lx processor. the lower 16 bits of this register are used when executing 8086 or 80286 code. table 5-4 gives the bit formats for the eflags register. table 5-4. eflags register bit name flag type description 31:22 rsvd -- reserved. set to 0. 21 id system identification bit . the ability to set and clear this bit indicates that the cpuid instruction is sup- ported. the id can be modified only if the cpuid bit in ccr4 (index e8h[7]) is set. 20:19 rsvd -- reserved. set to 0. 18 ac system alignment check enable. in conjunction with the am flag (bit 18) in cr0, the ac flag deter- mines whether or not misaligned accesses to me mory cause a fault. if ac is set, alignment faults are enabled. 17 vm system virtual 8086 mode. if set while in protected mode, the pr ocessor switches to virtual 8086 oper- ation handling segment loads as the 8086 does, but generating exception 13 faults on privileged opcodes. the vm bit can be set by the iret instructi on (if current privilege level is 0) or by task switches at any privilege level. 16 rf debug resume flag. used in conjunction with debug register br eakpoints. rf is checked at instruction boundaries before breakpoint excepti on processing. if set, any debug fault is ignored on the next instruction. 15 rsvd -- reserved. set to 0. 14 nt system nested task. while executing in protected mode, nt i ndicates that the execution of the current task is nested within another task. 13:12 iopl system i/o privilege level. while executing in protected mode, iopl indicates the maximum current privilege level (cpl) permitted to execute i/o instructions without generating an exception 13 fault or consulting the i/o permi ssion bit map. iopl also indi cates the maximum cpl allowing alteration of the if bit when new values are popped into the eflags register. 11 of arithmetic overflow flag. set if the operation resulted in a carry or borrow into the sign bit of the result but did not result in a carry or borrow out of the hi gh-order bit. also set if the operation resulted in a carry or borrow out of the high-order bit but did not result in a carry or borrow into the sign bit of the result. 10 df control direction flag. when cleared, df causes string instru ctions to auto-increment (default) the appropriate index registers (esi and/or edi). se tting df causes auto-decrement of the index registers to occur. 9 if system interrupt enable flag. when set, maskable interrupts (intr input pin) are acknowledged and serviced by the cpu. 8 tf debug trap enable flag. once set, a single-step interrupt occurs after the next instruction completes execution. tf is cleared by the single-step interrupt. 7 sf arithmetic sign flag. set equal to high-order bit of result (0 indicates positive, 1 indicates negative). 6 zf arithmetic zero flag. set if result is zero; cleared otherwise. 5 rsvd -- reserved. set to 0. 4 af arithmetic auxiliary carry flag. set when a carry out of (addition) or borrow into (subtraction) bit position 3 of the result occurs; cleared otherwise. 3 rsvd -- reserved. set to 0. 2 pf arithmetic parity flag. set when the low-order 8 bits of the result contain an even number of ones; other- wise pf is cleared. 1 rsvd reserved. set to 1. 0 cf arithmetic carry flag. set when a carry out of (addition) or borro w into (subtraction) the most significant bit of the result occurs; cleared otherwise.
94 amd geode? lx processors data book cpu core 33234h 5.4 system register set the system register set, shown in table 5-5, consists of registers not generally used by application programmers. these registers are ei ther initialized by the system bios or employed by system level programmers who generate operating systems and memory management programs. associated with the system register set are certain tables and registers that are listed in table 5-5. the control registers control certain aspects of the cpu core such as paging, coprocessor functions, and segment protection. the cpu core configuration registers are used to initial- ize, provide for, test or define most of the features of the cpu core. the attributes of these registers include: ? cpu setup - enable cache, features, operating modes. ? debug support - provide debugging facilities for the geode? lx processor and enable the use of data access breakpoints and code execution breakpoints. ? built-in self-test (bist) support. ? test - support a mechanism to test the contents of the on-chip caches and the translation lookaside buffers (tlbs). ? in-circuit emulation (ice) - provide for a alternative accessing path to support an ice. ? cpu identification - allow the bios and other software to identify the specific cpu and stepping. ? power management. ? performance monitoring - enables test software to measure the performance of application software. the descriptor table registers point to tables used to manage memory segments and interrupts. the task state register points to the task state segment, which is used to save and load the processor state when switching tasks. table 5-5 lists the system regi ster sets along with their size and function. table 5-5. system register set group name function width (bits) control registers cr0 system control register 32 cr2 page fault linear address register 32 cr3 page directory base register 32 cr4 feature enables 32 cpu core configuration registers pln pipeline control registers 64 imn instruction memory control registers 64 dmn data memory con- trol registers 64 bcn bus controller con- trol registers 64 fpun floating point unit shadow registers 64 descriptor ta b l e registers gdtr gdt register 32 idtr idt register 32 ldtr ldt register 16 task register tr task register 16 performance registers pcrn performance control registers 8
amd geode? lx processors data book 95 cpu core 33234h 5.4.1 control registers a map of the control registers (cr0, cr1, cr2, cr3, and cr4) is shown in table 5-6 and the bit descriptions are in the tables that follow. (thes e registers should not be con- fused with the crrn registers.) cr0 contains system con- trol bits that configure operating modes and indicate the general state of the cpu. the lower 16 bits of cr0 are referred to as the machine status word (msw). when operating in real mode, any program can read and write the control registers. in protected mode, however, only privilege level 0 (most-privileged) programs can read and write these registers. l1 cache controller the geode lx processor contains an on-board 64 kb l1 instruction cache, a 64 kb l1 write-back data cache, and a 128 kb unified l2 victim cache. with the memory controller on-board, the l1 cache requires no external logic to main- tain coherency. all dma cycles automatically snoop the l1 and l2 caches. the cd bit (cache disable, bit 30) in cr0 globally controls the operating mode of the l1 and l2 caches. lcd and lwt, local cache disable and local write-through bits in the translation lookaside buffer, control the mode on a page-by-page basis. additionally, memory configuration control can specify certain memory regions as non-cache- able. if the cache is disabled, no further cache line fills occur. however, data already present in the cache continues to be used. for the cache to be completely disabled, the cache must be invalidated with a wbinvd instruction after the cache has been disabled. write-back caching improves performance by relieving con- gestion on slower external buses. the geode lx processor caches smm regions, reducing system management overhead to allow for hardware emu- lation such as vga. table 5-6. control registers map 313029282726252423222120191817161514131211109876543210 cr4 register control register 4 (r/w) rsvd pce pge rsvd pse de tsc rsvd cr3 register control register 3 (r/w) pdbr (page directory base register) rsvd 0 0 rsvd cr2 register control register 2 (r/w) pfla (page fault linear address) cr1 register control register 1 (r/w) rsvd cr0 register control register 0 (r/w) pg cd nw rsvd am rsvd wp rsvd ne rsvd ts em mp pe machine status word (msw)
96 amd geode? lx processors data book cpu core 33234h table 5-7. cr4 bit descriptions bit name description 31:9 rsvd reserved. set to 0 (always returns 0 when read). 8pce performance counter enable. set pce = 1 to make rdpmc available at nonzero privi- lege levels. 7pge page global enable. set pge = 1 to make global pa ges immune to invlpg instruc- tions. 6:5 rsvd reserved. set to 0 (always returns 0 when read). 4 pse page size extensions . set pse = 1 to enable 4 mb pages. 3de debug extensions. set de = 1 to enable debug extensions (i.e., dr4, dr5, and i/o breakpoints). 2tsc time stamp counter instruction. 0: rdtsc instruction enab led for all cpl states. 1: rdtsc instruction enabled for cpl = 0 only. 1:0 rsvd reserved. set to 0 (always returns 0 when read). table 5-8. cr3 bit descriptions bit name description 31:12 pdbr page directory base register. identifies page directory base address on a 4 kb page boundary. 11:0 rsvd reserved. set to 0. table 5-9. cr2 bit descriptions bit name description 31:0 pfla page fault linear address. with paging enabled and after a page fault, pfla contains the linear address of the address that caused the page fault. table 5-10. cr0 bit descriptions bit name description 31 pg paging enable bit . if pg = 1 and protected mode is enabled (pe = 1), paging is enabled. after changing the state of pg, so ftware must execute an unconditional branch instruction (e.g., jmp, call) to have the change take effect.
amd geode? lx processors data book 97 cpu core 33234h 30 cd cache disable/not write-through (snoop). cache behavior is based on the cr0 cd and nw bits. cd nw 0 0 normal cache operation, coherency maintained. read hits access the cache, write hits update the cache, read/write misses may cause line allocations based on memory region configuration settings. 0 1 invalid, causes a general protection fault (gpf). 1 0 cache off, coherency maintained (i.e., snooping enabled). read hits access the cache, write hits update the cache, read/write misses do not cause line allocations. 1 1 cache off, coherency not maintained (i.e., snooping disabled). read hits access the cache, write hits update the cache, read/write misses do not cause line allocations. 29 nw 28:19 rsvd reserved. 18 am alignment check mask . if am = 1, the ac bit in the eflags register is unmasked and allowed to enable alignment check faults. setting am = 0 prevents ac faults from occur- ring. 17 rsvd reserved 16 wp write protec t. protects read only pages from supervisor write access. wp = 0 allows a read only page to be written from privilege leve l 0-2. wp = 1 forces a fault on a write to a read only page from any privilege level. 15:6 rsvd reserved. 5ne numerics exception . ne = 1 to allow fpu exceptions to be handled by interrupt 16. ne = 0 if fpu exceptions are to be handled by external interrupts. 4et (ro) extension type (read only). (default = 1) 3ts task switched . set whenever a task switch operation is performed. execution of a float- ing point instruction with ts = 1 causes a device not available (dna) fault. if mp = 1 and ts = 1, a wait instruction also causes a dna fault. (note 1) 2em emulate processor extension . if em = 1, all floating point instructions cause a dna fault 7. (note 1) 1mp monitor processor extension . if mp = 1 and ts = 1, a wait instruction causes dna fault 7. the ts bit is set to 1 on task switch es by the cpu. floating point instructions are not affected by the state of the mp bit. the mp bit should be set to 1 during normal oper- ations. (note 1) 0pe protected mode enable . enables the segment based prot ection mechanism. if pe = 1, protected mode is enabled. if pe = 0, the cpu operates in real mode and addresses are formed as in an 8086-style cpu. note 1. for effects of various combinations of the ts, em, and mp bits, see table 5-11 on page 98. table 5-10. cr0 bit descriptions (continued) bit name description
98 amd geode? lx processors data book cpu core 33234h table 5-11. effects of various combinations of em, ts, and mp bits cr0[3:1] instruction type ts em mp wait esc 000 execute execute 001 execute execute 1 0 0 execute fault 7 101 fault 7 fault 7 0 1 0 execute fault 7 0 1 1 execute fault 7 1 1 0 execute fault 7 111 fault 7 fault 7
amd geode? lx processors data book 99 cpu core register descriptions 33234h 5.5 cpu core register descriptions all cpu core registers are model specific registers (msrs) and are accessed via the rdmsr and wrmsr instructions. each module inside the processor is assigned a 256 regis- ter section of the address space. the module responds to any reads or writes in that range. unused addresses within a module?s address space are reserved, meaning the mod- ule returns zeroes on a read and ignores writes. addresses that are outside all the modul e address spaces are invalid, meaning a rdmsr/wrmsr instruction attempting to use the address generates a general protection fault. the registers associated with the cpu core are the stan- dard geodelink? device msrs and cpu core specific msrs. table 5-12 and table 5-13 are register summary tables that include reset values and page references where the bit descriptions are provid ed. note that the standard gld msrs for the cpu core start at 00002000h. table 5-12. standard geodelink? device msrs summary msr address type register name reset value reference 00002000h ro gld capabilities msr (gld_msr_cap) 00000000_000864xxh page 108 00002001h r/w gld master configuration msr (gld_msr_config) 00000000_00000320h page 108 00002002h r/w gld smi msr (gld_msr_smi) - not used 00000000_00000000h page 109 00002003h r/w gld error msr (gld_msr_error) - not used 00000000_00000000h page 109 00002004h r/w gld power management msr (gld_msr_pm) - not used 00000000_00000000h page 109 00002005h r/w gld diagnostic bus control msr (gld_msr_diag) 00000000_00000000h page 109 table 5-13. cpu core specific msrs summary msr address type register name reset value reference 00000010h r/w time stamp counter ms r (tsc_msr) 00000000_00000000h page 110 000000c1h r/w performance event counter 0 msr (perf_cnt0_msr) 00000000_00000000h page 110 000000c2h r/w performance event counter 1 msr (perf_cnt1_msr) 00000000_00000000h page 111 00000174h r/w sysenter/sysexit code segment selector msr (sys_cs_msr) 00000000_c09b0000h page 112 00000175h r/w sysenter/sysexit stack pointer msr (sys_sp_msr) 00000000_00000000h page 113 00000176h r/w sysenter/sysexit instruction pointer msr (sys_ip_msr) 00000000_00000000h page 113 00000186h r/w performance event counter 0 select msr (perf_sel0_msr 00000000_00000000h page 114 00000187h r/w performance event counter 1 select msr (perf_sel1_msr) 00000000_00000000h page 114 00001100h r/w instruction fetch configuration msr (if_config_msr) 00000000_00005051h page 115 00001102h w if invalidate msr (if_invalidate_msr) 00000000_00000000h page 118 00001108h r/w if test address msr (if_test_addr_msr) 00000000_00000000h page 118 00001109h r/w if test data msr (if_test_data_msr) 00000000_xxxxxxxxh page 119
100 amd geode? lx processors data book cpu core register descriptions 33234h 00001110h ro if sequential count mrs (if_seqcount_msr) 00000000_00000000h page 122 00001140h ro if built-in self-test ms r (if_bist_msr) 00000000_00000000h page 123 00001210h r/w exception unit (xc) configuration msr (xc_config_msr) 00000000_00000000h page 124 00001211h r/w xc mode msr (xc_mode_msr) 00000000_00000000h page 125 00001212h ro xc history msr (xc_hist_msr) 00000000_00000000h page 126 00001213h ro xc microcode address msr (xc_uaddr_msr) 00000000_00000000h page 127 00001250h r/w id configuration msr (i d_config_msr) 00000000_00000002h page 127 00001301h r/w smm control msr (smm_ctl_msr) 00000000_00000000h page 128 00001302h r/w debug management interrupt (dmi) control reg- ister 00000000_00000000h page 129 00001310h r/w temporary 0 msr (temp0_msr) xxxxxxxx_xxxxxxxxh page 130 00001311h r/w temporary 1 msr (temp1_msr) xxxxxxxx_xxxxxxxxh page 130 00001312h r/w temporary 2 msr (temp2_msr) xxxxxxxx_xxxxxxxxh page 130 00001313h r/w temporary 3 msr (temp3_msr) xxxxxxxx_xxxxxxxxh page 130 00001320h r/w es segment selector/flags register (es_sel_msr) xxxxxxxx_xxxxxxxxh page 131 00001321h r/w cs segment sele ctor/flags register (cs_sel_msr) xxxxxxxx_xxxxxxxxh page 131 00001322h r/w ss segment selector/flags register (ss_sel_msr) xxxxxxxx_xxxxxxxxh page 131 00001323h r/w ds segment sele ctor/flags register (ds_sel_msr) xxxxxxxx_xxxxxxxxh page 131 00001324h r/w fs segment selector/flags register (fs_sel_msr) xxxxxxxx_xxxxxxxxh page 131 00001325h r/w gs segment selector/flags register (gs_sel_msr) xxxxxxxx_xxxxxxxxh page 131 00001326h r/w ldt segment se lector/flags register (ldt_sel_msr) xxxxxxxx_xxxxxxxxh page 131 00001327h r/w temp segment selector/flags register (tm_sel_msr) xxxxxxxx_xxxxxxxxh page 131 00001328h r/w tss segment selector/flags register (tss_sel_msr) xxxxxxxx_xxxxxxxxh page 131 00001329h r/w idt segment se lector/flags register (idt_sel_msr) xxxxxxxx_xxxxxxxxh page 131 0000132ah r/w gdt segment se lector/flags register (gdt_sel_msr) xxxxxxxx_xxxxxxxxh page 131 0000132bh r/w smm header msr (smm_hdr_msr) 00000000_00000000h page 132 0000132ch r/w dmm header msr (dmm_hdr_msr) 00000000_00000000h page 133 00001330h r/w es segment base/limit msr (es_base_msr) xxxxxxxx_xxxxxxxxh page 134 00001331h r/w cs segment base/limit msr (cs_base_msr) xxxxxxxx_xxxxxxxxh page 134 00001332h r/w ss segment base/limit msr (ss_base_msr) xxxxxxxx_xxxxxxxxh page 134 00001333h r/w ds segment base/limit msr (ds_base_msr) xxxxxxxx_xxxxxxxxh page 134 00001334h r/w fs segment base/limit msr (fs_base_msr) xxxxxxxx_xxxxxxxxh page 134 table 5-13. cpu core specific msrs summary (continued) msr address type register name reset value reference
amd geode? lx processors data book 101 cpu core register descriptions 33234h 00001335h r/w gs segment base/limit msr (gs_base_msr) xxxxxxxx_xxxxxxxxh page 134 00001336h r/w ldt segment base/limit msr (ldt_base_msr) xxxxxxxx_xxxxxxxxh page 134 00001337h r/w temp segment base/limit msr (temp_base_msr) xxxxxxxx_xxxxxxxxh page 134 00001338h r/w tss segment base/limit msr (tss_base_msr) xxxxxxxx_xxxxxxxxh page 134 00001339h r/w idt segment base/limit msr (idt_base_msr) xxxxxxxx_xxxxxxxxh page 134 0000133ah r/w gdt segment base/limit msr (gdt_base_msr) xxxxxxxx_xxxxxxxxh page 134 0000133bh r/w smm segment base/limit msr (smm_base_msr xxxxxxxx_xxxxxxxxh page 134 0000133ch r/w dmm segment base/ limit msr (dmm_base_msr) xxxxxxxx_xxxxxxxxh page 134 00001340h r/w debug registers 1 and 0 msr (dr1_dr0_msr) xxxxxxxx_xxxxxxxxh page 135 00001341h r/w debug registers 3 and 2 msr (dr3_dr2_msr) xxxxxxxx_xxxxxxxxh page 135 00001343h r/w debug registers 7 and 6 ms r (dr6_dr7_msr) 00000000_ffff0000h page 136 00001350h r/w extended debug registers 1 and 0 msr (xdr1_xdr0_msr) 00000000_00000000h page 137 00001351h r/w extended debug registers 3 and 2 msr (xdr3_xdr2_msr) 00000000_00000000h page 137 00001352h r/w extended debug registers 5 and 4 msr (xdr5_xdr4_msr) ffffffff_00000000h page 138 00001353h r/w extended debug registers 7 and 6 msr (xdr7_xdr6_msr) xxxxxxxx_xxxxxxxxh page 138 00001354h r/w extended debug registers 9 and 8 msr (xdr9_xdr8_msr) ffffffff_00000000h page 140 00001355h r/w extended debug registers 11 and 10 msr (xdr11_xdr10_msr) xxxxxxxx_xxxx0000h page 141 00001360h r/w ex stage instruction pointe r msr (ex_ip_msr) 00000000_00000000h page 141 00001361h r/w wb stage instruction pointe r msr (wb_ip_msr) 00000000_00000000h page 142 00001364h ro ex stage linear instruction pointer msr (ex_lip_msr) 00000000_00000000h page 142 00001365h ro wb stage linear instruction pointer msr (wb_lip_msr) 00000000_00000000h page 143 00001366h ro c1/c0 linear instruction pointer msr (c1_c0_lip_msr) 00000000_00000000h page 143 00001367h ro c3/c2 linear instruction pointer msr (c3_c2_lip_msr) 00000000_00000000h page 144 00001370h r/w floating point environment code segment (fpenv_cs_msr) 00000000_00000000h page 144 00001371h r/w floating point environment instruction pointer (fpenv_ip_msr) 00000000_00000000h page 145 00001372h r/w floating point environment data segment (fpenv_ds_msr) 00000000_00000000h page 145 00001373h r/w floating point environment data pointer (fpenv_dp_msr) 00000000_00000000h page 146 table 5-13. cpu core specific msrs summary (continued) msr address type register name reset value reference
102 amd geode? lx processors data book cpu core register descriptions 33234h 00001374h r/w floating point environment opcode pointer (fpenv_op_msr) 00000000_00000000h page 146 00001380h ro address calculatio n unit configuration msr (ac_config_msr) 00000000_00000000h page 147 00001408h r/w general register eax msr (gr_eax_msr) 00000000_00000000h page 148 00001409h r/w general register ecx msr (gr_ecx_msr) 00000000_00000000h page 148 0000140ah r/w general register edx msr (gr_edx_msr) 00000000_00000000h page 148 0000140bh r/w general register ebx msr (gr_ebx_msr) 00000000_00000000h page 148 0000140ch r/w general register esp msr (gr_esp_msr) 00000000_00000000h page 148 0000140dh r/w general register ebp msr (gr_ebp_msr) 00000000_00000000h page 148 0000140eh r/w general register esi msr (gr_esi_msr) 00000000_00000000h page 148 0000140fh r/w general register edi msr (gr_edi_msr) 00000000_00000000h page 148 00001410h r/w general register temp 0 msr (gr_temp0_msr) 00000000_00000000h page 148 00001411h r/w general register temp 1 msr (gr_temp1_msr) 00000000_00000000h page 148 00001412h r/w general register temp 2 msr (gr_temp2_msr) 00000000_00000000h page 148 00001413h r/w general register temp 3 msr (gr_temp3_msr) 00000000_00000000h page 148 00001414h r/w general register temp 4 msr (gr_temp4_msr) 00000000_00000000h page 148 00001415h r/w general register temp 5 msr (gr_temp5_msr) 00000000_00000000h page 148 00001416h r/w general register temp 6 msr (gr_temp6_msr) 00000000_00000000h page 148 00001417h r/w general register temp 7 msr (gr_temp7_msr) 00000000_00000000h page 148 00001418h r/w extended flags msr (eflag_msr) 00000000_00000002h page 149 00001420h r/w control register 0 msr (cr0_msr) 00000000_60000010h page 149 00001700h r/w instruction memory configuration msr (im_config_msr) 00000000_00000000h page 150 00001710h r/w instruction cache index ms r (ic_index_msr) 00000000_00000000h page 152 00001711h r/w instruction cache data msr (ic_data_msr) xxxxxxxx_xxxxxxxxh page 152 00001712h r/w instruction cache tag (ic_tag_msr) 00000000_00000000h page 153 00001713h r/w instruction cache tag with increment (ic_tag_i_msr) 00000000_00000000h page 154 00001714h ro l0 instruction cache data msr (l0_ic_data_msr) xxxxxxxx_xxxxxxxxh page 154 00001715h ro l0 instruction cache tag with increment msr (l0_ic_tag_i_msr) 00000000_xxxxxxxxh page 154 00001720h r/w l1 instruction tlb index (itb_index_msr) 00000000_0000000xh page 155 00001721h r/w l1 instruction tlb least recently used msr (itb_lru_msr) 00000000_00000000h page 156 table 5-13. cpu core specific msrs summary (continued) msr address type register name reset value reference
amd geode? lx processors data book 103 cpu core register descriptions 33234h 00001722h r/w itb entry msr (itb_entry_msr) xxxxxxxx_xxxxxxxxh page 157 00001723h r/w itb entry with increment msr (itb_entry_i_msr) xxxxxxxx_xxxxxxxxh page 157 00001724h r/w itb l0 cache entry msr (itb_l0_entry_msr) xxxxxxxx_xxxxxxxxh page 157 00001730h ro instruction memory subsystem bist tag msr (im_bist_tag_msr) 00000000_0000000xh page 158 00001731h ro instruction memory subsystem bist data msr (im_bist_data_msr) 00000000_0000000xh page 158 00001800h r/w data memory sub system configuration 0 msr (dm_config0_msr) 00000000_00000000h page 159 00001801h r/w data memory sub system configuration 1 msr (dm_config1_msr) 00000000_00000000h page 162 00001804h r/w data memory subsystem prefetch lock msr (dm_pflock_msr) 00000000_00000000h page 163 00001808h r/w default region c onfiguration properties msr (rconf_default_msr) 01fffff0_10000001h page 164 warm start value: 04xxxxx0_1xxxxx01h 0000180ah r/w region configuration bypass msr (rconf_bypass_msr) 00000000_00000101h page 165 warm start value: 00000000_00000219h 0000180bh r/w region configuration a0000-bffff msr (rconf_a0_bf_msr) 01010101_01010101h page 165 warm start value: 19191919_19191919h 0000180ch r/w region configur ation c0000-dffff msr (rconf_c0_df_msr) 01010101_01010101h page 166 warm start value: 19191919_19191919h 0000180dh r/w region configur ation e0000-fffff msr (rconf_e0_ff_msr) 01010101_01010101h page 166 warm start value: 19191919_19191919h 0000180eh r/w region configuration smm msr (rconf_smm_msr) 00000001_00000001h page 167 warm start value: xxxxx001_xxxxx005h 0000180fh r/w region configuration dmm msr (rconf_dmm_msr) 00000001_00000001h page 168 warm start value: xxxxx001_xxxxx005h 00001810h r/w region configuration range 0 msr (rconf0_msr) 00000000_00000000h page 169 warm start value: xxxxx000_xxxxx0xxh 00001811h r/w region configuration range 1 msr (rconf1_msr) 00000000_00000000h page 169 warm start value: xxxxx000_xxxxx0xxh 00001812h r/w region configuration range 2 msr (rconf2_msr) 00000000_00000000h page 169 warm start value: xxxxx000_xxxxx0xxh table 5-13. cpu core specific msrs summary (continued) msr address type register name reset value reference
104 amd geode? lx processors data book cpu core register descriptions 33234h 00001813h r/w region configuration range 3 msr (rconf3_msr) 00000000_00000000h page 169 warm start value: xxxxx000_xxxxx0xxh 00001814h r/w region configuration range 4 msr (rconf4_msr) 00000000_00000000h page 169 warm start value: xxxxx000_xxxxx0xxh 00001815h r/w region configuration range 5 msr (rconf5_msr) 00000000_00000000h page 169 warm start value: xxxxx000_xxxxx0xxh 00001816h r/w region configuration range 6 msr (rconf6_msr) 00000000_00000000h page 169 warm start value: xxxxx000_xxxxx0xxh 00001817h r/w region configuration range 7 msr (rconf7_msr) 00000000_00000000h page 169 warm start value: xxxxx000_xxxxx0xxh 00001881h r/w x86 control register 1 msr (cr1_msr) 00000000_xxxxxxxxh page 172 00001882h r/w x86 control register 2 msr (cr2_msr) 00000000_xxxxxxxxh page 172 00001883h r/w x86 control register 3 msr (cr3_msr) 00000000_xxxxxxxxh page 172 00001884h r/w x86 control register 4 msr (cr4_msr) 00000000_xxxxxxxxh page 172 00001890h r/w data cache index msr ( dc_index_msr) 00000000_00000000h page 172 00001891h r/w data cache data msr (dc_data_msr) 00000000_00000000h page 173 00001892h r/w data cache tag msr (dc_tag_msr) 00000000_00000000h page 173 00001893h r/w data cache t ag with increment msr (dc_tag_i_msr) 00000000_00000000h page 174 00001894h wo data/instruction cache snoop register (snoop_msr) 00000000_xxxxxxxxh page 175 00001898h r/w l1 data tlb index register (l1dtlb_index_msr) 00000000_00000000h page 175 00001899h r/w l1 data tlb least recently used msr (l1dtlb_lru_msr) 00000000_00000000h page 176 0000189ah r/w l1 data tlb entry msr (l1dtlb_entry_msr) 00000000_00000000h page 177 0000189bh r/w l1 data tlb entry with increment msr (l1dtlb_entry_i_msr) 00000000_00000000h page 178 0000189ch r/w l2 tlb/dte/pte index msr (l2tlb_index_msr) 00000000_00000000h page 178 0000189dh r/w l2 tlb/dte/pte least recently used msr (l2tlb_lru_msr) 00000000_00000000h page 179 0000189eh r/w l2 tlb/dte/pte entry msr (l2tlb_entry_msr) 00000000_00000000h page 180 0000189fh r/w l2 tlb/dte/pte entry with increment msr (l2tlb_entry_i_msr) 00000000_00000000h page 182 000018c0h r/w data memory subsystem built-in self-test msr (dm_bist_msr) 00000000_00000000h page 182 00001900h r/w bus controller configuration 0 msr (bc_config0_msr) 00000000_00000111h page 183 table 5-13. cpu core specific msrs summary (continued) msr address type register name reset value reference
amd geode? lx processors data book 105 cpu core register descriptions 33234h 00001901h r/w bus controller configuration 1 msr (bc_config1_msr) 00000000_00000000h page 184 00001904h ro reserved status msr (rsvd_sts_msr) 00000000_00000000h page 185 00001908h r/w msr lock msr (msr_lock_msr) 00000000_00000000h page 185 00001910h r/w real time stamp counter msr (rtsc_msr) 00000000_00000000h page 186 00001911h ro tsc and rtsc low dwords msr (rtsc_tsc_msr) 00000000_00000000h page 186 00001920h r/w l2 cache configuration msr (l2_config_msr) 00000000_0000000eh page 187 00001921h ro l2 cache status msr (l2_status_msr) 00000000_00000001h page 188 00001922h r/w l2 cache index msr (l2_index_msr) 00000000_00000000h page 188 00001923h r/w l2 cache data msr (l2_data_msr) 00000000_00000000h page 189 00001924h r/w l2 cache tag msr (l2_tag_msr) 00000000_00000000h page 189 00001925h r/w l2 cache tag with increment msr (l2_tag_i_msr) 00000000_00000000h page 190 00001926h r/w l2 cache built-in self-test msr (l2_bist_msr) 00000000_00000000h page 190 00001927h r/w l2 cache treatment control msr (l2_trtmnt_ctl_msr) 00000000_00000000h page 192 00001930h r/w power mode msr (pmode_msr) 00000000_00000300h page 193 00001950h r/w bus controller extended debug registers 1 and 0 msr (bxdr1_bxdr0_msr) 00000000_00000000h page 194 00001951h r/w bus controller extended debug registers 3 and 2 msr (bxdr3_bxdr2_msr) 00000000_00000000h page 194 00001953h r/w bus controller extended debug registers 6 and 7 msr (bxdr6_bxdr7_msr) 00000000_00000000h page 195 00001970h r/w bus controller debug register 0 msr (bdr0_msr) 00000000_00000000h page 197 00001971h r/w bus controller debug register 1 msr (bdr1_msr) 00000000_00000000h page 197 00001972h r/w bus controller debug register 2 msr (bdr2_msr) 00000000_00000000h page 197 00001973h r/w bus controller debug register 3 msr (bdr3_msr) 00000000_00000000h page 197 00001976h r/w bus controller debug register 6 msr (bdr6_msr) 00000000_00000000h page 198 00001977h r/w bus controller debug register 7 msr (bdr7_msr) 00000000_00000000h page 198 00001980h r/w memory subsystem array control enable msr (mss_array_ctl_en_msr) 00000000_00000000h page 200 00001981h r/w memory subsystem array control 0 msr (mss_array_ctl0_msr) 00000000_2010f3c9h page 200 00001982h r/w memory subsystem array control 1 msr (mss_array_ctl1_msr) 00000000_104823cfh page 201 00001983h r/w memory subsystem array control 2 msr (mss_array_ctl2_msr) 00000104_820c30c3h page 201 00001a00h r/w fpu modes msr (fp_mode_msr) 00000000_00000000h page 202 table 5-13. cpu core specific msrs summary (continued) msr address type register name reset value reference
106 amd geode? lx processors data book cpu core register descriptions 33234h 00001a03h r/w fpu reserved msr (fpu_rsvd_msr) 00000000_00000000h page 202 00001a10h r/w fpu x87 control word msr (fpu_cw_msr) 00000000_00000040h page 203 00001a11h r/w fpu x87 status word msr (fpu_sw_msr) 00000000_00000000h page 203 00001a12h r/w fpu x87 tag word msr (fpu_tw_msr) 00000000_00000000h page 203 00001a13h ro fpu busy msr (fpu_busy_msr) 00000000_00000000h page 204 00001a14h ro fpu register map msr (fpu_map_msr) 00000000_76543210h page 204 00001a40h r/w mantissa of r0 ms r (fpu_mr0_msr) xxxxxxxx_xxxxxxxxh page 205 00001a41h r/w exponent of r0 msr (fpu_er0_msr) 00000000_0000xxxxh page 206 00001a42h r/w mantissa of r1 ms r (fpu_mr1_msr) xxxxxxxx_xxxxxxxxh page 205 00001a43h r/w exponent of r1 msr (fpu_er1_msr) 00000000_0000xxxxh page 206 00001a44h r/w mantissa of r2 ms r (fpu_mr2_msr) xxxxxxxx_xxxxxxxxh page 205 00001a45h r/w exponent of r2 msr (fpu_er2_msr) 00000000_0000xxxxh page 206 00001a46h r/w mantissa of r3 ms r (fpu_mr3_msr) xxxxxxxx_xxxxxxxxh page 205 00001a47h r/w exponent of r3 msr (fpu_er3_msr) 00000000_0000xxxxh page 206 00001a48h r/w mantissa of r4 ms r (fpu_mr4_msr) xxxxxxxx_xxxxxxxxh page 205 00001a49h r/w exponent of r4 msr (fpu_er4_msr) 00000000_0000xxxxh page 206 00001a4ah r/w mantissa of r5 msr (fpu_mr5_msr) xxxxxxxx_xxxxxxxxh page 205 00001a4bh r/w exponent of r5 msr (fpu_er5_msr) 00000000_0000xxxxh page 206 00001a4ch r/w mantissa of r6 msr (fpu_mr6_msr) xxxxxxxx_xxxxxxxxh page 205 00001a4dh r/w exponent of r6 msr (fpu_er6_msr) 00000000_0000xxxxh page 206 00001a4eh r/w mantissa of r7 msr (fpu_mr7_msr) xxxxxxxx_xxxxxxxxh page 205 00001a4fh r/w exponent of r7 msr (fpu_er7_msr) 00000000_0000xxxxh page 206 00001a50h r/w mantissa of r8 ms r (fpu_mr8_msr) xxxxxxxx_xxxxxxxxh page 205 00001a51h r/w exponent of r8 msr (fpu_er8_msr) 00000000_0000xxxxh page 206 00001a52h r/w mantissa of r9 ms r (fpu_mr9_msr) xxxxxxxx_xxxxxxxxh page 205 00001a53h r/w exponent of r9 msr (fpu_er9_msr) 00000000_0000xxxxh page 206 00001a54h r/w mantissa of r10 ms r (fpu_mr10_msr) xxxxxxxx_xxxxxxxxh page 205 00001a55h r/w exponent of r10 msr (fpu_er10_msr) 00000000_0000xxxxh page 206 00001a56h r/w mantissa of r11 ms r (fpu_mr11_msr) xxxxxxxx_xxxxxxxxh page 205 00001a57h r/w exponent of r11 msr (fpu_er11_msr) 00000000_0000xxxxh page 206 00001a58h r/w mantissa of r12 ms r (fpu_mr12_msr) xxxxxxxx_xxxxxxxxh page 205 00001a59h r/w exponent of r12 msr (fpu_er12_msr) 00000000_0000xxxxh page 206 00001a5ah r/w mantissa of r13 ms r (fpu_mr13_msr) xxxxxxxx_xxxxxxxxh page 205 00001a5bh r/w exponent of r13 msr (fpu_er13_msr) 00000000_0000xxxxh page 206 00001a5ch r/w mantissa of r14 msr (fpu_mr14_msr) xxxxxxxx_xxxxxxxxh page 205 00001a5dh r/w exponent of r14 msr (fpu_er14_msr) 00000000_0000xxxxh page 206 00001a5eh r/w mantissa of r15 ms r (fpu_mr15_msr) xxxxxxxx_xxxxxxxxh page 205 00001a5fh r/w exponent of r15 msr (fpu_er15_msr) 00000000_0000xxxxh page 206 00001a60h- 00001a6fh r/w fpu reserved msrs (fpu_rsvd_msr) xxxxxxxx_xxxxxxxxh page 207 table 5-13. cpu core specific msrs summary (continued) msr address type register name reset value reference
amd geode? lx processors data book 107 cpu core register descriptions 33234h 00003000h r/w standard levels and vendor id string 1 (cpuid0_msr) 68747541_00000001h page 207 00003001h r/w vendor id strings 2 and 3 (cpuid1_msr) 69746e65_444d4163h page 207 00003002h r/w type/family/model/step (cpuid2_msr) 00000400_000005a2h page 207 00003003h r/w feature flags (cpuid3_msr) 0088a93d_00000000h page 207 00003004h wo reserved (cpuid4_msr) 00000000_00000000h page 207 00003005h wo reserved (cpuid5_msr) 00000000_00000000h page 207 00003006h r/w max extended levels 1 (cpuid6_msr) 68747541_80000006h page 207 00003007h r/w max extended levels 2 (cpuid7_msr) 69746e65_444d4163h page 207 00003008h r/w extended type/fa mily/model/stepping (cpuid8_msr) 00000000_000005a1h page 207 00003009h r/w extended feature flags (cpuid9_msr) c0c0a13d_00000000h page 207 0000300ah r/w cpu marketing name 1 (cpuida_msr) 4d542865_646f6547h page 207 0000300bh r/w cpu marketing name 2 (cpuidb_msr) 72676574_6e492029h page 207 0000300ch r/w cpu marketing name 3 (cpuidc_msr) 6f725020_64657461h page 207 0000300dh r/w cpu marketing name 4 (cpuidd_msr) 6220726f_73736563h page 207 0000300eh r/w cpu marketing name 5 (cpuide_msr) 43502044_4d412079h page 207 0000300fh r/w cpu marketing name 6 (cpuidf_msr) 00000000_00000053h page 207 00003010h r/w l1 tlb information (cpuid10_msr) ff10ff10_00000000h page 207 00003011h r/w l1 cache information (cpuid11_msr) 40100120_40100120h page 207 00003012h r/w l2 tlb information (cpuid12_msr) 00002040_0000f004h page 207 00003013h r/w l2 cache information (cpuid13_msr) 00000000_00804120h page 207 table 5-13. cpu core specific msrs summary (continued) msr address type register name reset value reference
108 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.1 standard geodelink? device msrs 5.5.1.1 gld capabilities msr (gld_msr_cap) 5.5.1.2 gld master configur ation msr (gld_msr_config) msr address 00002000h ty p e r o reset value 00000000_000864xxh gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. reads as 0. 23:8 dev_id device id. identifies device (0864h). 7:0 rev_id revision id. identifies device revision. see amd geode? lx processors specification update document for value. msr address 00002001h ty p e r / w reset value 00000000_00000320h gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd rsvd pri0 rsvd pid gld_msr_config bit descriptions bit name description 63:11 rsvd reserved. write as read. 10:7 rsvd reserved. (default = 3) 6:4 pri0 priority level. priority value used for cpu core gliu requests. (default = 2) 3 rsvd reserved. write as read. 2:0 pid priority id value. priority id value used for cpu core gliu requests. always write to 0. (default = 0)
amd geode? lx processors data book 109 cpu core register descriptions 33234h 5.5.1.3 gld smi msr (gld_msr_smi) this register is not used in the cpu core module. 5.5.1.4 gld error msr (gld_msr_error) this register is not used in the cpu core module. 5.5.1.5 gld power management msr (gld_msr_pm) this register is not used in the cpu core module. 5.5.1.6 gld diagnostic bus control msr (gld_msr_diag) this register is reserved for internal use by amd and should not be written to. msr address 00002002h ty p e r / w reset value 00000000_00000000h msr address 00002003h ty p e r / w reset value 00000000_00000000h msr address 00002004h ty p e r / w reset value 00000000_00000000h msr address 00002005h ty p e r / w reset value 00000000_00000000h
110 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2 cpu core specific msrs 5.5.2.1 time stamp counter msr (tsc_msr) 5.5.2.2 performance event co unter 0 msr (perf_cnt0_msr) msr address 00000010h ty p e r / w reset value 00000000_00000000h tsc_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 tsc (high dword) 313029282726252423222120191817161514131211109876543210 tsc (low dword) tsc_msr bit descriptions bit name description 63:0 tsc time stamp counter. this register is the 64-bit time stamp counter, also readable via the rdtsc instruction. bus controller configuration 0 register (m sr 00001900h) contains configuration bits that determine if tsc counts duri ng smm, dmm, or suspend modes. writes to this register clears the upper dw ord to 0. the lower dword is written nor- mally. msr address 000000c1h ty p e r / w reset value 00000000_00000000h perf_cnt0_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd perf_cnt0 (high byte) 313029282726252423222120191817161514131211109876543210 perf_cnt0 (low dword) perf_cnt0_msr bit descriptions bit name description 63:40 rsvd reserved. write as read. 39:0 perf_cnt0 performance event counter 0. this register is a 40-bit event counter used to count events or conditions inside of the cpu core. this counter is controlled by performance event counter 0 select msr (msr 00000186h).
amd geode? lx processors data book 111 cpu core register descriptions 33234h 5.5.2.3 performance event co unter 1 msr (perf_cnt1_msr) msr address 000000c2h ty p e r / w reset value 00000000_00000000h perf_cnt1_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd perf_cnt1 (high byte) 313029282726252423222120191817161514131211109876543210 perf_cnt1 (low dword) perf_cnt1_msr bit descriptions bit name description 63:40 rsvd reserved. write as read. 39:0 perf_cnt1 performance event counter 1. this register is a 40-bit event counter used to count events or conditions inside the cpu core. this counter is controlled by performance event counter 1 select msr (msr 00000187h).
112 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.4 sysenter/sysexit code segment select or msr (sys_cs_msr) sys_cs_msr is used by the sysenter instruction (fast system call) as the selector of the most privileged code seg- ment. sys_cs plus 8 is used by sysente r as the selector of the most privil eged stack segment. sys_cs plus 16 is used by sysexit as the selector of the least privileged code segment. sys_cs plus 24 is used by sysexit as the selec- tor of the least privileged stack segment. msr address 00000174h ty p e r / w reset value 00000000_c09b0000h sys_cs_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 g d rsvd p dpl s x c r a cs_sel ti rpl sys_cs_msr bit descriptions bit name description 63:32 rsvd reserved. 31 g (ro) granularity (read only). code segment limit granular ity is 4 kb. (default = 1) 30 d (ro) default (read only). code segment default size is 32 bits. (default = 1) 29:24 rsvd (ro) reserved (read only). 23 p (ro) present (read only). code segment descriptor is present. (default = 1) 22:21 dpl (ro) descriptor privilege level (read only). code segment descriptor privilege level. (default = 11) 20 s (ro) segment (read only). code segment is not a syst em segment. (default = 1) 19 x (ro) executable (read only). code segment is executable. (default = 1) 18 c (ro) conforming (read only). code segment is conforming. (default = 0) 17 r (ro) readable (read only). code segment is readable. (default = 1) 16 a (ro) accessed (read only). code segment was accessed. (default = 1) 15:3 cs_sel code segment selector. (default = 0) 2ti descriptor table indicator. (default = 0) 1:0 rpl (ro) requestor privilege level (read only). (default = 0)
amd geode? lx processors data book 113 cpu core register descriptions 33234h 5.5.2.5 sysenter/sysexit stack pointer msr (sys_sp_msr) sys_sp msr is used by the sysenter instruction (fast system call) as the most privileged stack pointer. 5.5.2.6 sysenter/sysexit instruct ion pointer msr (sys_ip_msr) sys_ip msr is used by the sysenter instruction (fast system ca ll) as the offset into the most privileged code segment. msr address 00000175h ty p e r / w reset value 00000000_00000000h sys_sp_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 esp sys_sp_msr bit descriptions bit name description 63:32 rsvd reserved. 31:0 esp enter stack pointer. stack pointer to be used after sysenter in most privileged code. (default = 0) msr address 00000176h ty p e r / w reset value 00000000_00000000h sys_ip_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 eip sys_ip_msr bit descriptions bit name description 63:32 rsvd reserved. 31:0 eip enter instruction pointer. offset into the most privileged code segment. (default = 0)
114 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.7 performance event counte r 0 select msr (perf_sel0_msr 5.5.2.8 performance event counte r 1 select msr (perf_sel1_msr) msr address 00000186h ty p e r / w reset value 00000000_00000000h perf_sel0_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pc_en rsvd pc0_umask pc0_event perf_sel0_msr bit descriptions bit name description 63:23 rsvd reserved. write as read. 22 pc_en performance event coun ters 0 and 1 enable. 0: disable counters. 1: enable counters. 21:16 rsvd reserved. write as read. 15:8 pc0_umask performance event co unter 0 unit mask. selects sub-events. 00h: all sub-events counted. 7:0 pc0_event performance event counte r 0 event select value. see individual module chapters for performance event selections. msr address 00000187h ty p e r / w reset value 00000000_00000000h perf_sel1_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pc1_umask pc1_event perf_sel1_msr bit descriptions bit name description 63:16 rsvd reserved. write as read. 15:8 pc1_umask performance event co unter 1 unit mask. selects sub-events. 00h: all sub-events counted. 7:0 pc1_event performance event counte r 1 event select value. see individual module chapters for performance event selections.
amd geode? lx processors data book 115 cpu core register descriptions 33234h 5.5.2.9 instruction fetch configuration msr (if_config_msr) if_confg_msr controls the operation of the instruction fetch (if). the level-0 cof cache (change of flow (cof) cache), l1 cof cache, return stack, and power saving mode may be turned on or off. the wrmsr instruction can access if_config msr at any time. devices extern al to the cpu should issue writes to if_config msr only if the cpu is sus- pended or stalled. msr address 00001100h ty p e r / w reset value 00000000_00005051h if_config_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd betd bivd lsnpd psnpd rsvd bsp rsvd w_dis 313029282726252423222120191817161514131211109876543210 rsvd ii_ns rsvd cc_ser rsvd rq_ser rsvd ii_ser rsvd ii_imflsh rsvd cc_l0 rsvd dmm_dis rsvd cc_ps rsvd strong rsvd rs rsvd cc_invl rsvd cc_l1 if_config_msr bit descriptions bit name description 63:48 rsvd reserved. 47 betd branch tree messaging (btm) exception type. allow the btm stream to contain exception type records. 0: enable. (default) 1: disable. 46 bivd branch tree messaging interrupt vector. allow the btm stream to contain interrupt vector records. 0: enable. (default) 1: disable. 45 lsnpd linear snooping. 0: enable. (default) 1: disable. 44 psnpd physical snooping. 0: enable. (default) 1: disable. 43:41 rsvd reserved. 40:37 bsp branch tree messaging sync period. specifies the maximum period between btm synchronization records. if bsp is non-zero, the if will insert a synchronization record into the btm stream whenever it sees a series of 32*bsp non-synchronization records. (default = 0) 36 rsvd reserved. 35:32 w_dis branch target buffer (btb) way. each bit is used to disable one way of the btb. bit 32 = way 0, bit 33 = way 1, bit 34 = way 2, and bit 35 = way 3. 0: enable way. (default) 1: disable way. 31:29 rsvd reserved.
116 amd geode? lx processors data book cpu core register descriptions 33234h 28 ii_ns instruction pipeline (ip) empty mode. 0: im interface may make requests to instruct ion memory (im) when the ip is not empty. (default) 1: im interface only makes requests to im after the ip is empty. note: enabling this mode reduces performance. 27:25 rsvd reserved. 24 cc_ser cof cache serialization. 0: allow more than one outstanding request in cof cache. (default) 1: allow only one request in the cof cache. note: enabling cof cache serialization may reduce performance. 23:21 rsvd reserved. 20 rq_ser request queue serialization. 0: allow more than one request in the request queue. (default) 1: only one request is allowed in the request queue. note: enabling rq serialization reduces performance. 19:17 rsvd reserved. 16 ii_ser instruction memory request serialization. 0: im requests are not serialized. (default) 1: im interface waits until im responds to a request before im interface issues the next request. note: enabling im interface serialization reduces performance. 15 rsvd reserved. 14 ii_imflsh instruction memory flush. 0: if never issues flush requests to im. 1: if may issue flush requests to im. (default) note: enabling im flushing usually increases performance. 13 rsvd reserved. 12 cc_l0 level-0 cof cache. 0: disable. 1: enable. (default) note: enabling the l0 cof cache increases performance. unless cc_l1 is enabled (bit 0 = 1), then cc_l0 has no effect. 11 rsvd reserved. 10 dmm_dis debug management mode (dmm). 0: the cof cache and return stack is neither used nor updated during dmm. (default) 1: the cof cache and return stack may be used and updated during dmm. note: disabling the cof cache and return stack during dmm may reduce performance but make debug easier. 9 rsvd reserved. 8 cc_ps power saving mode. 0: disable. (default) 1: enable. note: cc_l1 must be disabled (bit 0 = 0) to enable power saving. 7 rsvd reserved. if_config_msr bit descriptions (continued) bit name description
amd geode? lx processors data book 117 cpu core register descriptions 33234h 6strong strong prediction. allow the if to make strong predictions. 0: disable. 1: enable. (default) note: enabling strong predictions may improve performance. 5 rsvd reserved. 4rs return stack. 0: disable. 1: enable. (default) note: enabling the return stack increases performance unless cc_l1 is enabled (bit 0 = 1), then the return stack has no effect. 3 rsvd reserved. 2 cc_invl cof cache invalidation. 0: translation look-aside buffer (tlb) invalidations do not invalidate the cof cache. (default) 1: whenever the tlb is invalidated, the cof cache is also invalidated. note: invalidating the cof cache whenever the tlb is invalidated may reduce perfor- mance. 1 rsvd reserved. 0 cc_l1 level-1 cof cache. 0: disable. 1: enable. (default) note: enabling the l1 cof cache increases performance. if_config_msr bit descriptions (continued) bit name description
118 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.10 if invalidate msr (if_invalidate_msr) if_invalidate msr may be used to inva lidate the contents of the tag rams (l evel-1 cof cache), level-0 cof cache, and the return stack. devices external to the cpu should issue writes to if_invalidate_msr only if the cpu is sus- pended or stalled. 5.5.2.11 if test addre ss msr (if_test_addr_msr) if_test_addr_msr is used to indirectly address the if state elements, while if_test_data_msr (msr 0000109h) is used to read/write the elements. the format of the data wr itten to, or read from if_test_data_msr depends on the value in if_test_addr msr. msr address 00001102h ty p e w reset value 00000000_00000000h if_invalidate_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd rs cc if_invalidate_msr bit descriptions bit name description 63:2 rsvd reserved. 1rs invalidate return stack. 0: do not alter the re turn stack. (default) 1: empty the return stack. 0cc invalidate l0 and l1 cof cache. 0: do not alter the cof cache. (default) 1: empty the cof cache. msr address 00001108h ty p e r / w reset value 00000000_00000000h if_test_addr_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd block index if_test_addr_msr bit descriptions bit name description 63:13 rsvd reserved.
amd geode? lx processors data book 119 cpu core register descriptions 33234h 5.5.2.12 if test data msr (if_test_data_msr) 12:8 block block identifier. 00h: target ram 0 (way 0). (default) 01h: target ram 1 (way 0). 02h: target ram 2 (way 0). 03h: target ram 3 (way 0). 04h: target ram 4 (way 1). 05h: target ram 5 (way 1). 06h: target ram 6 (way 1). 07h: target ram 7 (way 1). 08h: target ram 8 (way 2). 09h: target ram 9 (way 2). 0ah: target ram 10 (way 2). 0bh: target ram 11 (way 2). 0ch: target ram 12 (way 3). 0dh: target ram 13 (way 3). 0eh: target ram 14 (way 3). 0fh: target ram 15 (way 3). 10h: tag ram 0 (way 0). 11h: tag ram 1 (way 1). 12h: tag ram 2 (way 2). 13h: tag ram 3 (way 3). 14h: l0 cof cache. 15h: return stack. 7:0 index block index. (default = 00h) when accessing a tag ram or a target ram, the index is the address of the ram loca- tion (0-255). when accessing the l0 cof cache, indexes 0-1 refer to the 2 tag entries, 4-5 refer to the 2 source addresses, 8-9 refer to the 2 target addresses, and 12-13 refer to the 2 return addresses. when accessing the return stack, indexes 0-7 refer to the 8 non-speculative return addresses, indexes 8-15 refer to the if speculative return addresses, and address 16 refers to the valid bits, indexes 17-24 refer to the id speculative return addresses. msr address 00001109h ty p e r / w reset value 00000000_xxxxxxxxh if_test_addr_msr bit descriptions (continued) bit name description if_test_data_msr register map for target rams 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 tgt if_test_data_msr bit descriptions for target rams bit name description 63:32 rsvd reserved. 31:0 tgt cof target.
120 amd geode? lx processors data book cpu core register descriptions 33234h if_test_data_msr register map for tag rams 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 v lip rsvd strength type end if_test_data_msr bit descriptions for tag rams bit name description 63:32 rsvd reserved. 31 v tag is valid. (default = 0) 30:22 lip linear address bits [19:11]. 21:20 rsvd reserved. 19:16 strength prediction strength. bit 19 = strength3, bit 18 = strength2, bit 17 = strength1, and bit 16 = strength0. 0: weakly predicted. 1: strongly predicted. 15:8 type cof type. bits [15:14] = type3, bits [13:12] = type2, bits [11:10] = type1, and bits [9:8] = type0. 7:0 end predicted taken cof end markers. if_test_data_msr register map for level-0 cof cache tag 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pntkn rsvd vld len rsvd ptkn rsvd type rsvd lru if_test_data_msr bit descriptions for level-0 cof cache tag bit name description 63:21 rsvd reserved. 20 pntkn predicted not taken. entry ends with a predicted not-taken change of flow. 19:17 rsvd reserved. 16 vld valid. if an entry is valid, then all the tag information as well as the entry?s address and target must also be valid. (default = 0) 15:12 len number of bytes. number of bytes from address to either end of qword or end of pre- dicted taken change of flow (0-8). 11:9 rsvd reserved. 8 ptken predicted taken. entry ends with a predicted taken change of flow. 7:6 rsvd reserved. 5:4 type change of flow type. 3:1 rsvd reserved. 0lru next entry. indicates that entry is the next entry to be written. exactly one of the four entries should have this bit set.
amd geode? lx processors data book 121 cpu core register descriptions 33234h if_test_data_msr register map for level-0 cof cache address 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 addr[31:0] if_test_data_msr bit descriptions for level-0 cof cache address bit name description 63:32 rsvd reserved. 31:0 addr[31:0] address bits [31:0]. linear address for which the entry contains data. if_test_data_msr register map for level-0 cof cache target 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 target[31:0] if_test_data_msr bit descriptions for level-0 cof cache target bit name description 63:32 rsvd reserved. 31:0 target[31:0] target bits [31:0]. if an entry is valid and contains a predicted taken change of flow, then this is the predicted target for the change of flow. if_test_data_msr register map for return stack addresses 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 addr[31:0] if_test_data_msr bit descriptions for return stack addresses bit name description 63:32 rsvd reserved. 31:0 addr[31:0] address bits [31:0]. linear address to which a return instruction should return.
122 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.13 if sequential co unt mrs (if_seqcount_msr) if seqcount msr is a read only msr cont aining the number of sequential instruct ions executed since the last change of flow. this is useful when the cpu is halted, since it helps de termine the instructions executed since the last record of the btm stream. if_test_data_msr register map for return stack valids 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd id_spec_vld if_spec_vld[7:0] nonspec_vld[7:0] if_test_data_msr bit descriptions for return stack valids bit name description 63:24 rsvd reserved. 23:16 id_spec_vld valid instruction decode speculative. id speculative return stack entries that are valid. the lease significant entry is the next to be popped from the stack. (default = 0) 15:8 if_spec_vld valid instruction fetch speculative. if speculative return stac k entries that are valid. the least significant entry is the next to be popped from the stack. (default = 0) 7:0 nonspec_vld valid non-speculative. non-speculative return stack entries that are valid. the least significant entry the next to be popped from the stack. (default = 0) msr address 00001110h ty p e r o reset value 00000000_00000000h if_seqcount_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd seqcount if_seqcount_msr bit descriptions bit name description 63:5 rsvd reserved. 4:0 seqcount sequential count . number of sequential instructions executed since the last change of flow.
amd geode? lx processors data book 123 cpu core register descriptions 33234h 5.5.2.14 if built-in sel f-test msr (if_bist_msr) if_bist_msr may be used to run built-in self-test (bist) on the if tag and ta rget rams, and to get an indication of whether the bist run passed or failed. there are separate bi st controllers for the tag ram and for the target rams. a msr read of if_bist_msr causes bist to be run. if_bist_msr can only be run when the level-1 cof cache, the level-0 cof cache, and the return stack is disabled in the if_config msr. if the cof cache is enabled, reading if_bis t_msr does not cause bist to be run, and returns zero. after bist has been run by reading if_bist_msr, the co ntents of the if tag rams is invalidated (cleared). msr address 00001140h ty p e r o reset value 00000000_00000000h if_bist_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd tgt_pass tag_pass if_bist_msr bit descriptions bit name description 63:2 rsvd reserved. 1tgt_pass target ram bist status. 0: target ram bist did not pass. (default) 1: target ram bist passed. 0tag_pass tag ram bist status. 0: tag ram bist did not pass. (default) 1: tar ram bist passed.
124 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.15 exception unit (xc) co nfiguration msr (xc_config_msr) xc_config_msr allows the processor to be configured so that when the processor is in it s halt state, it can request that its clocks be turned off. it also allows the processor to be configured so that the processor is suspended when a pause instruction is executed. msr address 00001210h ty p e r / w reset value 00000000_00000000h xc_config_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd susponpause susponhlt xc_config_msr bit descriptions bit name description 63:2 rsvd reserved. 1 susponpause suspend on pause. when set, if a pause instruction is executed, the processor is sus- pended for the number of clocks specified in the pausedly field of bc_config0_msr (msr 00001900h[27:24]). (default = 0) 0 susponhlt suspend on halt. when set, if the processor is halte d, then it requests that its clocks be turned off. (default = 0)
amd geode? lx processors data book 125 cpu core register descriptions 33234h 5.5.2.16 xc mode msr (xc_mode_msr) xc_mode_msr contains information about the current status of the processor. msr address 00001211h ty p e r / w reset value 00000000_00000000h xc_mode_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dm_ac_stall fp_stall fp_error fp_busy ip_busy dm_busy if_busy dm_ex_delay iq_empty wait_fpintr flushing halted suspended nmi_active dmm_active smm_active xc_mode_msr bit descriptions bit name description 63:16 rsvd (ro) reserved (read only). 15 dm_ac_stall (ro) data memory subsystem stall addr ess calculation unit (read only). dm wants no more requests from ac. 14 fp_stall (ro) floating point stall (read only). fp is stalling the pipeline. 13 fp_error (ro) floating point error (read only). fp is reporting an error. 12 fp_busy (ro) floating point busy (read only). fp is reporting that it is not idle. 11 ip_busy (ro) instruction pipeline busy (read only). ip is reporting that it is not idle. 10 dm_busy (ro) data memory subsystem busy (read only). dm is reporting that it is not idle. 9 if_busy (ro) instruction fetch busy (ready only). if is reporting that it is not idle. 8 dm_ex_delay (ro) data memory subsystem execution delay (read only). pipeline is waiting for dm to provide instruction data. 7 iq_empty (ro) instruction queue empty (read only). instruction queue is empty. 6 wait_fpintr (ro) wait for floating poin t interrupt (read only). processor is waiting for an external maskable interrupt due to a fp error (cr0 ne bit is set, see table 5-10 "cr0 bit descriptions" on page 96). (default = 0) 5 flushing (ro) flushing (read only). processor is flushing the pipeline while waiting for dm to empty. 4halted (ro) halted (read only). processor is halted. (default = 0) 3 suspended (ro) suspended (read only). processor is suspended. (default = 0) 2nmi_active non-maskable interrupt active. processor is in a nmi handler. (default = 0) 1 dmm_active debug management mode. processor is in debug management mode. (default = 0) 0smm_active system management mode. processor is in system management mode. (default = 0)
126 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.17 xc history msr (xc_hist_msr) msr address 00001212h ty p e r o reset value 00000000_00000000h xc_hist_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd type11 type10 type9 type8 type7 type6 313029282726252423222120191817161514131211109876543210 rsvd type5 type4 type3 type2 type1 type0 xc_hist_msr bit descriptions bit name description (note 1) 63:62 rsvd reserved. 61:57 type11 exception type 11. 56:52 type10 exception type 10. 51:47 type9 exception type 9. 46:42 type8 exception type 8. 41:37 type7 exception type 7. 36:32 type6 exception type 6. 31:30 rsvd reserved. 29:25 type5 exception type 5. 24:20 type4 exception type 4. 19:15 type3 exception type 3. 14:10 type2 exception type 2. 9:5 type1 exception type 1. 4:0 type0 exception type 0. note 1. table 5-14 shows the definitio n of the types in the xc_hist msr. table 5-14. xc_hist_msr exception types value description value description value description 00h divide error 0bh segment not present 16h external system management during i/o instruction 01h debug 0ch stack fault 17h external system management 02h external non-maskable interrupt 0dh general protection fault 18h init 03h breakpoint 0eh page fault 19h reset 04h overflow 0fh reserved 1ah internal suspend/stall 05h bound 10h fpu error trap 1bh external suspend/stall 06h invalid operation code 11h alignment fault 1ch unsuspend/unstall 07h fpu unavailable 12h fpu error interrupt 1dh triple fault shutdown 08h double fault 13h internal debug management 1eh external maskable interrupt 09h self-modified code fault 14h external debug management 1fh no exception 0ah invalid task-state segment 15h i/o-initiated system management -- --
amd geode? lx processors data book 127 cpu core register descriptions 33234h 5.5.2.18 xc microcode address msr (xc_uaddr_msr) 5.5.2.19 id configuratio n msr (id_config_msr) msr address 00001213h ty p e r o reset value 00000000_00000000h xc_uaddr_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd uaddr4 uaddr3 uaddr2[11:8] 313029282726252423222120191817161514131211109876543210 uaddr2[7:0] uaddr1 uaddr0 xc_uaddr_msr bit descriptions bit name description 63:60 rsvd reserved. 59:48 uaddr4 microcode address for exception 4. 47:36 uaddr3 microcode address for exception 3. 35:24 uaddr2 microcode address for exception 2. 23:12 uaddr1 microcode address for exception 1. 11:0 uaddr0 microcode address for exception 0. most recent exception. msr address 00001250h ty p e r / w reset value 00000000_00000002h id_config_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd gpf_tr inv_3dnow serial id_config_msr bit descriptions bit name description 63:3 rsvd (ro) reserved (read only). 2gpf_tr general protection faults on test register accesses. generate general protection faults on accesses to test registers. 0: disable. (default) 1: enable. 1 inv_3dnow inverse 3dnow!?. inverse amd 3dnow!? instructions pfrcpv and rfrsqrtv. 0: disable. 1: enable. (default) 0 serial serialize. serialize the cpu integer pipeline by only allowing one instruction in the pipe- line at a time. 0: integer pipeline is not serialized. (default) 1: integer pipeline is serialized.
128 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.20 smm contro l msr (smm_ctl_msr) msr address 00001301h ty p e r / w reset value 00000000_00000000h smm_ctl_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd smi_extl smi_io smi_inst smm_nest smm_susp smm_nmi smm_ctl_msr bit descriptions bit name description 63:6 rsvd (ro) reserved (read only). 5 smi_extl enable external asmi pin. enable external asynchronous smis. 0: disable. 1: enable. 4smi_io enable i/o generated smi. enable smis caused by an i/o instruction. 0: disable. 1: enable. 3smi_inst enable smi instructions. enable smi instructions: smint, rsm, svdc, rsdc, svldt, rsldt, svts, rsts. if not enabled, executing an smi instruction causes an invalid operation fault. 0: disable. 1: enable. 2 smm_nest enable smi nesting. enable non-software smis during smm mode. 0: disable. 1: enable. 1smm_susp enable suspend during smm. enable suspend during smm mode. 0: disable. 1: enable. 0 smm_nmi enable non-maskable in terrupts during smm. enable nmi during smm mode. 0: disable. 1: enable.
amd geode? lx processors data book 129 cpu core register descriptions 33234h 5.5.2.21 debug management inte rrupt (dmi) control register msr address 00001302h ty p e r / w reset value 00000000_00000000h dmi control register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dmi_tf dmi_stall dmm_susp dmi_tss dmm_cache dmi_icebp dmi_dbg dmi_ext dmi_gpf dmi_inst dmi control register bit descriptions bit name description 63:10 rsvd reserved. write as read. 9dmi_tf dmi trap flag. 0: disable dmi single stepping. 1: if dmi_stall (bit 8) is 0, dmi occurs af ter the successful execut ion of each instruc- tion. if dmi_stall is 1, debug stall occu rs after the successful execution of each instruction. 8dmi_stall dmi stall. 0: if not in dmm, dmi conditions cause dmis. 1: dmi conditions cause a debug stall. 7 dmm_susp enable susp# during dmm. enable susp# during dmm mode. 0: disable. 1: enable. 6dmi_tss task switch debug fault control. 0: task switch debug faults cause debug exceptions. 1: task switch debug exceptions cause dmis when not in dmm. 5 dmm_cache cache control during dmm. 0: do not change cr0 cd and nw bits when entering dmm. 1: set cr0, cd and nw bits when entering dmm . see table 5-10 "cr0 bit descriptions" on page 96 for cd and nw bit descriptions. 4 dmi_icebp enable dmis on icebp (f1) instructions. 0: disable. 1: enable. 3dmi_dbg enable replacing debug exceptions as dmis. 0: disable. 1: enable. 2 dmi_ext enable external tdbgi pin. enable dmis caused by the tdbgi pin (ball ab2) when not in dmm. 0: disable. 1: enable.
130 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.22 temporary msrs temporary 0 msr (temp0_msr) temporary 1 msr (temp1_msr) temporary 2 msr (temp2_msr) temporary 3 msr (temp3_msr) 1dmi_gpf dmi general protection faults. when enabled and not in dmm mode, allow general protection faults to generate dmis. 0: disable. 1: enable. 0dmi_inst dmi instructions. enable dmi instructions dmint and rdm. if not enabled, executing a dmi instruction generates an invalid operation fault. 0: disable. 1: enable. dmi control register bit descriptions (continued) bit name description msr address 00001310h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001311h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001312h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001313h ty p e r / w reset value xxxxxxxx_xxxxxxxxh tempx_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 tempx tempx_msr bit descriptions bit name description 63:32 rsvd reserved. write as read. 31:0 tempx temporary x. used by microcode, usually for holding operands for address calculations.
amd geode? lx processors data book 131 cpu core register descriptions 33234h 5.5.2.23 segment selector/flags msrs the segment selector/flags msrs provide access to the segment selector and segment flags parts of a segment register. the contents of segment registers should be accessed using mov or svdc/rsdc. es segment selector /flags register (es_sel_msr) cs segment selector/flags register (cs_sel_msr) ss segment selector /flags register (ss_sel_msr) ds segment selector/flags register (ds_sel_msr) fs segment selector/flags register (fs_sel_msr) gs segment selector/flags register (gs_sel_msr) ldt segment selector/flags register (ldt_sel_msr) temp segment selector/flags register (tm_sel_msr) tss segment selector/flags register (tss_sel_msr) idt segment selector/flags register (idt_sel_msr) gdt segment selector/flags register (gdt_sel_msr) msr address 00001320h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001321h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001322h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001323h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001324h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001325h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001326h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001327h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001328h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001329h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 0000132ah ty p e r / w reset value xxxxxxxx_xxxxxxxxh segment selector/flags msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 g b/d rsvd avl rsvd p dpl s x e/c w/r a selector ti rpl segment selector/flags msr bit descriptions bit name description 63:32 rsvd reserved. 31 g limit granularity bit. 30 b/d stack address size / code default size. 29 rsvd reserved. 28 avl available. bit available for operating system use. 27:24 rsvd reserved. 23 p present. 22:21 dpl descriptor privilege level. 20 s non-system descriptor.
132 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.24 smm header msr (smm_hdr_msr) the smm_hdr_msr provides access to the address r egister that controls w here smi data is written. 19 x executable non-system segment. 18 e/c expand down data segment / conforming code segment. 17 w/r writable data segment / readable code segment. 16 a accessed segment. 15:3 selector segment selector. 2ti descriptor table indicator (ldt/gdt). 1:0 rpl requestor privilege level. msr address 0000132bh ty p e r / w reset value 00000000_00000000h smm_hdr_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 smm_hdr segment selector/flags msr bit descriptions (continued) bit name description smm_hdr_msr bit descriptions bit name description 63:32 rsvd reserved. write as read. 31:0 smm_hdr smm header. address that indicates where smi data is written. smi data is written at lower addresses than smm_hdr (negative offsets).
amd geode? lx processors data book 133 cpu core register descriptions 33234h 5.5.2.25 dmm header msr (dmm_hdr_msr) dmm_hdr_msr provides access to the address regist er that controls where dmi data is written. msr address 0000132ch ty p e r / w reset value 00000000_00000000h dmm_hdr_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 dmm_hdr dmm_hdr_msr bit descriptions bit name description 63:32 rsvd reserved. write as read. 31:0 dmm_hdr dmm header. address that indicates w here dmi data is written. dmi data is written at lower addresses than dmm_hdr (negative offsets).
134 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.26 segment base/limit msrs the segment base/limit msrs provide access to the segment limit and segment base parts of a segment register. the limit value is the true limit; it does not need to be altered based on the limit granularity bit. t he contents of segment registers should be accessed using mov or svdc/rsdc. es segment base/limit msr (es_base_msr) cs segment base/limit msr (cs_base_msr) ss segment base/limit msr (ss_base_msr) ds segment base/limit msr (ds_base_msr) fs segment base/limit msr (fs_base_msr) gs segment base/limit msr (gs_base_msr) ldt segment base/limit msr (ldt_base_msr) temp segment base/limit msr (temp_base_msr) tss segment base/limit msr (tss_base_msr) idt segment base/limi t msr (idt_base_msr) gdt segment base/limit msr (gdt_base_msr) smm segment base/limit msr (smm_base_msr dmm segment base/ limit msr (dmm_base_msr) msr address 00001330h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001331h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001332h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001333h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001334h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001335h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001336h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001337h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001338h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001339h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 0000133ah ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 0000133bh ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 0000133ch ty p e r / w reset value xxxxxxxx_xxxxxxxxh segment base/limit msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 limit 313029282726252423222120191817161514131211109876543210 base segment base/limit msr bit descriptions bit name description 63:32 limit segment limit. 31:0 base segment base.
amd geode? lx processors data book 135 cpu core register descriptions 33234h 5.5.2.27 debug registers 1 and 0 msr (dr1_dr0_msr) dr1_dr0_msr provides access to debug register 1 (dr1 ) and debug register 0 (dr0). dr0 and dr1 each contain either an i/o port number or a linear address for use as a br eakpoint. the contents of debug registers are more easily accessed using the mov instruction. 5.5.2.28 debug registers 3 and 2 msr (dr3_dr2_msr) dr3/dr2_msr provides access to debug register 3 (dr3 ) and debug register 2 (dr2). dr2 and dr3 each contain either an i/o port number or a linear address for use as a br eakpoint. the contents of debug registers are more easily accessed using the mov instruction. msr address 00001340h ty p e r / w reset value xxxxxxxx_xxxxxxxxh dr1_dr0_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dr1 313029282726252423222120191817161514131211109876543210 dr0 dr1_dr0_msr bit descriptions bit name description 63:32 dr1 breakpoint 1 i/o port number/linear address. 31:0 dr0 breakpoint 0 i/o port number/linear address. msr address 00001341h ty p e r / w reset value xxxxxxxx_xxxxxxxxh dr3_dr2_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dr3 313029282726252423222120191817161514131211109876543210 dr2 dr2_dr3_msr bit descriptions bit name description 63:32 dr3 breakpoint 3 i/o port number/linear address. 31:0 dr2 breakpoint 2 i/o port number/linear address.
136 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.29 debug registers 7 and 6 msr (dr6_dr7_msr) dr7_dr6_msr provides access to debug register 7 (dr7) and debug register 6 (dr6). dr6 contains status information about debug conditions that have occu rred. dr7 contains debug condition enables, types, and lengths. the contents of debug registers are more easily ac cessed using the mov instruction. msr address 00001343h ty p e r / w reset value 00000000_ffff0000h dr7_dr6_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 len3 type3 len2 type2 len1 type1 len0 type0 rsvd gd rsvd g3 l3 g2 l2 g1 l1 g0 l0 313029282726252423222120191817161514131211109876543210 rsvd (ffffh) bt bs bd rsvd (ffh) b3 b2 b1 b0 dr7_dr6_msr bit descriptions bit name description 63:62 len3 breakpoint 3 length. 61:60 type3 breakpoint 3 type. 59:58 len2 breakpoint 2 length. 57:56 type2 breakpoint 2 type. 55:54 len1 breakpoint 1 length. 53:52 type1 breakpoint 1 type. 51:50 len0 breakpoint 0 length. 49:48 type0 breakpoint 0 type. 47:46 rsvd reserved. 45 gd enable global detect faults. 44:40 rsvd reserved. 39, 38 g3, l3 breakpoint 3 enables. 37, 36 g2, l2 breakpoint 2 enables. 35, 34 g1, l1 breakpoint 1 enables. 33, 32 g0, l0 breakpoint 0 enables. 31:16 rsvd reserved. 15 bt tss t-bit trap occured. 14 bs single-step trap occured. 13 bd global detect fault occured. 12:4 rsvd reserved. 3b3 breakpoint 3 matched. 2b2 breakpoint 2 matched. 1b1 breakpoint 1 matched. 0b0 breakpoint 0 matched.
amd geode? lx processors data book 137 cpu core register descriptions 33234h 5.5.2.30 extended debug registers 1 and 0 msr (xdr1_xdr0_msr) xdr1/xdr0_msr provides access to extended debug regist er 1 (xdr1) and extended debug register 0 (xdr0). xdr0 and xdr1 each contain either an i/o port number or a linear address for use as an extended breakpoint. 5.5.2.31 extended debug registers 3 and 2 msr (xdr3_xdr2_msr) xdr3/xdr2_msr provides access to extended debug regist er 3 (xdr3) and extended debug register 2 (xdr2). xdr2 and xdr3 each contain either an i/o port number or a linear address for use as an extended breakpoint. msr address 00001350h ty p e r / w reset value 00000000_00000000h xdr1_xdr0_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 xdr1 313029282726252423222120191817161514131211109876543210 xdr0 xdr1_xdr0_msr bit descriptions bit name description 63:32 xdr1 extended breakpoint 1 i/o port number/linear address. 31:0 xdr0 extended breakpoint 0 i/o port number/linear address. msr address 00001351h ty p e r / w reset value 00000000_00000000h xdr3_xdr2_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 xdr3 313029282726252423222120191817161514131211109876543210 xdr2 xdr3_xdr2_msr bit descriptions bit name description 63:32 xdr3 extended breakpoint 3 i/o port number/linear address. 31:0 xdr2 extended breakpoint 2 i/o port number/linear address.
138 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.32 extended debug registers 5 and 4 msr (xdr5_xdr4_msr) xdr5/xdr4_msr provides access to extended debug regist er 5 (xdr5) and extended debug register 4 (xdr4). xdr4 contains an opcode match value. xdr5 contains an opcode match mask. 5.5.2.33 extended debug registers 7 and 6 msr (xdr7_xdr6_msr) xdr7_xdr6_msr provides access to the extended brea kpoint enables, types, lengths, and status. msr address 00001352h ty p e r / w reset value ffffffff_00000000h xdr5_xdr4_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 prefix_mask4 opcode_mask4 313029282726252423222120191817161514131211109876543210 prefix_value4 opcode_value4 pn pr pl pc ps po pa pf xdr5_xdr4_msr bit descriptions bit name description 63:56 prefix_mask4 prefix mask value for extended breakpoint 4. 55:32 opcode_mask4 opcode mask value for extended breakpoint 4. 31 pn repne/repnz prefix value for extended breakpoint 4. 30 pr rep/repe/repz prefix value for extended breakpoint 4. 29 pl lock prefix value for extended breakpoint 4. 28 pc cs segment override prefix value for extended breakpoint 4. 27 ps ss/ds/es/fs/gs segment override pref ix value for extended breakpoint 4. 26 po operand size prefix value for extended breakpoint 4. 25 pa address size prefix value for extended breakpoint 4. 24 pf 0f or 0f 0f prefix valu e for extended breakpoint 4. 23:0 opcode_value4 opcode match value for extended breakpoint 4. msr address 00001353h ty p e r / w reset value xxxxxxxx_xxxxxxxxh xdr7_xdr6_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 len3 type3 len2 type2 len1 type1 len0 type0 rsvd e6 e5 e4 e3 e2 e1 e0 313029282726252423222120191817161514131211109876543210 rsvd (1ffffh) bs rsvd (1) bi rsvd (1fh) b6b5b5b3b2b1b0
amd geode? lx processors data book 139 cpu core register descriptions 33234h xdr7_xdr6_msr bit descriptions bit name description 63:62 len3 extended breakpoint 3 length. 61:60 type3 extended breakpoint 3 type. 59:58 len2 extended breakpoint 2 length. 57:56 type2 extended breakpoint 2 type. 55:54 len1 extended breakpoint 1 length. 53:52 type1 extended breakpoint 1 type. 51:50 len0 breakpoint 0 length. 49:48 type0 breakpoint 0 type. 47:39 rsvd reserved. 38 e6 extended breakpoint 6 enable. 37 e5 extended breakpoint 5 enable. 36 e4 extended breakpoint 4 enable. 35 e3 extended breakpoint 3 enable. 34 e2 extended breakpoint 2 enable. 33 e1 extended breakpoint 1 enable. 32 e0 extended breakpoint 0 enable. 31:15 rsvd reserved. default = 1ffffh. 14 bs extended si ngle-step trap status. 13 rsvd reserved. default = 1. 12 bi icebp or int_1 status. 11:7 rsvd reserved. default = 1fh. 6b6 extended breakpoint 6 status. 5b5 extended breakpoint 5 status. 4b4 extended breakpoint 4 status. 3b3 extended breakpoint 3 status. 2b2 extended breakpoint 2 status. 1b1 extended breakpoint 1 status. 0b0 extended breakpoint 0 status.
140 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.34 extended debug registers 9 and 8 msr (xdr9_xdr8_msr) xdr9_xdr8_msr provides access to extended debug re gister 9 (xdr9) and extended debug register 8 (xdr8). xdr8 contains an opcode match value. xdr9 contains an opcode match mask. msr address 00001354h ty p e r / w reset value ffffffff_00000000h xdr9_xdr8_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 prefix_mask5 opcode_mask5 313029282726252423222120191817161514131211109876543210 prefix_value5 opcode_value5 pn pr pl pc ps po pa pf xdr9_xdr8_msr bit descriptions bit name description 63:56 prefix_mask5 prefix mask value for extended breakpoint 5. 55:32 opcode_mask5 opcode mask value for extended breakpoint 5. 31 pn repne/repnz prefix value for extended breakpoint 5. 30 pr rep/repe/repz prefix value for extended breakpoint 5. 29 pl lock prefix value for extended breakpoint 5. 28 pc cs segment override prefix value for extended breakpoint 5. 27 ps ss/ds/es/fs/gs segment override pref ix value for extended breakpoint 5. 26 po operand size prefix value for extended breakpoint 5. 25 pa address size prefix value for extended breakpoint 5. 24 pf 0f or 0f 0f prefix valu e for extended breakpoint 5. 23:0 opcode_value5 opcode match value for extended breakpoint 5.
amd geode? lx processors data book 141 cpu core register descriptions 33234h 5.5.2.35 extended debug registers 11 and 10 msr (xdr11_xdr10_msr) xdr11_xdr10_msr provides access to the extended i/o breakpoint. 5.5.2.36 ex stage instruction pointer msr (ex_ip_msr) ex_ip_msr provides access to the ex stage instruction pointer (effective address). msr address 00001355h ty p e r / w reset value xxxxxxxx_xxxx0000h xdr11_xdr10_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd io_port xdr11_xdr10_msr bit descriptions bit name description 63:16 rsvd reserved. these bits are not writable. 15:0 io_port i/o port for extended i/o breakpoint 6. msr address 00001360h ty p e r / w reset value 00000000_00000000h ex_ip_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 ex_ip ex_ip_msr bit descriptions bit name description 63:32 rsvd reserved. 31:0 ex_ip ex stage effective instruction pointer.
142 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.37 wb stage instructio n pointer msr (wb_ip_msr) wb_ip_msr provides access to the wb stag e instruction pointer (effective address). 5.5.2.38 ex stage linear instruct ion pointer msr (ex_lip_msr) ex_lip_msr provides access to the ex stage linear instruction pointer. msr address 00001361h ty p e r / w reset value 00000000_00000000h wb_ip_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 wb_ip wb_ip_msr bit descriptions bit name description 63:32 rsvd reserved. 31:0 wb_ip wb stage effective instruction pointer. msr address 00001364h ty p e r o reset value 00000000_00000000h ex_lip_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 ex_lip ex_lip_msr bit descriptions bit name description 63:32 rsvd reserved. 31:0 ex_lip ex stage linear instruction pointer.
amd geode? lx processors data book 143 cpu core register descriptions 33234h 5.5.2.39 wb stage line ar instruction pointer msr (wb_lip_msr) wb_lip_msr provides access to the wb stage linear instruction pointer. 5.5.2.40 c1/c0 linear instructio n pointer msr (c1_c0_lip_msr) c1_c0_lip_msr provides access to linear instruct ion pointers when the code segment was loaded. msr address 00001365h ty p e r o reset value 00000000_00000000h wb_lip_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 wb_lip wb_lip_msr bit descriptions bit name description 63:32 rsvd reserved. 31:0 wb_lip wb stage linear instruction pointer. msr address 00001366h ty p e r o reset value 00000000_00000000h c1_c0_lip_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 c1_lip 313029282726252423222120191817161514131211109876543210 c0_lip c1_c0_lip_msr bit descriptions bit name description 63:32 c1_lip cs 1 linear instruction pointer. second most recent linear instruction point when code segment was loaded. 31:0 c0_lip cs 0 linear instruction pointer. most recent linear instruction point when code seg- ment was loaded.
144 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.41 c3/c2 linear instructio n pointer msr (c3_c2_lip_msr) c3_c2_lip_msr provides access to linear instruct ion pointers when the code segment was loaded. 5.5.2.42 floating point environm ent code segmen t (fpenv_cs_msr) fpenv_cs_msr provides access to the floating point (fp) environment code segment. software better accesses the floating point environment data using the flde nv/fstenv and fsave/frstor instructions. msr address 00001367h ty p e r o reset value 00000000_00000000h c3_c2_lip_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 c3_lip 313029282726252423222120191817161514131211109876543210 c2_lip c3_c2_lip_msr bit descriptions bit name description 63:32 c3_lip cs 3 linear instruction pointer. fourth most recent linear instruction point when code segment was loaded. 31:0 c2_lip cs 2 linear instruction pointer. third most recent linear instruction point when code segment was loaded. msr address 00001370h ty p e r / w reset value 00000000_00000000h fpenv_cs_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd cs fpenv_cs_msr bit descriptions bit name description 63:16 rsvd reserved. 15:0 cs code segment. selector of code segment of last fp instruction that may have caused an fp error.
amd geode? lx processors data book 145 cpu core register descriptions 33234h 5.5.2.43 floating point environment instruction pointer (fpenv_ip_msr) fpenv_ip_msr provides access to the floating point (fp) envi ronment instruction pointer. software better accesses the floating point environment data using the flde nv/fstenv and fsave/frstor instructions. 5.5.2.44 floating point environm ent data segment (fpenv_ds_msr) fpenv_ds_msr provides access to the floating point (fp) envi ronment data segment. software better accesses the float- ing point environment data using the flde nv/fstenv and fsave/frstor instructions. msr address 00001371h ty p e r / w reset value 00000000_00000000h fpenv_ip_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 ip fpenv_ip_msr bit descriptions bit name description 63:32 rsvd reserved. 31:0 ip instruction pointer. effective address of last fp instru ction that may have caused an fp error. msr address 00001372h ty p e r / w reset value 00000000_00000000h fpenv_ds_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd ds fpenv_ds_msr bit descriptions bit name description 63:16 rsvd reserved. 15:0 ds data segment. selector of data segment of memory operand of last fp instruction that may have caused an fp error.
146 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.45 floating point environm ent data pointer (fpenv_dp_msr) fpenv_dp_msr provides access to the floating point (fp) environment data pointer. software better accesses the float- ing point environment data using the flde nv/fstenv and fsave/frstor instructions. 5.5.2.46 floating point environmen t opcode pointer (fpenv_op_msr) fpenv_op_msr provides access to the floating point (fp) environment opcode. software better accesses the floating point environment opcode using the fldenv /fstenv and frstor/fsave instructions. msr address 00001373h ty p e r / w reset value 00000000_00000000h fpenv_dp_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 dp fpenv_dp_msr bit descriptions bit name description 63:32 rsvd reserved. 31:0 dp data pointer. effective address of memory operand of last fp instruction that may have caused an fp error. msr address 00001374h ty p e r / w reset value 00000000_00000000h fpenv_op_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd op fpenv_op_msr bit descriptions bit name description 63:11 rsvd reserved. 10:0 op opcode pointer. opcode of last fp instruction exec uted that may have caused an fp error.
amd geode? lx processors data book 147 cpu core register descriptions 33234h 5.5.2.47 address calculation unit configuration msr (ac_config_msr) msr address 00001380h ty p e r o reset value 00000000_00000000h ac_config_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd lock_en ac_config_msr bit descriptions bit name description 63:1 rsvd reserved. 0 lock_en lock enable. allow address calculation unit (ac) to issue locked requests to data memory subsystem (dm).
148 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.48 general register msrs general register ea x msr (gr_eax_msr) general register ec x msr (gr_ecx_msr) general register ed x msr (gr_edx_msr) general register eb x msr (gr_ebx_msr) general register esp msr (gr_esp_msr) general register eb p msr (gr_ebp_msr) general register esi msr (gr_esi_msr) general register edi msr (gr_edi_msr) general register temp 0 msr (gr_temp0_msr) general register temp 1 msr (gr_temp1_msr) general register temp 2 msr (gr_temp2_msr) general register temp 3 msr (gr_temp3_msr) general register temp 4 msr (gr_temp4_msr) general register temp 5 msr (gr_temp5_msr) general register temp 6 msr (gr_temp6_msr) general register temp 7 msr (gr_temp7_msr) msr address 00001408h ty p e r / w reset value 00000000_00000000h msr address 00001409h ty p e r / w reset value 00000000_00000000h msr address 0000140ah ty p e r / w reset value 00000000_00000000h msr address 0000140bh ty p e r / w reset value 00000000_00000000h msr address 0000140ch ty p e r / w reset value 00000000_00000000h msr address 0000140dh ty p e r / w reset value 00000000_00000000h msr address 0000140eh ty p e r / w reset value 00000000_00000000h msr address 0000140fh ty p e r / w reset value 00000000_00000000h msr address 00001410h ty p e r / w reset value 00000000_00000000h msr address 00001411h ty p e r / w reset value 00000000_00000000h msr address 00001412h ty p e r / w reset value 00000000_00000000h msr address 00001413h ty p e r / w reset value 00000000_00000000h msr address 00001414h ty p e r / w reset value 00000000_00000000h msr address 00001415h ty p e r / w reset value 00000000_00000000h msr address 00001416h ty p e r / w reset value 00000000_00000000h msr address 00001417h ty p e r / w reset value 00000000_00000000h general registers msrs register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 gr_reg general registers msrs bit descriptions bit name description 63:32 rsvd reserved. write as read. 31:0 gr_reg general register.
amd geode? lx processors data book 149 cpu core register descriptions 33234h 5.5.2.49 extended flags msr (eflag_msr) 5.5.2.50 control register 0 msr (cr0_msr) this is the standard x86 control register 0 (cr0). cr1 , cr2, cr3, and cr4 are located at msrs 00001881h-00001884h (see section 5.5.2.74 on page 172). the co ntents of cr0-cr4 should only be acce ssed using the mov instruction. they are mentioned here for completeness only. see section 5.4.1 ?control registers? on page 95 for bit descriptions. msr address 00001418h ty p e r / w reset value 00000000_00000002h eflag_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd (0) id rsvd (0) ac vm rf rsvd (0) nt iopl of df if tf sf zf rsvd (0) af rsvd (0) pf rsvd (1) cf eflag_msr bit descriptions bit name description 63:22 rsvd reserved. (default = 0) 21 id identification flag. (default = 0) 20:19 rsvd reserved. (default = 0) 18 ac alignment check flag. (default = 0) 17 vm virtual 8086 flag. (default = 0) 16 rf resume flag. disable instruction address breakpoints. (default = 0) 15 rsvd reserved. (default = 0) 14 nt nested task flag. (default = 0) 13:12 iopl input/output privilege level. (default = 0) 11 of overflow flag. (default = 0) 10 df repeated-string direction flag. (default = 0) 9if eternal maskable interrupt enable. (default = 0) 8tf single-step trap flag. (default = 0) 7sf sign flag. (default = 0) 6zf zero flag. (default = 0) 5 rsvd reserved. (default = 0) 4af auxiliary carry flag. (default = 0) 3 rsvd reserved. (default = 0) 2pf parity flag. (default = 0) 1 rsvd reserved. (default = 1) 0cf carry flag. (default = 1) msr address 00001420h ty p e r / w reset value 00000000_60000010h
150 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.51 instruction me mory configuration msr (im_config_msr) msr address 00001700h ty p e r / w reset value 00000000_00000000h im_config_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 lock rsvd drt rsvd abse ebe rsvd icd tus rsvd l0d l0in rsvd ser fld tbe im_config_msr bit descriptions bits name description 63:32 rsvd reserved. (default = 0) 31:24 lock lock. locks ways of the instruction cache from being allocated or replaced on an instruction cache miss. if all ways are locked, caching is effectively disabled. bit 31: ways 15 & 14 bit 30: ways 13 & 12 bit 29: ways 11 & 10 bit 28: ways 9 & 8 bit 27: ways 7 & 6 bit 26: ways 5 & 4 bit 25: ways 3 & 2 bit 24: ways 1 & 0 0: not locked. (default) 1: locked 23:17 rsvd reserved. 16 drt dynamic retention test. allow dynamic retention te st for bist of tag array. 0: disable. (default) 1: enable. 15:12 rsvd reserved. (default = 0) 11 abse aborts for speculat ive instruction fetch requests enable. enable aborts for specu- lative if requests for which there is an l1 tlb miss. im passes the speculative informa- tion from if directly to dm. dm responds in one of four ways: returns page if it hits in the l2. returns abort if it does not hit in the l2 and it a speculative request. returns a retry if it does not hit in the l2 and it was a non-speculative request and the pipe is not idle, does a tablewalk if it does not hit in the l2 and it was a non-spec ulative request and the pipe is idle. 0: disable. (default) 1: enable. 10 ebe instruction memory eviction bus enable. the default is to have im evictions disabled. this bit should be set when the l2 cache is enabled, since the l2 cache operates exclu- sively in victim mode. 0: disable. invalidate clean cache lines when replaced, do not evict. (default) 1: enable. evict clean cache lines when they are replaced. 9 rsvd reserved.
amd geode? lx processors data book 151 cpu core register descriptions 33234h 8icd instruction cache disable. completely disable l0 and l1 instruction caches. contents of cache is not modified and no cache entry is read. 0: use standard x86 cacheability rules. (default) 1: instruction cache will always generate a miss. 7tus translation look-aside buffer updates select. select l1 tlb updates (not l1 tlb evictions) to go out on the im?s translation bus. otherwise, only l1 tlb evictions go out on im?s translation bus. im only supports eit her updates or evictions going out on the bus, but not both. 0: disable. (default) 1: enable. 6 rsvd reserved. always write zero. 5 l0d l0 cache disable. 0: disable. (default) 1: enable. 4 l0in l0 cache invalidate. 0: disable. (default) 1: enable. 3 rsvd reserved. 2 ser serialize cache state machine. if this bit is set, only one outstanding request to the bus controller is allowed at one time. 0: disable. (default) 1: enable. 1fld flushing disable. disable full flushing of the im (including outstanding bus controller requests) on if aborts. if this bit is disabled, the im only aborts requests that have not already gone out to the bus controller. 0: enable. (default) 1: disable. 0tbe treatment bus enable. if this bit is set, then the treatm ent bus from the glcp is able to modify the im?s behavior. 0: disable. (default) 1: enable im_config_msr bit descriptions (continued) bits name description
152 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.52 instruction cache index msr (ic_index_msr) 5.5.2.53 instruction cache data msr (ic_data_msr) msr address 00001710h ty p e r / w reset value 00000000_00000000h ic_index_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dsel rsvd way line ic_index_msr bit descriptions bits name description 63:18 rsvd (ro) reserved (read only). 17:16 dsel data qword select for l1 cache msr access. determines which qword in a cache line is accessed by a read or a write to ic_data_msr (msr 00001711h). this field resets to 0 on any access to ic_tag_msr (msr 00001712h) or ic_tag_i_msr (msr 00001713h) and increments on access to ic_data_msr. this field is not used when accessing the l0 cache. (default = 0) 15:11 rsvd (ro) reserved (read only). 10:7 way l1 cache way to access. forms the high-order bits of an 11-bit counter. the line field (bits [6:0]) forms the low seven bits of the counter. this field increments when the line field overflows on a access to ic_tag_i_msr (msr 00001713h). this field is not used for the l0 cache. (default = 0) 6:0 line l1 cache line to access. forms the low-order bits of an 11-bit counter. the way field (bits [3:0]) forms the high four bits of the counter. this field post-increments on an access to ic_tag_i_msr (msr 00001713h). when accessing the l0 cache, only bits [4:0] are important and are used to select the line to read in the l0 cache. (default = 0) msr address 00001711h ty p e r / w reset value xxxxxxxx_xxxxxxxxh ic_data_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 data (upper) 313029282726252423222120191817161514131211109876543210 data (lower) ic_data_msr bit descriptions bits name description 63:0 data qword to read from or write to the l1 cache. the address to the qword specified by the line and dsel fields from ic_index_msr (msr 00001710h). the way in the cache to read and write is specified by the way field in ic_index_msr. each access to ic_data_msr increments dsel.
amd geode? lx processors data book 153 cpu core register descriptions 33234h 5.5.2.54 instruction cache tag (ic_tag_msr) msr address 00001712h ty p e r / w reset value 00000000_00000000h ic_tag_msr msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd lru 313029282726252423222120191817161514131211109876543210 tag rsvd v ic_tag_msr bit descriptions bits name description 63:47 rsvd (ro) reserved (read only). 46:32 lru least recently used bits for the cache line. same data will be read for all ways in a line. if bit(s) are set to 1: bit 46: ways (15-8) more recent than ways (7-0) bit 45: ways (15-12) more recent than ways (11-8) bit 44: ways (15,14) more recent than ways (13,12) bit 43: way 15 more recent than way 14 bit 42: way 13 more recent than way 12 bit 41: ways (11,10) more recent than ways (9,8) bit 40: way 11 more recent than way 10 bit 39: way 9 more recent than way 8 bit 38: ways (7-4) more recent than ways (3-0) bit 37: ways (7,6) more recent than ways (5,4) bit 36: way 7 more recent than way 6 bit 35: way 5 more recent than way 4 bit 34: ways (2,3) more recent than ways (1,0) bit 33: way 3 more recent than way 2 bit 32: way 1 more recent than way 0 31:12 tag tag. cache tag value for the line/way selected by ic_index_msr (msr 00001710h). (default = 0) 11:1 rsvd (ro) reserved (read only). 0v valid. valid bit for the line/way selected by ic_index_msr (msr 00001710h). (default = 0)
154 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.55 instruction cache tag with increment (ic_tag_i_msr) 5.5.2.56 l0 instruction cach e data msr (l0_ic_data_msr) 5.5.2.57 l0 instruction cache tag wi th increment msr (l0_ic_tag_i_msr) msr address 00001713h ty p e r / w reset value 00000000_00000000h ic_tag_i_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd lru 313029282726252423222120191817161514131211109876543210 tag rsvd v ic_tag_i_msr bit descriptions bit name description 63:0 --- definition same as instructio n cache tag msr (msr 00001712h). except read/write of this register causes an auto-increment on the ic_index_msr (msr 00001710h). msr address 00001714h ty p e r o reset value xxxxxxxx_xxxxxxxxh l0_ic_data_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 data (upper) 313029282726252423222120191817161514131211109876543210 data (lower) l0_ic_data_msr bit descriptions bits name description 63:0 data qword read from l0 cache. the address to the qword sp ecified by the line field from ic_index_msr (msr 00001710h[4:0]). msr address 00001715h ty p e r o reset value 00000000_xxxxxxxxh l0_ic_tag_i_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 tlb_num rsvd tag line rsvd v
amd geode? lx processors data book 155 cpu core register descriptions 33234h 5.5.2.58 l1 instruction tlb index (itb_index_msr) the l1 instruction tlb is accessible via an index/data mechanism. the index of the entry to access is set via itb_index_msr and an entry is read or written via itb_ entry_msr or itb_entry_i_msr. an autoincrement mecha- nism is provided to post-increment itb_index_msr af ter every access to itb_entry_i_msr. the l0 tlb can be accessed by a read only msr and it is not necessary to use the itb_index_msr to read the l0 tlb. the l1 tlb lru bits can be accessed using the itb_lru_msr. diagnostic accesses to the l0 or l1 instruction tlb array do not affect the values of the lru bits. note that the l1 instruction tlb is always in use and canno t be disabled. that means that diagnostic accesses generated by code running on the processor are unreliable at best, since the tlb contents may be changing while the code is running. furthermore, the l1 instruction tlb is flushed on any mode change, so a debug handler would no longer see the tlb con- tents prior to the dmi. thus the l1 inst ruction tlb accesses are intended only to be used by the glcp after the pipeline has been halted. l0_ic_tag_i_msr bit descriptions bits name description 63:32 rsvd reserved. 31:16 tlb_num tlb number. this is the one-hot-value of the tlb entry corresponding to the l0 cache entry. (default = 0) 15:12 rsvd reserved. 11:8 tag tag/line. this is a combination of the 4-bit tag and the 5-bit line. together they make up bits [11:3] of the physical address for the line selected by ic_index_msr (msr 00001710h). 7:3 line 2:1 rsvd reserved. 0v valid. valid bit for the line selected by ic_index_msr (msr 00001710h). (default = 0) msr address 00001720h ty p e r / w reset value 00000000_0000000xh itb_index_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd index itb_index_msr bit descriptions bits name description 63:4 rsvd reserved. 3:0 index index.
156 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.59 l1 instruction tlb least recently used msr (itb_lru_msr) msr address 00001721h ty p e r / w reset value 00000000_00000000h itb_lru_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd lru itb_lru_msr bit descriptions bits name description 63:30 rsvd (ro) reserved (read only). (default = 0) 29:0 lru least recently used value. bit 29: entries 8-11 more recent than entries 12-15 bit 28: entries 4-7 more recent than entries 12-15 bit 27: entries 4-7 more recent than entries 8-11 bit 26: entries 0-3 more recent than entries 12-15 bit 25: entries 0-3 more recent than entries 8-11 bit 24: entries 0-3 more recent than entries 4-7 bit 23: entry 14 more recent than entry 15 bit 22: entry 13 more recent than entry 15 bit 21: entry 13 more recent than entry 14 bit 20: entry 12 more recent than entry 15 bit 19: entry 12 more recent than entry 14 bit 18: entry 12 more recent than entry 13 bit 17: entry 10 more recent than entry 11 bit 16: entry 9 more recent than entry 11 bit 15: entry 9 more recent than entry 10 bit 14: entry 8 more recent than entry 11 bit 13: entry 8 more recent than entry 10 bit 12: entry 8 more recent than entry 9 bit 11: entry 6 more recent than entry 7 bit 10: entry 5 more recent than entry 7 bit 9: entry 5 more recent than entry 6 bit 8: entry 4 more recent than entry 7 bit 7: entry 4 more recent than entry 6 bit 6: entry 4 more recent than entry 5 bit 5: entry 2 more recent than entry 3 bit 4: entry 1 more recent than entry 3 bit 3: entry 1 more recent than entry 2 bit 2: entry 0 more recent than entry 3 bit 1: entry 0 more recent than entry 2 bit 0: entry 0 more recent than entry 1 0: false (default) 1: true
amd geode? lx processors data book 157 cpu core register descriptions 33234h 5.5.2.60 l1 instruct ion tlb entry msrs itb entry msr (itb_entry_msr) itb entry with incremen t msr (itb_entry_i_msr) itb l0 cache entry msr (itb_l0_entry_msr) msr address 00001722h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001723h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001724h ty p e r / w reset value xxxxxxxx_xxxxxxxxh itb_entry_msr, itb_entry_i_msr, itb_l0_entry_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 linaddr rsvd 313029282726252423222120191817161514131211109876543210 physaddr ws rsvd cd rsvd us rsvd v itb_entry_msr, itb_entry_i_msr, itb_l0_entry_msr bit descriptions bits name description 63:44 linaddr linear address. 43:32 rsvd (ro) reserved (read only). (default = 0) 31:12 physaddr physical address. 11 ws write serialize property. 0: not write serialized. (default) 1: write serialized. 10:5 rsvd (ro) reserved (read only). (default = 0) 4cd cache disable. 0: cache enabled. 1: cache disabled. 3 rsvd (ro) reserved (read only). (default = 0) 2us user access privileges. 0: supervisor. 1: user. 1 rsvd (ro) reserved (read only). (default = 0) 0v valid bit. 0: not valid. (default) 1: valid.
158 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.61 instruction memory subsyste m bist tag msr (im_bist_tag_msr) the instruction memory s ubsystem supports built-in self-test (bist) for the tag and data arrays. normally, bist is run dur- ing manufacturing test. for convenience, bist can be activated by reading the bist msrs. warning: it is important that the instru ction cache be disabled before initiating bist via msrs. there are no guarantees of proper behavior if bist is activate d with the instruction cache enabled. the instruction cache can be disabled through the im_config_msr (msr 00001700h[4]). 5.5.2.62 instruction memory subsyste m bist data msr (im_bist_data_msr) msr address 00001730h ty p e r o reset value 00000000_0000000xh im_bist_tag_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd cmp tag im_bist_tag_msr bit descriptions bits name description 63:2 rsvd (ro) reserved (read only). (default = 0) 1cmp tag compare logic bist. 0: fail (default) 1: pass 0tag valid and tag array bist. 0: fail (default) 1: pass msr address 00001731h ty p e r o reset value 00000000_0000000xh im_bist_data_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd data im_bist_data_msr bit descriptions bits name description 63:1 rsvd (ro) reserved (read only). (default = 0) 0data data array bist. 0: fail 1: pass
amd geode? lx processors data book 159 cpu core register descriptions 33234h 5.5.2.63 data memory subsystem configuration 0 msr (dm_config0_msr) msr address 00001800h ty p e r / w reset value 00000000_00000000h dm_config0_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd snoopto rsvd wsreq rsvd wcto rsvd wbto rsvd wbdis 313029282726252423222120191817161514131211109876543210 lslock nolockevct evctonrpl nofttbres dtcninv p4mdis dtcdis l2tdis dcdis spcdec wtbrst wbinvd nosmc nofwd blockc misser ldser dm_config0_msr bit descriptions bits name description 63:49 rsvd reserved. (default = 0) 48 snoopto snoop timeout. allow dm to escape a snoop deadlock by timing out a snoop request to the dm tag machine. 0: disable. 1: enable. (default) 47 rsvd reserved. (default = 0) 46:44 wsreq number of outstanding wr ite-serialized requests. the system must be able to accept wsreq+1 cacheline + 2-4 qword writes without backing up the bus controller to prevent a lockup condition in the event of an inbound snoop hit. 000: unlimited. (default) 001-111: binary value. 43 rsvd reserved. (default = 0) 42:40 wcto write-combine timeout. flushes write-combinable entry from write buffer if it has not been written for the specified number of clocks. 000: disable timeout. (default) 001-111: 2**(4 + wcto) clocks (32, 64, ..., 2048). 39 rsvd reserved. (default = 0) 38:36 wbto write-burst timeout. flushes write-burstable entry from write buffer if it has not been written for the specified number of clocks. 000: disable timeout. (default) 001-111: 2**(4 + wbto) clocks (32, 64, ..., 2048). 35:33 rsvd reserved. (default = 0)
160 amd geode? lx processors data book cpu core register descriptions 33234h 32 wbdis write buffer disable. disabling the write buffer forces st ores to be sent directly from the output of the store queue to the bus controller. enabling the write buffer allows memory stores to be buffered, with or without combining based on region properties. 0: enable write buffer. (default) 1: disable write buffer. note: if write allocate is used in any region configuration register, then the write buffer must be enabled. 31:16 lslock load/store lockout. bit mask of ways which cannot be allocated or replaced on a load or store miss. if all ways are locked, cachin g is effectively disabled, though the cache will still be interrogated. use dcdis (bit 8) to disa ble the interrogations as well. note that this field has been increased from 4 bits in the amd geode? gx processor to 16 bits to allow for the new 16 way cache). (default = 0) 15 nolockevct do not evict clean lines locked by lslock. when this bit is 1, clean lines locked by lslock will not be evicted into the l2 cache upon replacement. this feature is intended to be used with the auto-prefetch mechanism to prevent auto-prefetched data from get- ting into the l2 cache. in this case, lslo ck and apflock would divide the ways of the cache into prefetched and non-prefetched ways. only the non-prefetched ways would be evicted into the l2. (default = 0) 14 evctonrpl evict clean lines on replacement. this bit should be set when an external l2 cache is operating in victim mode. 0: invalidate clean cache lines when replaced, do not evict. (default) 1: evict clean cache lines when they are replaced. 13 nofttbres no page fault. do not page fault if any reserved bits are set in the directory table entries (dte)/page table entries (pte). 0: take the page fault. (default) 1: do not take the page fault. 12 dtcninv do not invalidate dte cache entry. do not invalidate dte cache entry on invlpg instruction. entire dte cache is still fl ushed on a store into the directory page. 0: invalidate dte cache entry if invlpg hits. (default) 1: do not invalidate dte cache entry on invlpg. 11 p4mdis disable 4m pte cache. 0: allow 4m ptes to be cached. (default) 1: do not cache 4m ptes a nd flush any existing entries. 10 dtcdis disable dte cache. 0: allow dtes to be cached. (default) 1: do not cache dtes, flush any existing entries. 9 l2tdis disable l2 tlb. contents will not be modified. 0: interrogate and allocate entries in the l2 tlb. (default) 1: l2 tlb will always generate a miss. 8 dcdis disable data cache (completely). contents will not be modified. intended to be used for array testing or in ca se of cache array failure. 0: use standard x86 cacheability rules. (default) 1: data cache will always generate a miss. dm_config0_msr bit descriptions (continued) bits name description
amd geode? lx processors data book 161 cpu core register descriptions 33234h 7 spcdec decrease number of speculative reads of data cache. 0: actively resync cache tag and data arrays so that loads can be speculatively handled in one clock if the mru way is hit. (default) 1: do not attempt to resync cache tag and data arrays. this is a performance optimizat ion bit and the preferred value may have to be empirically determined. the cache tag and data arrays get ?out of sync? when there is a miss to the mru way or if the data array is busy with a st ore, linefill, or evicti on. while the arrays are out of sync, all hits take 2 clocks. when th ey are in sync, hits to the mru way take 1 clock while hits to other ways take 3. 6wtbrst write-through bursting. 0: writes are sent unmodified to the bu s on write-through operations. (default) 1: writes may be combined using write-burs table semantics on write-through operations. 5wbinvd convert invd to wbinvd instruction. 0: invd instruction invalidates cache without writeback. (default) 1: invd instruction writes back any dirty cache lines 4nosmc snoop detecting on self-modified code. generates snoops on stores for detecting self-modified code. 0: generate snoops. (default) 1: disable snoops. 3nofwd forward data from bus controller. enable forwarding of data directly from bus control- ler if a new request hits a line fill in progress. 0: forward data from bus controller if possible. (default) 1: wait for valid data in cache, then read cache array. 2blockc blocking cache. 0: new request overlapp ed with linefill. (default) 1: linefill must complete before starting new request. 1 misser serialize load misses. stall everything but snoops on a load miss. set this bit if part of pci space is marked as cacheable (e.g., for a rom), data accesses will be made from that cacheable space, and there is a pci mast er device which must complete a master request before it will complete a slave read. 0: load misses are treated the same as load hits. (default) 1: load misses prevent non-snoop requests fr om being handled until the miss data is returned by the bus controller. 0 ldser serialize loads vs stores. all loads are serialized versus stores in the store queue, but a load that hits the cache completes without affecting any pending stores in the write buffers. 0: loads bypass stores based on region properties. (default) 1: all loads and stores are executed in program order. dm_config0_msr bit descriptions (continued) bits name description
162 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.64 data memory subsystem configuration 1 msr (dm_config1_msr) msr address 00001801h ty p e r / w reset value 00000000_00000000h dm_config1_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd apflock 313029282726252423222120191817161514131211109876543210 rsvd apfmode apfena rsvd pfxlockena nopfxevct arraydis pfxlock dm_config1_msr bit descriptions bits name description 63:48 rsvd reserved. 47:32 apflock auto-prefetch lock. bit mask of ways that cannot be allocated or replaced on an auto- prefetch issued for a cache miss due to an in struction that is not using the restricted cache prefix. automatic prefetches that result from rest ricted cache prefix instructions use the pfxlock field (bits [15:0]) for way masking. (default = 0) 31:27 rsvd reserved. 26:25 apfmode auto-prefetch mode. when auto-prefetching is enabled via the apfena bit (bit 24), apfmode determines how the prefetches are issued as follows: 00: even only. an auto-prefetch is issued for the odd cache line when a fill is issued for an even cache line, but no auto-prefetch is issued for a fill on an odd cache line. for example, when a fill request is issued for address 0h, a prefetch will be issued for address 20h. (default) 01: even/odd. auto-prefetches are issued for an odd cache line when an even fill is issued, and for even cache lines when an odd fill is issued. (i.e the auto-prefetch address is the toggle of fill address a[5]). using this mode effectively increases the dm logical cache line size to 64 bytes for fills. line replacements and snoop evictions are still done using a 32-byte line size. 1x: increment. auto-prefetches are issued for th e next cache line (auto- prefetch line = fill line + 1) when a fill is issued, except for the last cache line in a 4k page (fill address bits [11:5] = 1111111b). 24 apfena auto-prefetch enable. allows dm to perform automatic prefetch operations based on cache fills as specified by th e apfmode field (bits [26:25]). 0: disable. 1: enable. 23:22 rsvd reserved. 21 pfxlockena prefetch prefix instructions lock enable. when this bit is enabled, the lslock field in dm_config0 (msr 00001800h[31:16]) determines which ways are available for replacement for all processor memory refe rences except prefetch instructions. 0: disable the restricted cache feature. (default) 1: enable the restricted cache featur e (pfxlock field, bits [15:0]).
amd geode? lx processors data book 163 cpu core register descriptions 33234h 5.5.2.65 data memory subsystem pr efetch lock msr (dm_pflock_msr) 20 nopfxevct no prefetch prefix evictions. this bit disables clean line eviction in the case where a new allocation occurs on a load/store miss when a move string operation uses the repnz prefix instead of the normal rep prefix (restricted cache move feature, see pfx- lock, bits [15:0]). when nopfxevct is set, cache lines replaced by a load instruction using the restricted cache prefix (repnz) will not be evicted if they are clean. (see evc- tonrpl bit description in dm_config0 _msr (msr 00001800h[14]) for clean line eviction feature). clean line evictions of this type can be disabled in order to protect the victim mode l2 cache from being polluted by the transient data being moved. if this bit is a 0, then normal clean line eviction occurs on any line replacement if enabled by the evctonrpl bit. note that any dirty line that is replaced will be evicted regardless of the state of this bit. (default = 0) 19:16 arraydis array disable. mask used to disable individual cache arrays (way groups) in the dm to save power or to avoid array defects. when an array is disabled, the dm will not read or write the data array or tag ar ray associated with this way group, reducing power. any data in the cache must be flushed before disabling an array or it will be lost. bit 19: ways 15-12 bit 18: ways 11-8 bit 17: ways 7-4 bit 16: ways 3-0 0: enable. (default) 1: disable. 15:0 pfxlock prefetch prefix instructions lock. bit mask of ways that cannot be allocated or replaced on a load miss when a move string oper ation uses the repnz prefix (instead of the normal rep prefix). if all ways are locked, caching is effectively disabled, though the cache will still be interrogated. note that t he repnz prefix has no effect on prefetch instructions or writes to a write-allocate region that miss the cache and cause a write- allocate. (default = 0) msr address 00001804h ty p e r / w reset value 00000000_00000000h dm_config1_msr bit desc riptions (continued) bits name description dm_pflock_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 pflockt2 pflockt1 313029282726252423222120191817161514131211109876543210 pflockt0 pflocknta
164 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.66 default regi on configuration properties msr (rconf_default_msr) dm_pflock_msr bit descriptions bits name description 63:48 pflockt2 prefetch lockout of prefetcht2. bit mask of ways that cannot be allocated or replaced on a data prefetch miss on a pref ectht2 instruction. if all ways are locked, prefetcht2 is effectively disabled. use this field to prevent data prefetch operations from polluting too much of the cache. (default = 0) 47:32 pflockt1 prefetch lockout of prefetcht1. bit mask of ways that cannot be allocated or replaced on a data prefetch miss on a pref ectht1 instruction. if all ways are locked, prefetcht1 is effectively disabled. use this field to prevent data prefetch operations from polluting too much of the cache. (default = 0) 31:16 pflockt0 prefetch lockout of prefetcht0. bit mask of ways that cannot be allocated or replaced on a data prefetch miss on a pref ectht0 instruction. if all ways are locked, prefetcht0 is effectively disabled. use this field to prevent data prefetch operations from polluting too much of the cache. (default = 0) 15:0 pflocknta prefetch lockout of prefetchnta. bit mask of ways that cannot be allocated or replaced on a data prefetch miss on a prefec thnta instruction. if all ways are locked, prefetchnta is effectively disabled. use this field to prevent data prefetch operations from polluting too much of the cache. (default = 0) msr address 00001808h ty p e r / w reset value 01fffff0_10000001h warm start value 04xxxxx0_1xxxxx01h rconf_default_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 romrp rombase devrp 313029282726252423222120191817161514131211109876543210 devrp systop sysrp rconf_default_msr bit descriptions bit name description 63:56 romrp rom region properties. region properties for addresses greater than rombase (bits 55:36]). 55:36 rombase rom base address. base address for boot rom. this field represents a[32:12] of the memory address space, 4 kb granularity. 35:28 devrp systop to rombase region properties. region properties for addresses less than rombase (bits 55:36]) and addre sses greater than or equal to systop (bits [27:8]). 27:8 systop top of system memory. top of system memory that is available for general processor use. the frame buffer and other privat e memory areas are located above systop. 7:0 sysrp system memory region properties. region properties fo r addresses less than sys- top (bits [27:8]). note t hat region configuration 000a 0000h-000fffffh takes prece- dence over sysrp. note: region properties: bits [7:6] = rsvd; bit 5 = ws; bit 4 = wc; bit 3 = wt; bit 2 = wp; bit 1 = wa; bit 0 = cd. see "region properties" on page 170 for further details.
amd geode? lx processors data book 165 cpu core register descriptions 33234h 5.5.2.67 region configuration by pass msr (rconf_bypass_msr) 5.5.2.68 region configuration a 0000-bffff msr (rconf_a0_bf_msr) msr address 0000180ah ty p e r / w reset value 00000000_00000101h warm start value 00000000_00000219h rconf_bypass_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd rpsmhdr rptlb rconf_bypass_msr bit descriptions bit name description 63:16 rsvd reserved. 15:8 rpsmhdr region properties during smm/dmm. region configuration properties used during smm/dmm header accesses. 7:0 rptlb region properties during tablewalks. note: region properties: bits [7:6] = rsvd; bit 5 = ws; bit 4 = wc; bit 3 = wt; bit 2 = wp; bit 1 = wa; bit 0 = cd. see "region properties" on page 170 for further details. msr address 0000180bh ty p e r / w reset value 01010101_01010101h warm start value 19191919_19191919h rconf_a0_bf_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rpbc rpb8 rpb4 rpb0 313029282726252423222120191817161514131211109876543210 rpac rpa8 rpa4 rpa0 rconf_a0_bf_msr bit descriptions bit name description 63:56 rpbc region properties for 000bc000-000bffff. 55:48 rpb8 region properties for 000b8000-000bbfff. 47:40 rpb4 region properties for 000b4000-000bafff. 39:32 rpb0 region properties for 000b0000-000b3fff. 31:24 rpac region properties for 000ac000-000affff. 23:16 rpa8 region properties for 000a8000-000abfff. 15:8 rpa4 region properties for 000a4000-000a7fff. 7:0 rpa0 region properties for 000a0000-000a3fff. note: region properties: bits [7:6] = rsvd; bit 5 = ws; bit 4 = wc; bit 3 = wt; bit 2 = wp; bit 1 = wa; bit 0 = cd. see "region properties" on page 170 for further details.
166 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.69 region configuration c 0000-dffff msr (rconf_c0_df_msr) 5.5.2.70 region configuration e 0000-fffff msr (rconf_e0_ff_msr) msr address 0000180ch ty p e r / w reset value 01010101_01010101h warm start value 19191919_19191919h rconf_c0_df_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rpdc rpd8 rpd4 rpd0 313029282726252423222120191817161514131211109876543210 rpcc rpc8 rpc4 rpc0 rconf_c0_df_msr bit descriptions bit name description 63:56 rpdc region properties for 000dc000-000dffff. 55:48 rpd8 region properties for 000d8000-000dbfff. 47:40 rpd4 region properties for 000d4000-000dafff . 39:32 rpd0 region properties for 000d0000-000d3fff. 31:24 rpcc region properties for 000cc000-000cffff. 23:16 rpc8 region properties for 000c8000-000cbfff. 15:8 rpc4 region properties for 000c4000-000c7fff. 7:0 rpc0 region properties for 000c0000-000c3fff. note: region properties: bits [7:6] = rsvd; bit 5 = ws; bit 4 = wc; bit 3 = wt; bit 2 = wp; bit 1 = wa; bit 0 = cd. see "region properties" on page 170 for further details. msr address 0000180dh ty p e r / w reset value 01010101_01010101h warm start value 19191919_19191919h rconf_e0_ff_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rpfc rpf8 rpf4 rif0 313029282726252423222120191817161514131211109876543210 rpec rpe8 rpe4 rpe0
amd geode? lx processors data book 167 cpu core register descriptions 33234h 5.5.2.71 region configuratio n smm msr (rconf_smm_msr) rconf_e0_ff_msr bit descriptions bit name description 63:56 rpfc region properties for 000fc000-000fffff. 55:48 rpf8 region properties for 000f8000-000fbfff. 47:40 rpf4 region properties for 000f4000-000fafff. 39:32 rpf0 region properties for 000f0000-000f3fff. 31:24 rpec region properties for 000ec000-000effff. 23:16 rpe8 region properties for 000e8000-000ebfff. 15:8 rpe4 region properties for 000e4000-000e7fff. 7:0 rpe0 region properties for 000e0000-000e3fff. note: region properties: bits [7:6] = rsvd; bit 5 = ws; bit 4 = wc; bit 3 = wt; bit 2 = wp; bit 1 = wa; bit 0 = cd. see "region properties" on page 170 for further details. msr address 0000180eh ty p e r / w reset value 00000001_00000001h warm start value xxxxx001_xxxxx005h rconf_smm_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 smmtop rsvd rpsmm 313029282726252423222120191817161514131211109876543210 smmbase rsvd rpsmm_en smm_norm rconf_smm_msr bit descriptions bit name description 63:44 smmtop top of smm. top of smm region, 4 kb granularity inclusive. 43:40 rsvd reserved. 39:32 rpsmm region properties in smm region when smm active. 31:12 smmbase start of smm. start of smm region, 4 kb granularity inclusive 11:9 rsvd reserved. 8 rpsmm_en smm properties region enable. 0: disable. 1: enable. 7:0 smm_norm region properties in smm region when smm inactive. note: region properties: bits [7:6] = rsvd; bit 5 = ws; bit 4 = wc; bit 3 = wt; bit 2 = wp; bit 1 = wa; bit 0 = cd. see "region properties" on page 170 for further details.
168 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.72 region configuratio n dmm msr (rconf_dmm_msr) msr address 0000180fh ty p e r / w reset value 00000001_00000001h warm start value xxxxx001_xxxxx005h rconf_dmm_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dmmtop rsvd rpdmm 313029282726252423222120191817161514131211109876543210 dmmbase rsvd rpdmm_en dmm_norm rconf_dmm_msr register bit descriptions bit name description 63:44 dmmtop top of dmm. top of dmm region, 4 kb granularity inclusive. 43:40 rsvd reserved. 39:32 rpdmm region properties in dmm region when dmm active. 31:12 dmmbase start of dmm. start of dmm region, 4 kb granularity inclusive. 11:9 rsvd reserved. 8 rpdmm_en dmm properties region enable. 0: disable. 1: enable. 7:0 dmm_norm region properties in dmm region when dmm inactive. note: region properties: bits [7:6] = rsvd; bit 5 = ws; bit 4 = wc; bit 3 = wt; bit 2 = wp; bit 1 = wa; bit 0 = cd. see "region properties" on page 170 for further details.
amd geode? lx processors data book 169 cpu core register descriptions 33234h 5.5.2.73 region configuratio n range msrs 0 through 7 region configuration ra nge 0 msr (rconf0_msr) region configuration ra nge 1 msr (rconf1_msr) region configuration ra nge 2 msr (rconf2_msr) region configuration ra nge 3 msr (rconf3_msr) region configuration ra nge 4 msr (rconf4_msr) region configuration ra nge 5 msr (rconf5_msr) region configuration ra nge 6 msr (rconf6_msr) region configuration ra nge 7 msr (rconf7_msr) msr address 00001810h ty p e r / w reset value 00000000_00000000h warm start value xxxxx000_xxxxx0xxh msr address 00001811h ty p e r / w reset value 00000000_00000000h warm start value xxxxx000_xxxxx0xxh msr address 00001812h ty p e r / w reset value 00000000_00000000h warm start value xxxxx000_xxxxx0xxh msr address 00001813h ty p e r / w reset value 00000000_00000000h warm start value xxxxx000_xxxxx0xxh msr address 00001814h ty p e r / w reset value 00000000_00000000h warm start value xxxxx000_xxxxx0xxh msr address 00001815h ty p e r / w reset value 00000000_00000000h warm start value xxxxx000_xxxxx0xxh msr address 00001816h ty p e r / w reset value 00000000_00000000h warm start value xxxxx000_xxxxx0xxh msr address 00001817h ty p e r / w reset value 00000000_00000000h warm start value xxxxx000_xxxxx0xxh rconfx_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rptop rsvd 313029282726252423222120191817161514131211109876543210 rpbase rsvd rpen rp rconfx_msr bit descriptions bit name description 63:44 rptop top of range. 4 kb granularity, inclusive. 43:32 rsvd reserved. 31:12 rpbase start of range. 4 kb granularity, inclusive. 11:9 rsvd reserved. 8 rpen enable range. 0: disable range. 1: enable range. 7:0 rp range properties. note: region properties: bits [7:6] = rsvd; bit 5 = ws; bit 4 = wc; bit 3 = wt; bit 2 = wp; bit 1 = wa; bit 0 = cd. see "region properties" on page 170 for further details.
170 amd geode? lx processors data book cpu core register descriptions 33234h region properties the region properties consist of an 8-bit field as shown in table 5-15. table 5-16 and table 5-17 describe the various region properties effects on read and write operations. note that the cache is always interrogated even in regions that are not cacheable, and read hits are serviced from the cache while write hits update the cache and are sent to the bus using the region?s write semantics. table 5-15. region properties register map 76543210 (rsvd) reserved ws (write-serialize) wc (write-combine) wt (write-through) wp (write-protect) wa (write-allocate) cd (cache disable) table 5-16. read operations vs. region properties ws wc wt wp wa cd description 0xxxx0 cacheable. read misses cause a cache line to be allocated. 1xxxx0 undefined state. unpredictable behavior occurs. xxxxx1 uncacheable. reads are sent unmodified to th e bus. cache is still interro- gated and provides data for read hits. used for accessing memory-mapped devices. note: ?x? indicates setting or clearing this bit has no effect. table 5-17. write operations vs. region properties ws wc wt wp wa cd description xxx1xx write-protected. writes to the region are discarded. 1xxxx0 undefined state. unpredictable behavior occurs. x1xxx0 undefined state. unpredictable behavior occurs. xxxx11 undefined state . unpredictable behavior occurs. 000000 write-back cacheable. write misses are sent to the bus, a cache line is not allocated on a write miss. 000010 write-back cacheable/write-allocate. write misses alloca te a line in the cache. 0010x0 write-through cacheable. write misses do not allocate a line in the cache. write hits update the cache but do not mark the line as dirty. all writes are sent to the bus. 000001 uncacheable. all writes are sent to the bus in strict program order without any combining. write hits still update the cache. traditionally used for accessing memory-mapped devices (but see write-burstable below). 100001 uncacheable. all writes are sent to the bus in strict program order without any combining. write hits still update the cache. traditionally used for accessing memory-mapped devices (but see write-burstable below). write-serialize. limit the number of outstanding writes to the value of the wsreq field in dm_config0_m sr (msr 00001800h[46:44]). 010001 write-combined (uncacheable). writes to the same cache line may be com- bined. multiple writes to the same byte results in a single write with the last value specified. write order is not preserved; ideal for use with frame buffers.
amd geode? lx processors data book 171 cpu core register descriptions 33234h if paging is enabled, the region properties can be further modified by the pcd and pwt flags in the page table entry. the pcd flag is or?d with the cd bit of the region properties, and the pwt bit is or?d with the wt bit of the region properties. a similar combination is performed during tablewalks usi ng the pcd/pwt bits from cr3 for the dte access and the pcd/pwt bits from the dte for the pte acce ss. the net effect is that the wc and ws flags may actually be used even for a region that is marked cacheable if a page table mapping late r forces it to be uncacheable. fo r regions that are write-com- bined, the pwt flag in the page table can be used to force write-burstable properties for selected pages. 110001 write-combined (uncacheable). writes to the same cache line may be com- bined. multiple writes to the same byte results in a single write with the last value specified. write order is not preserved; ideal for use with frame buffers. write-serialize. limit the number of outstanding writes to the value of the wsreq field in dm_config0_msr (msr 00001800h[46:44]). 011001 write-burstable (uncacheable). writes to the same cache line are combined as long as they are to increasing addresses and do not access a previously written byte. multiple writes to the same byte results in multiple bytes on the bus. the semantics match write bursting on pci and should therefore be suit- able for accessing memory-mapped devices. 111001 write-burstable (uncacheable). writes to the same cache line are combined as long as they are to increasing addresses and do not access a previously written byte. multiple writes to the same byte results in multiple bytes on the bus. the semantics match write bursting on pci and should therefore be suit- able for accessing memory-mapped devices. write-serialize. limit the number of outstanding writes to the value of the wsreq field in dm_config0_msr (msr 00001800h[46:44]). note: ?x? indicates setting or clearing this bit has no effect. table 5-17. write operations vs. region properties (continued) ws wc wt wp wa cd description
172 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.74 x86 control register s msrs (cr1, cr2, cr3, cr4) these are the standard x86 control registers cr1, cr2, cr 3, and cr4. cr0 is located at msr 00001420h (see section 5.5.2.50 on page 149). the content s of cr0-cr4 should only be accessed using the mov instruction. they are mentioned here for completeness only. see section 5.4.1 ?contr ol registers? on page 95 for bit descriptions x86 control register 1 msr (cr1_msr) x86 control register 2 msr (cr2_msr) x86 control register 3 msr (cr3_msr) x86 control register 4 msr (cr4_msr) 5.5.2.75 data cache inde x msr (dc_index_msr) msr address 00001881h ty p e r / w reset value 00000000_xxxxxxxxh msr address 00001882h ty p e r / w reset value 00000000_xxxxxxxxh msr address 00001883h ty p e r / w reset value 00000000_xxxxxxxxh msr address 00001884h ty p e r / w reset value 00000000_xxxxxxxxh msr address 00001890h ty p e r / w reset value 00000000_00000000h dc_index_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dc_dsel rsvd dc_line dc_way dc_index_msr bit descriptions bit name description 63:18 rsvd (ro) reserved (read only). 17:16 dc_dsel data qword select. determines which qword in a cache line is accessed by a read or a write to dc_data_msr (msr 00001891h). dc_dsel increments on accesses to dc_data and resets to 0 on accesses to dc_tag_msr (msr 00001892h) or dc_tag_i_msr (msr 00001893h). 15:11 rsvd (ro) reserved (read only). 10:4 dc_line cache line select. forms the high 7 bits of a 9-bit counter. the dc_way field (bits [1:0]) forms the low 2 bits of the counter. this field increments when dc_way overflows on an access to dc_tag_i_msr (msr 00001893h). 3:0 dc_way cache way select. forms the low 2 bits of a 9-bit counter. the dc_line field (bits [10:4]) forms the high 7 bits of the counte r. this field post-increments on accesses to dc_tag_i_msr (msr 00001893h).
amd geode? lx processors data book 173 cpu core register descriptions 33234h 5.5.2.76 data cache data msr (dc_data_msr) 5.5.2.77 data cache tag msr (dc_tag_msr) msr address 00001891h ty p e r / w reset value 00000000_00000000h dc_data_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dc_data 313029282726252423222120191817161514131211109876543210 dc_data dc_data_msr bit descriptions bit name description 63:0 dc_data data cache data. qword data to read from or write to the cache line buffer. the buffer is filled from the cache data array on a read to dc_tag_msr (msr 00001892h) or dc_tag_i_msr (msr 00001893h), and the buffer is written to the cache data array on a write to dc_tag_msr or dc_tag_i_msr msrs. the dc_dsel field in the dc_index_msr (msr 00001890h[17:16]) select s which qword in the buffer is accessed by dc_data, and each access to dc_data increments dc_dsel. msr address 00001892h ty p e r / w reset value 00000000_00000000h dc_tag_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd lru 313029282726252423222120191817161514131211109876543210 tag rsvd dirty valid dc_tag_msr bit descriptions bits name description 63:50 rsvd (ro) reserved (read only). (default = 0)
174 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.78 data cache tag with increment msr (dc_tag_i_msr) bit descriptions for this register are the same as for msr 00001892h, except read/write of th is register causes an auto- increment on dc_index_msr (msr 00001890h). 49:32 lru least recently used value. (default = 0) bit 49: ways 11-8 more recent than ways 15-12. bit 48: ways 7-4 more recent than ways 15-12. bit 47: ways 7-4 more recent than ways 11-8. bit 46: ways 3-0 more recent than ways 15-12. bit 45: ways 3-0 more recent than ways 11-8. bit 44: ways 3-0 more recent than ways 7-4. bit 43: ways 15-14 more recent than ways 13-12. bit 42: ways 11-10 more recent than ways 9-8. bit 41: ways 7-6 more recent than ways 5-4. bit 40: ways 3-2 more recent than ways 1-0. bit 39: way 15 more recent than way 14. bit 38: way 13 more recent than way 12. bit 37: way 11 more recent than way 10. bit 36: way 9 more recent than way 8. bit 35: way 7 more recent than way 6. bit 34: way 5 more recent than way 4. bit 33: way 3 more recent than way 2. bit 32: way 1 more recent than way 0. 0: false 1: true 31:12 tag tag. cache tag value for line/way selected by dc_index (msr 00001890h). (default = 0) 11:2 rsvd (ro) reserved (read only). (default = 0) 1dirty dirty. dirty bit for line/way. (default = 0) warning: operation is undefined if the dirty bit is set to 1 and the valid bit is 0. 0valid valid. valid bit for the line/way selected by dc_index (msr 00001890h). (default = 0) msr address 00001893h ty p e r / w reset value 00000000_00000000h dc_tag_msr bit descriptions (continued) bits name description dc_tag_i_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd lru 313029282726252423222120191817161514131211109876543210 tag rsvd dirty valid
amd geode? lx processors data book 175 cpu core register descriptions 33234h 5.5.2.79 data/instruction cache snoop register (snoop_msr) the snoop_msr provides a mechanism for injecting a ?snoop-for-write? request in to the memory subsystem. both the i and d caches are snooped for the specified physical address. a hit to a dirty line in the d cache results in a writeback fol- lowed by the line being invalidated. a hit to a clean line result s in only an invalidation. the snoop_msr is write-only - the read value is undefined. there is no indication as to whether the snoop hit in the caches. 5.5.2.80 l1 data tlb index re gister (l1dtlb_index_msr) msr address 00001894h ty p e w o reset value 00000000_xxxxxxxxh snoop_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 snoop_add snoop_msr bit descriptions bit name description 63:32 rsvd reserved (write only). write as 0. 31:0 snoop_add cache snoop address (write only). physical address to snoop in the caches. a hit to a dirty line results in a writeback followed by an invalidation. a hit to a clean line results in an invalidation only. both the data and instruction caches are snooped. msr address 00001898h ty p e r / w reset value 00000000_00000000h l1dtlb_index_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd index l1dtlb_index_msr bit descriptions bit name description 63:3 rsvd (ro) reserved (read only). 2:0 index l1 data tlb index. index of l1 data tlb entry to access. post increments on each access to l1tlb_entry_i_msr (msr 0000189bh).
176 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.81 l1 data tlb least recen tly used msr (l1dtlb_lru_msr) msr address 00001899h ty p e r / w reset value 00000000_00000000h l1dtlb_lru_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd lru l1dtlb_lru_msr bit descriptions bits name description 63:18 rsvd (ro) reserved (read only). 17:0 lru least recently used value. bit 17: entries 8-11 more recent than entries 12-15. bit 16: entries 4-7 more recent than entries 12-15. bit 15: entries 4-7 more re cent than entries 8-11. bit 14: entries 0-3 more recent than entries 12-15. bit 13: entries 0-3 more re cent than entries 8-11. bit 12: entries 0-3 more recent than entries 4-7. bit 11: entries 12/13 more recent than entries 14/15. bit 10: entries 8/9 more recent than entries 10/11. bit 9: entries 4/5 more recent than entries 6/7. bit 8: entries 0/1 more recent than entries 2/3. bit 7: entry 14 more recent than entry 15. bit 6: entry 12 more recent than entry 13. bit 5: entry 10 more recent than entry 11. bit 4: entry 8 more recent than entry 9. bit 3: entry 6 more recent than entry 7. bit 2: entry 4 more recent than entry 5. bit 1: entry 2 more recent than entry 3. bit 0: entry 0 more recent than entry 1. 0: false (default) 1: true
amd geode? lx processors data book 177 cpu core register descriptions 33234h 5.5.2.82 l1 data tlb entr y msr (l1dtlb_entry_msr) msr address 0000189ah ty p e r / w reset value 00000000_00000000h l1dtlb_entry_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 linaddr rsvd wp wa_ws wc 313029282726252423222120191817161514131211109876543210 physaddr rsvd dirty acc cd wt_br us wr valid l1dtlb_entry_msr bit descriptions bit name description 63:44 linaddr linear address. address [32:12]. 43:35 rsvd (ro) reserved (read only). 34 wp write-protect flag. 0: page can be written. 1: page is write-protected. 33 wa_ws write-allocate/write-serialize flag. if the page is cacheable, a 1 indicates the write- allocate flag. if the page is non-cacheable, a 1 indicates the write-serialize flag. 32 wc write-combine flag. when this page is marked as non-cacheable, a 1indicates that writes may be combined before being sent to the bus. 31:12 physaddr physical address. address [32:12] 11:7 rsvd (ro) reserved (read only). 6dirty dirty flag. a 1 indicates that the page has been written to. 5acc accessed flag. a 1 indicates an entry in the tlb. 4cd cache disable flag. a 1 indicates that the page is uncacheable. 3wt_br write-through/write-burst flag. when the page is cacheable, a 1 indicates that the page is write-through. when the page is n on-cacheable, a 1 indicates that the page allows write bursting. 2us user access privileges. 0: supervisor. 1: user. 1wr writable flag. 0: page can not be written. 1: page can be written. 0valid valid bit. a 1 indicates that the entry in the tlb is valid.
178 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.83 l1 data tlb entry with in crement msr (l1dtlb_entry_i_msr) bit descriptions for this register are the same as for msr 0 000189ah, except read/write of this register causes an auto- increment on the l1 tlb_index_msr (msr 00001898h). 5.5.2.84 l2 tlb/dte/pte in dex msr (l2tlb_index_msr) msr address 0000189bh ty p e r / w reset value 00000000_00000000h l1dtlb_entry_i_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 linaddr rsvd wp wa_ws wc 313029282726252423222120191817161514131211109876543210 physaddr rsvd dirty acc cd wt_br us wr valid msr address 0000189ch ty p e r / w reset value 00000000_00000000h l2tlb_index_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd sel rsvd index way index l2tlb_index_msr bit descriptions bit name description if sel (bits [17:16]) = 0x 63:18 rsvd (ro) reserved (read only). (default = 0) 17:16 sel select array to access. 0x: l2 tlb (64 entries, values 0-63). 10: dte cache (12 entries, values 0-11). 11: 4m pte cache (4 entries, values 0-3). 15:6 rsvd (ro) reserved (read only). (default = 0) 5:1 index l2 tlb index. post-increments on an access to l2tb_entry_i_msr (msr 0000189fh) if way (bit 0) = 1. 0way way to access. toggles on each access to l2tb_entry_i_msr (msr 0000189fh). if sel (bits [17:16]) = 1x 63:18 rsvd (ro) reserved (read only). (default = 0) 17:16 sel select array to access. 0x: l2 tlb (64 entries, values 0-63). 10: dte cache (12 entries, values 0-11). 11: 4m pte cache (4 entries, values 0-3).
amd geode? lx processors data book 179 cpu core register descriptions 33234h 5.5.2.85 l2 tlb/dte/pt e least recently used msr (l2tlb_lru_msr) 15:6 rsvd (ro) reserved (read only). (default = 0) 5:0 index dte/pte index. increments on every access to l2tlb_entry_i_msr (msr 0000189fh). msr address 0000189dh ty p e r / w reset value 00000000_00000000h l2tlb_index_msr bit de scriptions (continued) bit name description l2tlb_lru_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd dte_lru 313029282726252423222120191817161514131211109876543210 rsvd pte_lru rsvd l2wr1 l2tlb_lru_msr bit descriptions bits name description 63:53 rsvd (ro) reserved (read only). (default = 0) 52:32 dte_lru dte least recently used value. bit 52: dte entries 0-3 more recent than entries 4-7. bit 51: dte entries 0-3 more recent than entries 8-11. bit 50: dte entries 4-7 more recent than entries 8-11. bit 49: dte entry 8 more recent than entry 9. bit 48: dte entry 8 more recent than entry 10. bit 47: dte entry 8 more recent than entry 11. bit 46: dte entry 9 more recent than entry 10. bit 45: dte entry 9 more recent than entry 11. bit 44: dte entry 10 more recent than entry 11. bit 43: dte entry 4 more recent than entry 5. bit 42: dte entry 4 more recent than entry 6. bit 41: dte entry 4 more recent than entry 7. bit 40: dte entry 5 more recent than entry 6. bit 39: dte entry 5 more recent than entry 7. bit 38: dte entry 6 more recent than entry 7. bit 37: dte entry 0 more recent than entry 1. bit 36: dte entry 0 more recent than entry 2. bit 35: dte entry 0 more recent than entry 3. bit 34: dte entry 1 more recent than entry 2. bit 33: dte entry 1 more recent than entry 3. bit 32: dte entry 2 more recent than entry 3. 0: false (default) 1: true 31:22 rsvd (ro) reserved (read only). (default = 0)
180 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.86 l2 tlb/dte/pte en try msr (l2tlb_entry_msr) 21:16 pte_lru 4m pte least recently used value. bit 21: 4m pte entry 0 more recent than entry 1. bit 20: 4m pte entry 0 more recent than entry 2. bit 19: 4m pte entry 0 more recent than entry 3. bit 18: 4m pte entry 1 more recent than entry 2. bit 17: 4m pte entry 1 more recent than entry 3. bit 16: 4m pte entry 2 more recent than entry 3. 0: false (default) 1: true 15:1 rsvd (ro) reserved (read only). (default = 0) 0 l2wr1 l2 write to way 1. next l2 tlb write to way 1 if both ways are valid. (default = 0) msr address 0000189eh ty p e r / w reset value 00000000_00000000h l2tlb_lru_msr bit descriptions (continued) bits name description l2tlb_entry_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 linaddr rsvd wp wa_ws wc linaddr rsvd 313029282726252423222120191817161514131211109876543210 physaddr rsvd global rsvd dirty acc cd wt_br us wr valid 4mpte wt l2tlb_entry_msr bit descriptions bit name description if sel bits in l2tlb_index msr = 0x (msr 0000189ch[17:16] = 0x) 63:44 linaddr linear address. address [32:12]. 43:35 rsvd (ro) reserved (read only). 34 wp write-protect flag. 0: page can be written. 1: page is write-protected. 33 wa_ws write-allocate/write-serialize flag. if the page is cacheable, a 1 indicates the write- allocate flag. if the page is non-cacheable, a 1 indicates the write-serialize flag. 32 wc write-combine flag. when this page is marked as non-cacheable, a 1indicates that writes may be combined before being sent to the bus. 31:12 physaddr physical address. address [32:12] 11:9 rsvd (ro) reserved (read only). 8 global global page flag. a 1 indicates a global page.
amd geode? lx processors data book 181 cpu core register descriptions 33234h 7 rsvd (ro) reserved (read only). 6dirty dirty flag. a 1 indicates that the page has been written to. 5acc accessed flag. a 1 indicates an entry in the tlb. 4cd cache disable flag. a 1 indicates that the page is uncacheable. 3wt_br write-through/write burst flag. when the page is cacheable, a 1 indicates that the page is write-through. when the page is n on-cacheable, a 1 indicates that the page allows write bursting. 2us user access privileges. 0: supervisor. 1: user. 1wr writable flag. 0: page can not be written. 1: page can be written. 0valid valid bit. a 1 indicates that the entry in the tlb is valid. if sel bits in l2tlb_index msr = 1x (msr 0000189ch[17:16] = 1x) 63:44 linaddr linear address. address [32:22]. 53:32 rsvd (ro) reserved (read only). 31:12 physaddr physical address. address [32:12] 11:9 rsvd (ro) reserved (read only). 8 global global page flag. a 1 indicates a global page. 74mpte 4m pte flag. 0: dte access. 1: 4m pte access. 6dirty dirty flag. a 1 indicates that the page has been written to. 5acc accessed flag. a 1 indicates an entry in the tlb. 4cd cache disable flag. a 1 indicates that the page is uncacheable. 3wt write-through flag. a 1 indicates that the page is write-through. 2us user access privileges. 0: supervisor. 1: user. 1wr writable flag. 0: page can not be written. 1: page can be written. 0valid valid bit. a 1 indicates that the entry in the tlb is valid. l2tlb_entry_msr bit descriptions (continued) bit name description
182 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.87 l2 tlb/dte/pte entry with increment msr (l2t lb_entry_i_msr) bit descriptions for this register are the same as for msr 0 000189eh, except read/write of this register causes an auto- increment on the l2tlb_index_msr (msr 0000189ch). 5.5.2.88 data memory subsystem bu ilt-in self-test msr (dm_bist_msr) msr address 0000189fh ty p e r / w reset value 00000000_00000000h l2tlb_entry_i_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 linaddr rsvd wp wa_ws wc 313029282726252423222120191817161514131211109876543210 physaddr rsvd global rsvd dirty acc cd wt_br us wr valid msr address 000018c0h ty p e r / w reset value 00000000_00000000h dm_bist_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 tag c m p tag dat 313029282726252423222120191817161514131211109876543210 tlbcmp tlbdat data rsvd reten_tlb run_tlb reten_data run_data reten_tag run_tag dm_bist_msr bit descriptions bits name description 63:48 tagcmp[15:0] (ro) cache tag comparators (read only). bist results for cache tag comparators (array15...array0). 0: fail. 1: pass. 47:32 tagdat[15:0] (ro) cache tag data (read only). bist results for cache tag data integrity (array15...array0). 0: fail. 1: pass. 31:30 tlbcmp[1:0] (ro) l2 tlb comparators (read only). bist results for l2 tlb comp arators (array1, array0). 0: fail. 1: pass. 29:28 tlbdat[1:0] (ro) l2 tlb data (read only). bist results for l2 tlb data integrity (array1, array0). 0: fail. 1: pass. 27:24 data[3:0] (ro) data cache data (read only). bist results for data cache data arrays[3:0]. 0: fail. 1: pass. 23:6 rsvd (ro) reserved (read only). read as 0.
amd geode? lx processors data book 183 cpu core register descriptions 33234h 5.5.2.89 bus controller configur ation 0 msr (bc_config0_msr) 5 reten_tlb l2 tlb retention timer. enable retention timer for l2 tlb bist. 0: disable. 1: enable. 4 run_tlb l2 tlb run. start bist test on l2 tlb arrays. should read as 0 because bist will have completed before the msr read can start. 3 reten_data cache data retention timer. enable retention timer fo r cache data array bist. 0: disable. 1: enable. 2 run_data cache data run. start bist test on cache data array. should read as 0 because bist will have completed before the msr read can start. 1 reten_tag cache tag retention timer. enable retention timer for cache tag array bist. 0: disable. 1: enable. 0 run_tag cache tag run. start bist test on cache tag arrays. should read as 0 because bist will have completed before the msr read can start. msr address 00001900h ty p e r / w reset value 00000000_00000111h dm_bist_msr bit descriptions bits name description bc_config0_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pausedly rsvd gpf_x rsvd clk_ons susp rsvd rtsc_susp rsvd tsc_dmm tsc_susp tsc_smm rsvd isninv snoop bc_config0_msr bit descriptions bit name description 63:28 rsvd reserved. write as read. 27:24 pausedly pause delay. this field sets the number of clocks for which the bus controller will attempt to suspend the cpu when a pause instruction is executed. the approximate number of clocks is pausedly*8. note that the actual number of clocks that the cpu is sus- pended will differ from this value, and will vary from pause to pause due to the overhead of the suspend/unsuspend mechanism and any ot her cpu activity that would affect how it responds to suspend requests. note also that bit 1 of msr 00001210h must be set in order for suspend on pause to be enabled. 23:21 rsvd reserved. 20 gpf_x general protection faults on except flags. generate general protection faults on msr accesses whose response packets have the except flag set. 0: disable. 1: enable.
184 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.90 bus controller configur ation 1 msr (bc_config1_msr) this register is reserved. write as read. 19:14 rsvd reserved. write as read. 13 clk_ons cpu core clocks on during suspend. 0: all cpu core clocks off during suspend. (default) 1: all cpu core clocks on during suspend. 12 susp suspend active. enable suspend input. 0: ignore suspend input. (default) 1: enable suspend input. 11:9 rsvd reserved. write as read. 8 rtsc_susp real time stamp counter counts during suspend. 0: disable. 1: enable. (default) 7 rsvd reserved. write as read. 6tsc_dmm time stamp counter counts during dmm. 0: disable. (default) 1: enable. 5tsc_susp time stamp counter counts during suspend. 0: disable. (default) 1: enable. 4tsc_smm time stamp counter counts during smm. 0: disable. 1: enable. (default) 3:2 rsvd reserved. write as read. 1isninv ignore snoop invalidate. allow the cpu core to ignore the invalidate bit in the gliu snoop packet. when a snoop hits to a dirty cache line it is evicted, regardless of the state of the invalidate bit in the gliu packet. 0: process snoop packet. 1: ignore snoop packet. (default) 0snoop instruction memory (im) to data memory (dm) snooping. allow code fetch snoops from the im to the dm cache. 0: disable. 1: enable. (default) msr address 00001901h ty p e r / w reset value 00000000_00000000h bc_config0_msr bit descriptions (continued) bit name description
amd geode? lx processors data book 185 cpu core register descriptions 33234h 5.5.2.91 reserved status msr (rsvd_sts_msr) 5.5.2.92 msr lock msr (msr_lock_msr) msr address 00001904h ty p e r o reset value 00000000_00000000h rsvd_sts_msr bit descriptions bit name description 63:0 rsvd (ro) reserved (read only). reads back as 0. msr address 00001908h ty p e r / w reset value 00000000_00000000h msr_lock_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd msr_lock msr_lock_msr bit descriptions bit name description 63:1 rsvd reserved. write as read 0 msr_lock lock msrs. the cpu core msrs above 0xfff ( with the exception of the msr_lock register itself) are locked when this bit read s back as 1. to unlock these msrs, write the value 45524f434c494156h to this register. writing any other value locks the msrs. the lock only affects software access via the wrmsr and rdmsr instructions when the processor is not in smm or dmm mode. msrs are always writable and readable from the glbus and when the processor is in s mm or dmm mode regardless of the state of the lock bit. note that a write or read to a locked msr register causes a protection exception in the pipeline. when msrs are locked, no glbus msr transactions are generated (glbus msr addresses are above 3fffh).
186 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.93 real time stamp counter msr (rtsc_msr) 5.5.2.94 tsc and rtsc low dwords msr (rtsc_tsc_msr) msr address 00001910h ty p e r / w reset value 00000000_00000000h rtsc_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rtsc (high dword) 313029282726252423222120191817161514131211109876543210 rtsc (low dword) rtsc_msr bit descriptions bit name description 63:0 rtsc real time stamp counter. this register is the 64-bit secondary, or ?real? time stamp counter. this counter allows software to configure the tsc not to include smm or dmm time, and still have an accurate real ti me measurement that includes these times. bc_config0_msr (msr 00001900h) contains c onfiguration bits that determine if the rtsc counts during suspend mode. it always counts during smm and dmm modes. all bits in this register are writable, un like the tsc that clears the upper dword to 0 on writes. msr address 00001911h ty p e r o reset value 00000000_00000000h rtsc_tsc_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rtsc_low 313029282726252423222120191817161514131211109876543210 tsc_low rtsc_tsc_msr bit descriptions bit name description 63:32 rtsc_low real time stamp counter low dword. this field provides a synchronized snapshot of the low dword of the rtsc register (msr 00001910h). 31:0 tsc_low time stamp counter low dword. this field provides a synchronized snapshot of the low dword of the tsc register (msr 00000010h).
amd geode? lx processors data book 187 cpu core register descriptions 33234h 5.5.2.95 l2 cache configur ation msr (l2_config_msr) l2_config_msr controls the behavior of the l2 cache. msr address 00001920h ty p e r / w reset value 00000000_0000000eh l2_config_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd l2_im_lock l2_dm_lock rsvd l2_tag_clkgt_en l2_pass_iomsr l2_dmevct_dirty l2_wait_dm_wr l2_invalid l2_im_alloc_en l2_dm_alloc_en l2_alloc_en l2_en l2_config_msr bit descriptions bit name description 63:24 rsvd reserved. 23:20 l2_im_lock l2 instruction memo ry subsystem lock. on allocations from the im, avoid using the ways that have the corresponding bits set to 1. (default = 0) 19:16 l2_dm_lock l2 cache data memory subsystem lock. on allocations from the dm, avoid using the ways that have the corresponding bits set to 1. (default = 0) 15:9 rsvd reserved. 8 l2_tag_ clkgt_en l2 cache tag clock gating enable. if set, the l2 tags would be clocked only when accessed. otherwise, the tags would be clo cked whenever the bus controller clocks are active. (default = 0) 7 l2_pass_ iomsr l2 cache (always) pass i/os and msrs. reserved for debug only. pass i/os and msrs through regardless of the state of the l2. (default = 0) 6 l2_dmevct_ dirty l2 cache data memory subsyste m evictions (always) dirty. reserved for debug only. treats all dm evictions as dirty. (default = 0) 5 l2_wait_dm_ wr l2 cache wait for data memory subsystem writes. reserved for debug only. waits for all data beats from dm before proceeding. (default = 0) 4 l2_invalid l2 cache invalidate. invalidate the entire contents of the l2 cache. this bit always reads back as 0. (default = 0) 3 l2_im_alloc_ en l2 cache instruction memory subsystem allocation enable. a new im access is allocated into the l2 cache only if this bit is on. (default = 1) 2 l2_dm_alloc _en l2 cache data memory subs ystem allocation enable. a new dm access is allocated into the l2 cache only if this bit is on. (default = 1) 1 l2_alloc_en l2 cache allocation enable. a new line is allocated into the l2 cache only if this bit is on (default = 1) 0 l2_en l2 cache enable. if this bit is on, the arbiter redirects memory accesses to the l2 block. (default = 0)
188 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.96 l2 cache status msr (l2_status_msr) l2_status_msr returns the status of the l2 cache controller. 5.5.2.97 l2 cache inde x msr (l2_index_msr) l2_index_msr has the l2 cache index, the way and the data qword select for diagnostic accesses. msr address 00001921h ty p e r o reset value 00000000_00000001h l2_status_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd l2_idle l2_status_msr bit descriptions bit name description 63:1 rsvd reserved. 0 l2_idle l2 cache idle. returns 1 if the l2 cache controller is idle. (default = 1) msr address 00001922h ty p e r / w reset value 00000000_00000000h l2_index_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd l2_dsel rsvd l2_index rsvd l2_way l2_index_msr bit descriptions bit name description 63:18 rsvd reserved. (default = 0) 17:16 l2_dsel l2 cache data qword select. (default = 0) 15 rsvd reserved. (default = 0) 14:5 l2_index l2 cache index for diagnostics accesses. (default = 0) 4:2 rsvd reserved. (default = 0) 1:0 l2_way l2 cache way selected for diagnostics accesses. (default = 0)
amd geode? lx processors data book 189 cpu core register descriptions 33234h 5.5.2.98 l2 cache data msr (l2_data_msr) l2_data_msr is used to access the l2 cache data for diagnostic accesses. 5.5.2.99 l2 cache tag msr (l2_tag_msr) l2_tag_msr has the l2 cache tag, mru and valid bits for diagnostic accesses. msr address 00001923h ty p e r / w reset value 00000000_00000000h l2_data_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 l2_data (high dword) 313029282726252423222120191817161514131211109876543210 l2_data (low dword) l2_data_msr bit descriptions bit name description 63:0 l2_data l2 cache array data. (default = 0) msr address 00001924h ty p e r / w reset value 00000000_00000000h l2_tag_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 l2_tag rsvd l2_mru_2 l2_mru_1 l2_mru_0 rsvd l2_valid l2_tag_msr bit descriptions bit name description 63:32 rsvd reserved. (default = 0) 31:15 l2_tag l2 cache tag. tag entry of the current way. (default = 0) 14:7 rsvd reserved. (default = 0) 6 l2_mru_2 l2 cache 2 most recently used. mru bit for the current index. if equal to 1, ways 3-2 more recent than ways 1-0. (default = 0) 5 l2_mru_1 l2 cache 1 most recently used. mru bit for the current index. if equal to 1, way 3 more recent than way 2. (default = 0) 4 l2_mru_0 l2 cache 0 most recently used. mru bit for the current index. if equal to 1, way 1 more recent than way 0. (default = 0) 3:1 rsvd reserved. (default = 0) 0 l2_valid l2 cache valid. valid bit for the current way. 0: invalid. (default) 1: valid.
190 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.100 l2 cache tag with increment msr (l2_tag_i_msr) the l2_tag_i_msr has the auto incremented l2 cache tag, mru and valid bits for diagnostic accesses. bit descriptions for this register are the same as for l 2_tag_msr (msr 00001924h), except read/write of this register causes an auto increment on the l2_index_msr (msr 00001922h). 5.5.2.101 l2 cache built-in self-test msr (l2_bist_msr) l2_bist_msr has the l2 cache index for diagnostic accesses. msr address 00001925h ty p e r / w reset value 00000000_00000000h l2_tag_i_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 l2_tag rsvd l2_mru rsvd l2_valid msr address 00001926h ty p e r / w reset value 00000000_00000000h l2_bist_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd bist_mru_go bist_data_cmp_stat bist_data_go bist_tag_go_cmp bist_tag_go_way3 bist_tag_go_way2 bist_tag_go_way1 bist_tag_go_way0 bist_tag_go bist_mru_drt_en bist_mru_en bist_data_drt_en bist_data_en bist_tag_drt_en bist_tag_en l2_bist_msr bit descriptions bit name description 63:30 rsvd (ro) reserved (read only). (default = 0) 29 bist_mru_go (ro) l2 cache most recently used bist result (read only). 0: fail. (default) 1: pass. 28:13 bist_data_ cmp_stat (ro) l2 cache data bist result (read only). one for each passed comparator - 16 total. (default = 0) 12 bist_data_go (ro) l2 cache data bist result (read only). 0: fail. (default) 1: pass. 11 bist_tag_go_ cmp (ro) l2 cache tag comparator bist result (read only). 0: fail. (default) 1: pass.
amd geode? lx processors data book 191 cpu core register descriptions 33234h 10 bist_tag_go_ way3 (ro) l2 cache tag bist way 3 result (read only). 0: fail. (default) 1: pass. 9 bist_tag_go_ way2 (ro) l2 cache tag bist way 2 result (read only). 0: fail. (default) 1: pass. 8 bist_tag_go_ way1 (ro) l2 cache tag bist way 1 result (read only). 0: fail. (default) 1: pass. 7 bist_tag_go_ way0 (ro) l2 cache tag bist way 0 result (read only). 0: fail. (default) 1: pass. 6 bist_tag_go (ro) l2 cache tag bist result (read only). 0: fail. (default) 1: pass. 5 bist_mru_drt_ en l2 cache most recently used data retention timer bist enable. enable the data retention timer for the mru bist. 0: disable. (default) 1: enable 4bist_mru_en l2 cache most recently used bist enable. start mru bist (on a write). 0: disable. (default) 1: enable 3bist_data_ drt_en l2 cache data retention timer bist enable. enable data retention timer for the data bist. 0: disable. (default) 1: enable 2bist_data_en l2 cache data bist enable. start data bist (on a write). 0: don?t start bist. (default) 1: start bist 1bist_tag_ drt_en l2 cache tag data retention timer bist enable. enable data retention timer for the tag bist. 0: disable. (default) 1: enable 0bist_tag_en l2 cache tag bist enable. start tag bist (on a write). 0: don?t start bist. (default) 1: start bist l2_bist_msr bit descriptions (continued) bit name description
192 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.102 l2 cache treatment co ntrol msr (l2_trtmnt_ctl_msr) msr address 00001927h ty p e r / w reset value 00000000_00000000h l2_trtmnt_ctl_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd tag_st_rst_code rsvd imevct_inval_code rsvd l2_inval_code rsvd tag_st_rst_en imevct_inval_en l2_inval_en l2_trtmnt_ctl_msr bit descriptions bit name description 63:19 rsvd reserved. 18:16 tag_st_rst_ code l2 cache tag state machine reset code. if tag_st_rst_ena (bit 2) is set, the code on the treatment bus forces the tag st ate machine to reset. (caution: extremely destructive - use only to poke around on hard hangs.) (default = 0) 15 rsvd reserved. 14:12 imevct_inval _code instruction memory subsystem eviction invalidate code. if imevct_inval_ena (bit 1) is set, the code on the treatment bus forces invalidation of the im eviction buffer. (default = 0) 11 rsvd reserved. 10:8 l2_inval_ code l2 cache invalidate code. if l2_inval_ena (bit 0) is set, the code on the treatment bus forces invalidation of the l2 cache. (default = 0) 7:3 rsvd reserved. 2tag_st_rst_ en l2 cache tag state machine reset enable. allows tag state machine reset through the treatment bus. 0: disable. (default) 1: enable. 1 imevct_inval _en instruction memory subsystem eviction invalidate enable. allows im eviction buffer invalidation through the treatment bus. 0: disable. (default) 1: enable. 0 l2_inval_en l2 cache invalidate enable. allows l2 cache invalidation through the treatment bus. 0: disable. (default) 1: enable.
amd geode? lx processors data book 193 cpu core register descriptions 33234h 5.5.2.103 power mode msr (pmode_msr) this msr enables some modules to turn their clocks off when they are idle to save power. most of these bits are off by default. it is recommended that they be set by bios. msr address 00001930h ty p e r / w reset value 00000000_00000300h pmode_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd irs_if irs_imtag irs_imdata rsvd fpu_ex fpu_fp rsvd bcl2_msr bcl2_gated pmode_msr bit descriptions bit name description 63:19 rsvd reserved. 18 irs_if reserved, instruction fetch. reserved for possible futu re clock gating of if. (default = 0) 17 irs_imtag reserved, instruction memory subsystem. reserved for possible future clock gating im tag. (default = 0) 16 irs_imdata instruction memory subsystem data. when bit is set, im may turn off the clock when im_data is idle. (default = 0) 9fpu_ex fpu ex. when bit is set, fpu may turn off the clock to fpu region 1 when fp_ex is idle. (default = 1) 8fpu_fp fpu_fp. when bit is set, fpu may turn off the clock to fpu region 2 when fpu is idle. (default = 1) 1 bcl2_msr bcl2 msr. when bit is set, bcl2 may turn off the clock to bc region 1 when bcl2_msr is idle. (default = 0) 0 bcl2_gated bcl2 gated. when bit is set, bcl2 may turn off the clock to bc region 2 when bcl2 is idle. (default = 0)
194 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.104 bus controller extended debug registers 1 and 0 msr (bxdr1_bxdr0_msr) 5.5.2.105 bus controller extended debug registers 3 and 2 msr (bxdr3_bxdr2_msr) msr address 00001950h ty p e r / w reset value 00000000_00000000h bxdr1_bxdr0_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 bxdr1_phys_addr 313029282726252423222120191817161514131211109876543210 bxdr0_phys_addr bxdr1_bxdr0_msr bit descriptions bit name description 63:32 bxdr1_phys_ addr address match value for bxdr1. this field specifies addresses that must match the physical address currently in the bus controller in order to trigger the extended break- point. (default = 0) 31:0 bxdr0_phys_ addr address match value for bxdr0. this field specifies addresses that must match the physical address currently in the bus controller in order to trigger the extended break- point. (default = 0) msr address 00001951h ty p e r / w reset value 00000000_00000000h bxdr3_bxdr2_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 bxdr3_phys_addr 313029282726252423222120191817161514131211109876543210 bxdr2_phys_addr bxdr3_bxdr2_msr bit descriptions bit name description 63:32 bxdr3_phys_ addr address match value for bxdr3. this field specifies addresses that must match the physical address currently in the bus controller in order to trigger the extended break- point. (default = 0) 31:0 bxdr2_phys_ addr address match value for bxdr2. this field specifies addresses that must match the physical address currently in the bus controller in order to trigger the extended break- point. (default = 0)
amd geode? lx processors data book 195 cpu core register descriptions 33234h 5.5.2.106 bus controller extended debug registers 6 and 7 msr (bxdr6_bxdr7_msr) bxdr6 (bits [31:0]) contains the status of the extended bus controller breakpoints. when a breakpoint occurs, the corre- sponding status bit is set in this register. the st atus bits remain set until cleared by an msr write. bxdr7 (bits [63:32]) is used to enable and specify the type of bxdr0-bxdr3. bxdr7 is also used to specify the length of the breakpoint. for example, if bxdr0 is set to 00000006h, and bxdr7 indicates it has a length of 2 bytes, then an access to 00000006h or 00000007h triggers the breakpoint. bxdr0 and bxdr1 can be paired to specify a range breakpoint if the len0 or len1 field of bxdr7 is set accordingly. bxdr2 and bxdr3 can be paired to specify a range breakpoint if the len2 or len3 field of bxdr7 is set accordingly. msr address 00001953h ty p e r / w reset value 00000000_00000000h bxdr6_bxdr7_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 type3 type2 type1 type0 len3 len2 len1 len0 rsvd e3 e2 e1 e0 313029282726252423222120191817161514131211109876543210 rsvd t3 t2 t1 t0 bxdr6_bxdr7_msr bit descriptions bit name description bxdr7 63:60 type3 extended breakpoint 3 type. selects the type of extended breakpoint 3. 0000: im memory read (default) 0001: dm memory read 0010: dm memory write 0011: dm memory read/write 0100: dm i/o read 0101: dm i/o write 0110: dm i/o read/write 0111: glbus snoop for read 1000: glbus snoop for write 1001: glbus snoop for write-invalidate 1010: msr read 1011: msr write all others: undefined, breakpoint will not trigger 59:56 type2 extended breakpoint 2 type. selects the type of extended breakpoint 2. see type3 (bits [63:60]) for decode. 55:52 type1 extended breakpoint 1 type. selects the type of extended breakpoint 1. see type3 (bits [63:60]) for decode. 51:48 type0 extended breakpoint 0 type. selects the type of extended breakpoint 0. see type3 (bits [63:60]) for decode. 47:46 len3 extended breakpoint 3 length. selects the size of extended breakpoint 3. 00: 1 byte. (default) 01: 2 bytes. 10: range from even to odd register. 11: 4 bytes. 45:44 len2 extended breakpoint 2 length. selects the size of extende d breakpoint 2. see len3 (bits [47:46]) for decode. 43:42 len1 extended breakpoint 1 length. selects the size of extende d breakpoint 0. see len3 (bits [47:46]) for decode.
196 amd geode? lx processors data book cpu core register descriptions 33234h 41:40 len0 extended breakpoint 0 length. selects the size of extende d breakpoint 1. see len3 (bits [47:46]) for decode. 35 e3 extended breakpoint 3 enable. allows extended breakpoint 3 to be enabled. 0: disable. 1: enable. 34 e2 extended breakpoint 2 enable. allows extended breakpoint 2 to be enabled. 0: disable. 1: enable. 33 e1 extended breakpoint 1 enable. allows extended breakpoint 1 to be enabled. 0: disable. 1: enable. 32 e0 extended breakpoint 0 enable. allows extended breakpoint 0 to be enabled. 0: disable. 1: enable. bxdr6 31:4 rsvd reserved. 3t3 extended breakpoint 3 triggered. a 1 indicates that extended breakpoint 3 has trig- gered. write to clear. (default = 0) 2t2 extended breakpoint 2 triggered. a 1 indicates that extended breakpoint 2 has trig- gered. write to clear. (default = 0) 1t1 extended breakpoint 1 triggered. a 1 indicates that extended breakpoint 1 has trig- gered. write to clear. (default = 0) 0t0 extended breakpoint 0 triggered. a 1 indicates that extended breakpoint 0 has trig- gered. write to clear. (default = 0) bxdr6_bxdr7_msr bit desc riptions (continued) bit name description
amd geode? lx processors data book 197 cpu core register descriptions 33234h 5.5.2.107 bus controller debug registers 0 through 3 msrs each of these registers specifies an address that must match the physical address curr ently in the bus controller in order to trigger the breakpoint. bdr7 is used to enable and specify th e type of bdr0-bdr3. if a breakpoint is configured as a mem- ory breakpoint, the address is matched on a qword granularity. if a breakpoint is configured as an i/o or msr breakpoint, the address is matched based on all 32 bits. bus controller debug register 0 msr (bdr0_msr) bus controller debug register 1 msr (bdr1_msr) bus controller debug register 2 msr (bdr2_msr) bus controller debug register 3 msr (bdr3_msr) msr address 00001970h ty p e r / w reset value 00000000_00000000h msr address 00001971h ty p e r / w reset value 00000000_00000000h msr address 00001972h ty p e r / w reset value 00000000_00000000h msr address 00001973h ty p e r / w reset value 00000000_00000000h bdrx_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 phys_addr bdrx_msr bit descriptions bit name description 63:32 rsvd reserved. (default = 0) 31:0 phys_addr address match value for bdrx. (default = 0)
198 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.108 bus controller debug register 6 msr (bdr6_msr) this register contains the stat us of the bus controller breakpoints. when a breakpoint occurs, the corresponding status bit is set in this register. the status bits remain set until cleared by an msr write. 5.5.2.109 bus controller debug register 7 msr (bdr7_msr) this register is the bus controller breakpoint control/enable register. msr address 00001976h ty p e r / w reset value 00000000_00000000h bdr6_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd t3 t2 t1 t0 bdr6_msr bit descriptions bit name description 63:4 rsvd reserved. (default = 0) 3t3 breakpoint 3 triggered. a 1 indicates that breakpoint 3 has triggered. write to clear. (default = 0) 2t2 breakpoint 2 triggered. a 1 indicates that breakpoint 2 has triggered. write to clear. (default = 0) 1t1 breakpoint 1 triggered. a 1 indicates that breakpoint 1 has triggered. write to clear. (default = 0) 0t0 breakpoint 0 triggered. a 1 indicates that breakpoint 0 has triggered. write to clear. (default = 0) msr address 00001977h ty p e r / w reset value 00000000_00000000h bdr7_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 type3 type2 type1 type0 rsvd e3 e2 e1 e0 bdr7_msr bit descriptions bit name description 63:32 rsvd reserved. (default = 0)
amd geode? lx processors data book 199 cpu core register descriptions 33234h 31:28 type3 breakpoint 3 type. selects the type of extended breakpoint 3. 0000: im memory read (default). 0001: dm memory read. 0010: dm memory write. 0011: dm memory read/write. 0100: dm i/o read. 0101: dm i/o write. 0110: dm i/o read/write. 0111: glbus snoop for read. 1000: glbus snoop for write. 1001: glbus snoop for write-invalidate. 1010: msr read. 1011: msr write. all others: undefined, breakpoint will not trigger. 27:24 type2 breakpoint 2 type. selects the type of extended brea kpoint 2. see t ype3 (bits [31:28]) for decode. 23:20 type1 breakpoint 1 type. selects the type of extended brea kpoint 1. see t ype3 (bits [31:28]) for decode. 19:16 type0 breakpoint 0 type. selects the type of extended brea kpoint 0. see t ype3 (bits [31:28]) for decode. 15:4 rsvd reserved. (default = 0) 3e3 breakpoint 3 enable. allows extended breakpoint 3 to be enabled. 0: disable. 1: enable. 2e2 breakpoint 2 enable. allows extended breakpoint 2 to be enabled. 0: disable. 1: enable. 1e1 breakpoint 1 enable. allows extended breakpoint 1 to be enabled. 0: disable. 1: enable. 0e0 breakpoint 0 enable. allows extended breakpoint 0 to be enabled. 0: disable. 1: enable. bdr7_msr bit descriptions bit name description
200 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.110 memory subsystem array control enable msr (mss_array_ctl_en_msr) the msrs at addresses 00001980h-00001983h provide alternate array delay control values for the mss arrays. after a reset, the mss clock modules provide jtag -accessible control values. these msrs can be used by software to override these values. 5.5.2.111 memory subsyst em array control 0 msr (mss_array_ctl0_msr) msr address 00001980h ty p e r / w reset value 00000000_00000000h mss_array_ctl_en_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd en mss_array_ctl_en_msr bit descriptions bit name description 63:1 rsvd reserved. (default = 0) 0en enable. enable the array control values in this register to be used instead of those pro- vided by the clock modules. 0: disable. 1: enable. msr address 00001981h ty p e r / w reset value 00000000_2010f3c9h mss_array_ctl0_ms r register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd dmdata1 313029282726252423222120191817161514131211109876543210 dmdata1 dmdata0 dmtag1 dmtag0 l2tlb1 l2tlb0 mss_array_ctl0_msr bit descriptions bit name description 63:36 rsvd reserved. (default = 0) 35:27 dmdata1 data memory subsystem data 1 delay control. (default = 04) 26:18 dmdata0 data memory subsystem data 0 delay control. (default = 04) 17:12 dmtag1 data memory subsystem tag 1 delay control. (default = f) 11:6 dmtag0 data memory subsystem tag 0 delay control. (default = f) 5:3 l2tb1 data memory subsystem l2 tlb 1 delay control. (default = 1) 2:0 l2tb0 data memory subsystem l2 tlb 0 delay control. (default = 1)
amd geode? lx processors data book 201 cpu core register descriptions 33234h 5.5.2.112 memory subsyst em array control 1 msr (mss_array_ctl1_msr) 5.5.2.113 memory subsyst em array control 2 msr (mss_array_ctl2_msr) l2 delay control settings. msr address 00001982h ty p e r / w reset value 00000000_104823cfh mss_array_ctl1_ms r register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd imdata1 imdata0 imtag1 imtag0 mss_array_ctl1_msr bit descriptions bit name description 63:30 rsvd reserved. (default = 0) 29:21 imdata1 instruction memory subsystem data 1 delay control. (default = 82) 20:12 imdata0 instruction memory subsystem data 0 delay control. (default = 82) 11:6 imtag1 instruction memory subsystem tag 1 delay control. (default = f) 5:0 imtag0 instruction memory subsystem tag 0 delay control. (default = f) msr address 00001983h ty p e r / w reset value 00000104_820c30c3h mss_array_ctl2_ms r register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd l2data1 l2data0 313029282726252423222120191817161514131211109876543210 l2data0 l2tag3 l2tag2 l2tag1 l2tag0 mss_array_ctl2_msr bit descriptions bit name description 63:42 rsvd reserved. (default = 0) 41:33 l2data1 l2 cache data 1 delay setting. (default = 82) 32:24 l2data0 l2 cache data 0 delay setting. (default = 82) 23:18 l2tag3 l2 cache tag 3 delay setting. (default = 3) 17:12 l2tag2 l2 cache tag 2 delay setting. (default = 3) 11:6 l2tag1 l2 cache tag 1 delay setting. (default = 3) 5:0 l2tag0 l2 cache tag 0 delay setting. (default = 3)
202 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.114 fpu modes msr (fp_mode_msr) 5.5.2.115 fpu reserved msr (fpu_rsvd_msr) this register is reserved for internal testing; do not write. 5.5.2.116 fpu reserved msr (fpu_rsvd_msr) this register is reserved for internal testing; do not write. msr address 00001a00h ty p e r / w reset value 00000000_00000000h fp_mode_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd fpu_sp fpu_ipe fp_mode_msr bit descriptions bit name description 63:2 rsvd reserved. write as read. 1fpu_sp limit results to single precision. the fpu datapath width is single-precision. opera- tions on single precision numbers can generally be completed in one cycle, but double or extended precision numbers takes many cycles. this bit overrides the precision control bits in the x87 mode control register (of t he fpu instruction set), and causes the fpu to operate as if the precision control is set to single precision (00). 0: disable. 1: enable limit to single precision. 0 fpu_ipe enable force of imprecise exceptions. for precise exceptions, the fpu allows only one instruction to be in the pipeline at a time when any fpu exceptions are unmasked. this results in a huge performance penalty. to run the fpu at full speed, it is necessary to mask all exceptions in the fpu_cw_msr (msr 00001a10h[11:0]). when this bit is set, the fpu is allowed to run at full speed even if there are unmasked exceptions in the fpu_cw. with this bit set, exceptions will be generated, however, there is no guarantee that the exception will occur on any particular instruction boundary. it is known that setting this bit will cause so me diagnostic software to fail. it is recom- mended to be set only when the fpu except ion handler does not need to handle excep- tions on the specific instruction boundary. 0: disable. 1: enable. msr address 00001a01h ty p e r / w reset value 00000000_00000000h msr address 00001a03h ty p e r / w reset value 00000000_00000000h
amd geode? lx processors data book 203 cpu core register descriptions 33234h 5.5.2.117 fpu x87 control word msr (fpu_cw_msr) 5.5.2.118 fpu x87 status word msr (fpu_sw_msr) 5.5.2.119 fpu x87 tag word msr (fpu_tw_msr) msr address 00001a10h ty p e r / w reset value 00000000_00000040h fpu_cw_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd fpu_cw fpu_cw_msr bit descriptions bit name description 63:12 rsvd reserved. write as read. 11:0 fpu_cw fpu control word. msr address 00001a11h ty p e r / w reset value 00000000_00000000h fpu_sw_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd fpu_sw fpu_sw_msr bit descriptions bit name description 63:16 rsvd reserved. write as read. 15:0 fpu_sw fpu status word. msr address 00001a12h ty p e r / w reset value 00000000_00000000h fpu_tw_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd fpu_tw
204 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.120 fpu busy ms r (fpu_busy_msr) 5.5.2.121 fpu register map msr (fpu_map_msr) fpu_tw_msr bit descriptions bit name description 63:16 rsvd reserved. write as read. 15:0 fpu_tw fpu tag word. msr address 00001a13h ty p e r o reset value 00000000_00000000h fpu_busy_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd fpu_busy fpu_busy_msr bit descriptions bit name description 63:1 rsvd reserved. reads back as 0. 0fpu_busy fpu busy. software must check that the fpu is idle before accessing msrs 00001a10h-00001a12h and 00001a40h-00001a6fh. 0: fpu idle. 1: fpu busy. msr address 00001a14h ty p e r o reset value 00000000_76543210h fpu_map_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 fpu_reg_map fpu_map_msr bit descriptions bit name description 63:32 rsvd reserved. 31:0 fpu_reg_map fpu register map. internal mapping of architectural registers to physical registers in the register array.
amd geode? lx processors data book 205 cpu core register descriptions 33234h 5.5.2.122 mantissa of rx msrs mantissa of r0 msr (fpu_mr0_msr) mantissa of r1 msr (fpu_mr1_msr) mantissa of r2 msr (fpu_mr2_msr) mantissa of r3 msr (fpu_mr3_msr) mantissa of r4 msr (fpu_mr4_msr) mantissa of r5 msr (fpu_mr5_msr) mantissa of r6 msr (fpu_mr6_msr) mantissa of r7 msr (fpu_mr7_msr) mantissa of r8 msr (fpu_mr8_msr) mantissa of r9 msr (fpu_mr9_msr) mantissa of r10 msr (fpu_mr10_msr) mantissa of r11 msr (fpu_mr11_msr) mantissa of r12 msr (fpu_mr12_msr) mantissa of r13 msr (fpu_mr13_msr) mantissa of r14 msr (fpu_mr14_msr) mantissa of r15 msr (fpu_mr15_msr) msr address 00001a40h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a42h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a44h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a46h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a48h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a4ah ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a4ch ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a4eh ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a50h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a52h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a54h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a56h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a58h ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a5ah ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a5ch ty p e r / w reset value xxxxxxxx_xxxxxxxxh msr address 00001a5eh ty p e r / w reset value xxxxxxxx_xxxxxxxxh fpu_mrx_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 fpu_mrx 313029282726252423222120191817161514131211109876543210 fpu_mrx fpu_mrx_msr bit descriptions bit name description 63:0 fpu_mrx mantissa of fpu rx msr.
206 amd geode? lx processors data book cpu core register descriptions 33234h 5.5.2.123 exponent of rx msrs exponent of r0 msr (fpu_er0_msr) exponent of r1 msr (fpu_er1_msr) exponent of r2 msr (fpu_er2_msr) exponent of r3 msr (fpu_er3_msr) exponent of r4 msr (fpu_er4_msr) exponent of r5 msr (fpu_er5_msr) exponent of r6 msr (fpu_er6_msr) exponent of r7 msr (fpu_er7_msr) exponent of r8 msr (fpu_er8_msr) exponent of r9 msr (fpu_er9_msr) exponent of r10 msr (fpu_er10_msr) exponent of r11 msr (fpu_er11_msr) exponent of r12 msr (fpu_er12_msr) exponent of r13 msr (fpu_er13_msr) exponent of r14 msr (fpu_er14_msr) exponent of r15 msr (fpu_er15_msr) msr address 00001a41h ty p e r / w reset value 00000000_0000xxxxh msr address 00001a43h ty p e r / w reset value 00000000_0000xxxxh msr address 00001a45h ty p e r / w reset value 00000000_0000xxxxh msr address 00001a47h ty p e r / w reset value 00000000_0000xxxxh msr address 00001a49h ty p e r / w reset value 00000000_0000xxxxh msr address 00001a4bh ty p e r / w reset value 00000000_0000xxxxh msr address 00001a4dh ty p e r / w reset value 00000000_0000xxxxh msr address 00001a4fh ty p e r / w reset value 00000000_0000xxxxh msr address 00001a51h ty p e r / w reset value 00000000_0000xxxxh msr address 00001a53h ty p e r / w reset value 00000000_0000xxxxh msr address 00001a55h ty p e r / w reset value 00000000_0000xxxxh msr address 00001a57h ty p e r / w reset value 00000000_0000xxxxh msr address 00001a59h ty p e r / w reset value 00000000_0000xxxxh msr address 00001a5bh ty p e r / w reset value 00000000_0000xxxxh msr address 00001a5dh ty p e r / w reset value 00000000_0000xxxxh msr address 00001a5fh ty p e r / w reset value 00000000_0000xxxxh fpu_erx_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 fpu_erx fpu_erx_msr bit descriptions bit name description 63:16 rsvd reserved. write as read. 15:0 fpu_erx exponent of fpu rx msr.
amd geode? lx processors data book 207 cpu core register descriptions 33234h 5.5.2.124 fpu reserved msrs (fpu_rsvd_msr) msr addresses 00001a60h through 00001a6f are reserved for internal storage purposes and should not be written to. 5.5.2.125 cpu id msrs standard levels and vendor id string 1 (cpuid0_msr) vendor id strings 2 and 3 (cpuid1_msr) type/family/model/step (cpuid2_msr) feature flags (cpuid3_msr) reserved (cpuid4_msr) reserved (cpuid5_msr) max extended levels 1 (cpuid6_msr) max extended levels 2 (cpuid7_msr) extended type/family/mode l/stepping (cpuid8_msr) extended feature flags (cpuid9_msr) cpu marketing name 1 (cpuida_msr) cpu marketing name 2 (cpuidb_msr) cpu marketing name 3 (cpuidc_msr) cpu marketing name 4 (cpuidd_msr) cpu marketing name 5 (cpuide_msr) cpu marketing name 6 (cpuidf_msr) l1 tlb information (cpuid10_msr) l1 cache information (cpuid11_msr) l2 tlb information (cpuid12_msr) l2 cache information (cpuid13_msr) msr address 00003000h ty p e r / w reset value 68747541_00000001h msr address 00003001h ty p e r / w reset value 69746e65_444d4163h msr address 00003002h ty p e r / w reset value 00000400_000005a2h msr address 00003003h ty p e r / w reset value 0088a93d_00000000h msr address 00003004h ty p e w o reset value 00000000_00000000h msr address 00003005h ty p e w o reset value 00000000_00000000h msr address 00003006h ty p e r / w reset value 68747541_80000006h msr address 00003007h ty p e r / w reset value 69746e65_444d4163h msr address 00003008h ty p e r / w reset value 00000000_000005a1h msr address 00003009h ty p e r / w reset value c0c0a13d_00000000h msr address 0000300ah ty p e r / w reset value 4d542865_646f6547h msr address 0000300bh ty p e r / w reset value 72676574_6e492029h msr address 0000300ch ty p e r / w reset value 6f725020_64657461h msr address 0000300dh ty p e r / w reset value 6220726f_73736563h msr address 0000300eh ty p e r / w reset value 43502044_4d412079h msr address 0000300fh ty p e r / w reset value 00000000_00000053h msr address 00003010h ty p e r / w reset value ff10ff10_00000000h msr address 00003011h ty p e r / w reset value 40100120_40100120h msr address 00003012h ty p e r / w reset value 00002040_0000f004h msr address 00003013h ty p e r / w reset value 00000000_00804120h
208 amd geode? lx processors data book cpu core register descriptions 33234h cpuidx_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 cpuidx 313029282726252423222120191817161514131211109876543210 cpuidx cpuidx_msr bit descriptions bit name description 63:0 cpuid0 standard levels and vendor id string 1. same data as cpuid instruction [00000000] ebx/eax. 63:0 cpuid1 vendor id strings 2 and 3. same data as cpuid instruction [00000000] edx/ecx. 63:0 cpuid2 type/family/model/step. same data as cpuid instruction [00000001] ebx/eax. 63:0 cpuid3 feature flags. same data as cpuid instruction [00000001] edx/ecx. 63:0 cpuid4 reserved. this register is not used in the cpu core module. 63:0 cpuid5 reserved. this register is not used in the cpu core module. 63:0 cpuid6 cpuid max extended levels. same data as cpuid instruction [80000000] ebx/eax. 63:0 cpuid7 cpuid max extended levels. same data as cpuid instruction [80000000] edx/ecx. 63:0 cpuid8 extended type/family/model/stepping. same data as cpuid instruction [80000001] ebx/eax. 63:0 cpuid9 extended feature flags. same data as cpuid instruction [80000001] edx/ecx. 63:0 cpuida cpu marketing name 1. same data as cpuid instru ction [80000002] ebx/eax. 63:0 cpuidb cpu marketing name 2. same data as cpuid instru ction [80000002] edx/ecx. 63:0 cpuidc cpu marketing name 3. same data as cpuid instru ction [80000003] ebx/eax. 63:0 cpuidd cpu marketing name 4. same data as cpuid instru ction [80000003] edx/ecx. 63:0 cpuide cpu marketing name 5. same data as cpuid inst ruction [80000004] ebx/eax. 63:0 cpuidf cpu marketing name 6. same data as cpuid instru ction [80000004] edx/ecx. 63:0 cpuid10 l1 tlb information. same data as cpuid instruction [80000005] ebx/eax. 63:0 cpuid11 l1 cache information. same data as cpuid inst ruction [80000005] edx/ecx. 63:0 cpuid12 l2 tlb information. same data as cpuid instruction [80000006] ebx/eax. 63:0 cpuid13 l2 cache information. same data as cpuid inst ruction [80000006] edx/ecx.
amd geode? lx processors data book 209 6 integrated functions 33234h 6.0 integrated functions the integrated functions of the amd geode? lx proces- sor are: ? geodelink? memory controller (glmc) ? graphics processor (gp) ? display controller (dc) ? video processor (vp) ? geodelink control processor (glcp) ? geodelink pci bridge (glpci) ? video input port (vip) ? security block (sb) this section provides a functional description of each mod- ule and its respective registers. figure 6-1. integrated functions block diagram geodelink? interface unit 0 geodelink? interface unit 1 geodelink? control diagnostic te s t power mgmnt geodelink? sdclks tlb integer unit mmu load/store fpu 64 kb l1 d-cache 64 kb l1 i-cache bus controller cpu core alpha compositing rop unit blt engine graphics processor (gp) timing palette ram compression buffer display controller (dc) alpha blender video mixer video scalar video processor (vp) rgb yuv graphics filter/scaling (gliu0) (gliu1) memory clock module cpu pll system pll tft/vop 3x8-bit dac crt pci sysref dotref test/reset interface processor (glcp) controller (glmc) dotclk pll 128 kb l2 cache 1 kb lut rotation blt companion i/f vip hw vga 128-bit aes tft controller/ video output port (vop) amd geode? companion device 64-bit ddr security block random number generator eeprom on package 64-bit ddr sdram (cbc/ecb) tr u e (optional) geodelink? pci bridge (glpci) video input port (vip) (sb)
210 amd geode? lx processors data book geodelink? memory controller 33234h 6.1 geodelink? memory controller the geodelink? memory controller (glmc) module sup- ports the unified memory ar chitecture (uma) of the amd geode? lx processor and controls a 64-bit ddr sdram interface without any external buffering. the inter- nal block diagram of the glmc is shown in figure 6-2. the sdram memory array contains both the main system memory and the graphics frame buffer. up to four module banks of sdram are supported. each module bank can have two or four component banks depending on the mem- ory size and organization. the maximum configuration is four module banks with four component banks, each pro- viding a total of 16 open banks with the maximum memory size supported being 2 gb. the glmc handles multiple requests for memory data from the cpu core, the graphics processor, the display controller, and the external pci bus via the geodelink interface units (glius). the glmc contains extensive buffering logic that helps minimize contention for memory bandwidth between the various requests. figure 6-2. glmc block diagram adrs/ctl gen req req refresh arbiter data control sdram if msr registers w_data write response msr rd resp data path ras cas we cke ma ba cs dq dqm dqs bank/ page logic buf buf r_data memrd response glui0 request packet glui0 write packet glui0 response packet write buf write buf write buf capture/ resync
amd geode? lx processors data book 211 geodelink? memory controller 33234h features ? supports up to 400 mt/s (million transfers per second) ddr sdrams ? supports 64-bit data interface ? supports unbuffered dimms and sodimms ? can maintain up to 16 open banks at a time ? can support up to three outstanding requests at a time ? arbiter reorders requests fr om different sources to opti- mize data bus utilization ? single and burst data phase optimization ? programmable modes of high and low order address interleaving ? queues up to eight refreshes ? supports low power mode ? highly configurable to obtain best performance for installed dram 6.1.1 functional hardware 6.1.1.1 address translation the glmc module supports two address translations depending on the method used to interleave pages. the hardware supports high order interleaving (hoi) or low order interleaving (loi). select the interleaving mode used by programming the hoi_loi bit of the mc_cf8f_data register (msr 20000019h[33]. se e section 6.2.2.10 "tim- ing and mode program (mc_cf8f_data)" on page 229 for bit description. high order interleaving high order interleaving (hoi) uses the most significant address bits to select which bank the page is located in. figure 6-3 shows an example of how the geode lx pro- cessor?s internal physical addresses are connected to the memory interface address lines. this interleaving scheme works with any mixture of dimm types. however, it spreads the pages over wide address ranges. for example, assume a 64 mb memory subsystem with two 32 mb dimms installed. each dimm has a single module bank, and each module bank contains four compo- nent banks. this gives a total of eight component banks in this memory configuration. each page in a component bank is separated from the next component bank page by 8 mb. see figure 6-4. figure 6-3. hoi addressing example figure 6-4. hoi example aaaaaaaaaaaaaaaaaaaaaaaaaa 22222222211111111110000000 87654321098765432109876543 ba[1:0] mb[1] ra[9:0] ca[7:0] mb[0] ra[12:10] internal physical address ca are the cas addresses on ma[7:0] ra are the ras addresses on ma[12:0] module bank component banks bank 3 page 0 dimm0 dimm1 00000000h 00800000h 01000000h 01800000h 24m bank 2 page 0 16m bank 1 page 0 8m bank 0 page 0 0m module bank component banks bank 3 page 0 02000000h 02800000h 03000000h 03800000h 56m bank 2 page 0 48m bank 1 page 0 40m bank 0 page 0 32m
212 amd geode? lx processors data book geodelink? memory controller 33234h auto low order interleaving the glmc requires that module banks [0:1], if both installed, be identical and module banks [2:3], if both installed, be identical. st andard dimms and sodimms are configured this way. because of this requirement, when module banks [0:1] are installed or module banks [2:3] are installed, loi is in effect , when enabled for those bank pairs. if all four module banks [0:3] are identical, then loi is in effect across all four module banks. loi uses the least significant bits after the page bits to select which bank the page is located in. an example is shown in figure 6-5. as stated previously, for loi to be most effective, module banks [0:1] and module banks [2:3] must be of identical configuration. loi is least effective when only two module banks are installed and of different configuration. this can only happen when one of the module banks is installed in module bank [0 or 1] and the second module bank is installed in module bank [2 or 3]. loi has the advantage of creating an effective larger moving page throughout mem- ory. using an example of four identical module banks, with four component banks, and a 1 kb address (8 kb data) page, there would be an effective moving page of 64 kb of data (see figure 6-6). physical address to dram address conversion tables 6-1 and 6-2 on page 213 show auto loi address conversion examples when two dimms of the same size are used in a system. table 6-1 shows a one dimm bank conversion example, while table 6-2 shows a two dimm bank example. tables 6-3 and 6-4 on page 214 show non-auto loi address conversion examples when either one or two dimms of different sizes are used in a system. table 6-3 shows a one dimm bank address conversion example, while table 6-4 shows a two dimm bank example. the addresses are computed on a per dimm basis. since the dram interface is 64 bits wide, the lower three bits of the physical address get mapped onto the dqm[7:0] lines. thus, the address conversion tables (tables 6-1 through 6-4) show the physical address starting from a3. figure 6-5. loi addressing example figure 6-6. loi example aaaaaaaaaaaaaaaaaaaaaaaaaa 22222222211111111110000000 87654321098765432109876543 ra[12:0] mb[0] ba[1:0] ca[7:0] mb[1] internal physical address ca are the cas addresses on ma[7:0] ra are the ras addresses on ma[12:0] module bank 0 page 0 00000000h 00002000h 00004000h 00006000h component banks page 0 address page 0 address page 0 address page 0 address bank 1 page 0 bank 2 page 0 bank 0 bank 3 page 0 module bank 0 page 0 00008000h 0000a000h 0000c000h 0000e000h component banks page 0 address page 0 address page 0 address page 0 address bank 1 page 0 bank 2 page 0 bank 1 bank 3 page 0 module bank 0 page 0 00010000h 00012000h 00014000h 00016000h component banks page 0 address page 0 address page 0 address page 0 address bank 1 page 0 bank 2 page 0 bank 2 bank 3 page 0 module bank 0 page 0 00018000h 0001a000h 0001c000h 0001e000h component banks page 0 address page 0 address page 0 address page 0 address bank 1 page 0 bank 2 page 0 bank 3 bank 3 page 0
amd geode? lx processors data book 213 geodelink? memory controller 33234h table 6-1. loi - 2 dimms, same size, 1 dimm bank 1 kb page size 2 kb page size 4 kb page size 1 kb page size 2 kb page size 4 kb page size row col row col row col row col row col row col address 2 component banks 4 component banks ma13 a25 -- a26 -- a27 -- a26 -- a27 -- a28 -- ma12 a24 -- a25 -- a26 -- a25 -- a26 -- a27 -- ma11 a23 -- a24 -- a25 -- a24 -- a25 -- a26 -- ma10 a22 -- a23 -- a24 -- a23 -- a24 -- a25 -- ma9 a21 -- a22 -- a23 --- a22 -- a23 -- a24 -- ma8 a20 -- a21 -- a22 a11 a21 -- a22 -- a23 a11 ma7 a19 -- a20 a10 a21 a10 a20 -- a21 a10 a22 a10 ma6 a18 a9 a19 a9 a20 a9 a19 a9 a20 a9 a21 a9 ma5 a17 a8 a18 a8 a19 a8 a18 a8 a19 a8 a20 a8 ma4 a16 a7 a17 a7 a18 a7 a17 a7 a18 a7 a19 a7 ma3 a15 a6 a16 a6 a17 a6 a16 a6 a17 a6 a18 a6 ma2 a14 a5 a15 a5 a16 a5 a15 a5 a16 a5 a17 a5 ma1 a13 a4 a14 a4 a15 a4 a14 a4 a15 a4 a16 a4 ma0 a12 a3 a13 a3 a14 a3 a13 a3 a14 a3 a15 a3 cs0#/cs1# a11 a12 a13 a12 a13 a14 cs2#/cs3# -- -- -- -- -- -- ba0/ba1 a10 a11 a12 a11/a10 a12/a11 a13/a12 table 6-2. loi - 2 dimms, same size, 2 dimm banks 1 kb page size 2 kb page size 4 kb page size 1 kb page size 2 kb page size 4 kb page size row col row col row col row col row col row col address 2 component banks 4 component banks ma13 a26 -- a27 -- a28 -- a27 -- a28 -- a29 -- ma12 a25 -- a26 -- a27 -- a26 -- a27 -- a28 -- ma11 a24 -- a25 -- a26 -- a25 -- a26 -- a27 -- ma10 a23 -- a24 -- a25 -- a24 -- a25 -- a26 -- ma9 a22 -- a23 -- a24 -- a23 -- a24 -- a25 -- ma8 a21 -- a22 -- a23 a11 a22 -- a23 -- a24 a11 ma7 a20 -- a21 a10 a22 a10 a21 -- a22 a10 a23 a10 ma6 a19 a9 a20 a9 a21 a9 a20 a9 a21 a9 a22 a9 ma5 a18 a8 a19 a8 a20 a8 a19 a8 a20 a8 a21 a8 ma4 a17 a7 a18 a7 a19 a7 a18 a7 a19 a7 a20 a7 ma3 a16 a6 a17 a6 a18 a6 a17 a6 a18 a6 a19 a6 ma2 a15 a5 a16 a5 a17 a5 a16 a5 a17 a5 a18 a5 ma1 a14 a4 a15 a4 a16 a4 a15 a4 a16 a4 a17 a4 ma0 a13 a3 a14 a3 a15 a3 a14 a3 a15 a3 a16 a3 cs0#/cs1# a12 a13 a14 a13 a14 a15 cs2#/cs3# a11 a12 a13 a12 a13 a14 ba0/ba1 a10 a11 a12 a11/a10 a12/a11 a13/a12
214 amd geode? lx processors data book geodelink? memory controller 33234h table 6-3. non-auto loi - 1 or 2 dimms, different sizes, 1 dimm bank 1 kb page size 2 kb page size 4 kb page size 1 kb page size 2 kb page size 4 kb page size row col row col row col row col row col row col address 2 component banks 4 component banks ma13 a24 -- a25 -- a26 -- a25 -- a26 -- a27 -- ma12 a23 -- a24 -- a25 -- a24 -- a25 -- a26 -- ma11 a22 -- a23 -- a24 -- a23 -- a24 -- a25 -- ma10 a21 -- a22 -- a23 -- a22 -- a23 -- a24 -- ma9 a20 -- a21 -- a22 -- a21 -- a22 -- a23 -- ma8 a19 -- a20 -- a21 a11 a20 -- a21 -- a22 a11 ma7 a18 -- a19 a10 a20 a10 a19 -- a20 a10 a21 a10 ma6 a17 a9 a18 a9 a19 a9 a18 a9 a19 a9 a20 a9 ma5 a16 a8 a17 a8 a18 a8 a17 a8 a18 a8 a19 a8 ma4 a15 a7 a16 a7 a17 a7 a16 a7 a17 a7 a18 a7 ma3 a14 a6 a15 a6 a16 a6 a15 a6 a16 a6 a17 a6 ma2 a13 a5 a14 a5 a15 a5 a14 a5 a15 a5 a16 a5 ma1 a12 a4 a13 a4 a14 a4 a13 a4 a14 a4 a15 a4 ma0 a11 a3 a12 a3 a13 a3 a12 a3 a13 a3 a14 a3 cs0#/cs1#-- ---- ------ cs2#/cs3#-- ---- ------ ba0/ba1 a10 a11 a12 a11/a10 a12/a11 a13/a12 table 6-4. non-auto loi - 1 or 2 dimms, different sizes, 2 dimm banks 1 kb page size 2 kb page size 4 kb page size 1 kb page size 2 kb page size 4 kb page size row col row col row col row col row col row col address 2 component banks 4 component banks ma13 a25 -- a26 -- a27 -- a26 -- a27 -- a28 -- ma12 a24 -- a25 -- a26 -- a25 -- a26 -- a27 -- ma11 a23 -- a24 -- a25 -- a24 -- a25 -- a26 -- ma10 a22 -- a23 -- a24 -- a23 -- a24 -- a25 -- ma9 a21 -- a22 -- a23 -- a22 -- a23 -- a24 -- ma8 a20 -- a21 -- a22 a11 a21 -- a22 -- a23 a11 ma7 a19 -- a20 a10 a21 a10 a20 -- a21 a10 a22 a10 ma6 a18 a9 a19 a9 a20 a9 a19 a9 a20 a9 a21 a9 ma5 a17 a8 a18 a8 a19 a8 a18 a8 a19 a8 a20 a8 ma4 a16 a7 a17 a7 a18 a7 a17 a7 a18 a7 a19 a7 ma3 a15 a6 a16 a6 a17 a6 a16 a6 a17 a6 a18 a6 ma2 a14 a5 a15 a5 a16 a5 a15 a5 a16 a5 a17 a5 ma1 a13 a4 a14 a4 a15 a4 a14 a4 a15 a4 a16 a4 ma0 a12 a3 a13 a3 a14 a3 a13 a3 a14 a3 a15 a3 cs0#/cs1# a11 a12 a13 a12 a13 a14 cs2#/cs3# -- -- ba0/ba1 a10 a11 a12 a11/a10 a12/a11 a13/a12
amd geode? lx processors data book 215 geodelink? memory controller 33234h 6.1.1.2 arbitration the pipelining of the glmc module requests consists of the gliu0 interface request plus two request buffers: the c (closed) and o (open) slots (see figure 6-7). a request is accepted at the gliu0 interfac e as long as there is a slot available. the c slot holds a request to a closed page, or a request to an open page that matches a row address. the o slot holds a request to an open page that matches a row address. figure 6-7. request pipeline arbitration between the request at the gliu0 interface, the c request, and the o request at the dram end, depend on selection factors that try to optimize dram bus utilization and maximize throughput. this may involve reordering transactions as long as ordering rules and coherency are maintained. requests from the same geodelink device source are kept in order. req uests from different sources may pass each other as long as the addresses do not match. if reordering is allowable, requests may be reordered for the following reasons: 1) a request with a higher priority can pass a request in front of it with a lower priority, as long as the higher- priority request is ready to run and nothing else is already running. (conversely, a request with a lower priority may not pass a request in front of it with greater or equal priority.) 2) a younger request that hits to an open page can pass an older request in front of it that is not a page hit. 3) a write request still gathering its write data may be passed by a request behind it that is ready to run. 4) writes and reads are clumped together by the glmc to minimize bus turnarounds. the criteria for reordering is prioritized as above, with the requests? priority fields (pri) taking top precedence in determining if reordering may be performed. reordering based on criterion #2 may only happen if the relative priori- ties are sorted out as per criterion #1, and so on. requests in the c and o slots are run before the request at the gliu0 interface if the dram is ready to receive them. the gliu0 interface request can pass c and o requests only if the interface request is a read; a write needs to gather data in the write buffer first so it ends up moving to the c and possibly o slot while waiting. (for the case where a gliu0 non-burst write request and its single beat of write datum are valid in the same clock, writes could possibly be optimized to bypass the write buffer, thus allowing write requests from the gliu0 interface to be run on the fly at the dram interface. note that only single writes may be optimized; burst writes must be buffered first as there may be bubbles between data beats.) requests from the same source whose addresses are within the same cache line are run in order; otherwise, reordering from the same source is allowed. typically, refresh requests are run when gliu0 has indi- cated that a refresh can be initiated via a null refresh request transaction. the glmc has a refresh counter that, once enabled and initialized with an interval count, freely counts down to keep track of refresh intervals. each time this refresh counter times out, a refresh request is added to the glmc refresh queue, which can queue up to eight refresh requests. once a null refresh request is received from gliu0, and there is at least one refresh request in the refresh queue, and all outstanding transactions are fin- ished in the glmc, the glmc deletes one request from the queue and performs one refresh cycle. if gliu0 fails to send a null request in a timely manner, and eight refreshes queue up without a null request from gliu0, the refresh request is upgraded to the highest prior- ity, and one refresh proceeds. requests from the gliu0 interface will not be accepted unt il the high-priority refresh runs. mode-register-set requests and low-power-entry are arbitrated at the same level as high priority refresh. gliu ff refresh/low power/mode set c slot ff o slot ff sd ff gliu0 req
216 amd geode? lx processors data book geodelink? memory controller 33234h 6.1.1.3 data path the write datapath utilizes three write buffers to gather write data within a burst, each one is 4 deep x 64 bits. writes to the buffers are alternated between the three buff- ers or whichever one is empty. the sid, pid, and implied bex are also buffered along with the write data. once the write request has been proce ssed and arbitrated, and the corresponding gliu0 write data transfer is complete into the buffers, the buffers are then read out and the write command is dispatched out to memory. which of the three buffers is read out depends on which buffer?s sid, pid matches the sid, pid of the write request that won the arbitration for the dram. if more than one buffer?s sid, pid matches the write request?s sid, pid, then the buffer with the older data is read out. the write data is clocked out using a delay-tuned version of the glmc/sdram write clock. only one transaction?s set of write data is written into a buffer; therefore, only three write transactions can be buffered at any time. the write data is written into and read out of the buffers on the gliu0 clock, which is twice the frequency of the glmc/sdram clock. the da ta strobes dqs are also shipped out with each data beat, center-aligned with the data to strobe the data into the dram. unlike sdram, there is a write latency tdqss between the write command and the first write data presented to dram. read data is not buffered to minimize latency. the dqs strobes generated by the dram are edge-aligned with the read data, and are used to re gister the read data.the clock ratio between the gliu0 clock and glmc clock is a syn- chronous 2:1. since the arrival of the data can vary by as much as one clock from byte to byte, and vary over time and temperature, the glmc ca ptures and resyncs the data byte by byte as it becomes valid. 6.1.1.4 glmc/glcp /pad delay control settings glmc signals to and from the pads are controlled with var- ious delay lines in the pads. these delay lines are pro- grammable in the glcp module. for details on these delay controls, refer to the section 6.14.2.8 "glcp i/o delay controls (glcp_delay_controls)" on page 549. 6.1.1.5 basic timing diagrams figure 6-8 and figure 6-9 on page 217 illustrate timing waveforms for ddr reads and ddr writes. figure 6-8. ddr reads rd3 rd1 rd0 rd0 drdywx m_sd_data daout drdyrx clock ds r_data_sync rd2 rd3 rd1 rd0 rd0 rd2 r_data_pad rd3 rd1 rd0 rd0 rd2
amd geode? lx processors data book 217 geodelink? memory controller 33234h figure 6-9. ddr writes mph1 m_sd_data drdyrx rqin_ready dain rqin_take wrx0 wrx1 wrx2 wrx3 drdywx wry0 dain_ready dain_take rqin wrreqy wrreqx wrx0 wrx1 wrx2 wrx3 wry0 w_databuf_out daout wrrespx wrrespy wrx1 m_sd_dqs wrx0 wrx2 wrx3 wry0 wrx1 wrx0 wrx2 wrx3 wry0 w_dataf
218 amd geode? lx processors data book geodelink? memory controller 33234h 6.1.2 power control the glmc employs some methods of power control for power savings. one method is that it tri-states the glmc address and control pins when there is no valid address or control data being driven (i.e., when all the chip selects are inactive (high). this feature is enabled via glmc msr 2000001dh[12] (tri_state_dis), and is dis- abled by default. the second and third methods of power control are effected via the glmc?s gld_msr_pm register (msr 20002004h). the two modes of power control achievable via this register are pmod e0 and pmode1. if pmode0 is enabled, whenever the glmc?s internal state machines are idle and no requests or data are being processed, the glmc will shut off one of its two clocks, mb_clk, to save power. its other clock, mc_clk, remains active to maintain the refresh counters. if it needs to perform a refresh, or if a gliu request comes into the glmc, mb_clock is reacti- vated on the next cycle and th e glmc resumes full power. if pmode1 is enabled, the glmc goes into a deeper level of power-down when it becomes idle. it first sets up the dram to go into self-refresh, then shuts off both of its clocks. a wakeup signal in the form of a gliu request (or reset if the system powers down completely) gets the glmc back into full power. per dram requirements, the glmc waits 200 mc_clocks before accepting the next gliu request (see glmc ms r 2000001ah[15:8]). also, in order to avoid going into pmode0 or pmode1 unnecessar- ily, there are programmable sensitivity counters for both modes (see glmc msr 2000002 0h) that provide a way to filter out idle periods less than the duration specified in these counters. sequence of steps that occur on entry into pmode1 (i.e., save-to-ram): 6.1.2.1 entry into pmode1 (save-to-ram) when save-to-ram is requested: 1) acpi software performs all required memory writes. 2) if necessary, write a non-zero value to pm1_sens counter (msr 200000020h[63:32]). this filters out glmc idle periods less than counter value, so pmode1/save-to-ram is only entered on sufficiently long idle periods. 3) set pmode1 in msr 20002004h[2] to 1 to enable pmode1. on the next glmc idle condition that is longer than the value in pm1_sens, the glmc per- forms the following: 4) finish any outstanding memory transactions if any. 5) issue self-refresh command to put dimms in self- refresh. this entails issuing a refresh command with cke = 0. 6) turn off both glmc?s internal mc_clk and mb_clk. 6.1.2.2 resume from pmode1 either a reset or a gliu request wakes up the glmc from pmode1, triggering the following sequence: 1) both internal clocks, mb_clk and mc_clk, resume on next clock after wakeup event. 2) cke is released on next clock after clocks resume. if power was removed during entry into pmode1, cke is released as in a cold boot sequence. 3) a mode register set cycle to the dram is generated using the data that was programmed into the mc_cf07_data register (msr 20000018h) 4) after 200 sdclks (as set in pm1_up_dly (msr 2000001ah[15:8])), the glmc starts accepting mem- ory reads/writes. 6.1.3 bios initialization sequence this is the recommended sequence that bios should take to initialize the glmc and drams properly: 1) initialize the following glmc registers/bits based on serial presence detect (spd) values: ? msr 20000018h except ref_int bits [23:8] ? msr 20000019h 2) initialize the following glmc registers: ? msr 2000001ah[15:8] = c8h ? msr 20002004h[2] = 0, [0] = 1 3) release mask_cke[1:0] (msr 2000001dh[9:8] = 11). 4) set/clear ref_tst bit (msr 20000018h[3]) 16 times to force 8 refreshes. this also causes a precharge-all before the first refresh, per jedec requirement. 5) initialize ref_int (msr 20000018h[23:8]) to set refresh interval. 6) perform load-mode with msr_ba = 01 (msr 200000018h[29:28] = 01) to initialize dimm extended mode register. load-mode is performed by setting/ clearing prog_dram (msr 200000018h[0]). 7) set rst_dll (msr 20000018h[27] = 1), perform sec- ond load-mode with msr_ba = 00 (msr 20000018h[29:28]) to initialize mode register and reset dll. 8) perform third load-mode (msr 20000018h[29:28] = 00) and rst_dll cleared (msr 20000018h[27] = 0). 9) clear tristate_dis (msr 2000001dh[12] = 0) to enable the glmc tri_stat e during idle cycles (i.e., cs[3:0]# = fh). 10) wait at least 200 sdclks before performing the first read/write operation.
amd geode? lx processors data book 219 geodelink? memory controller register descriptions 33234h 6.2 geodelink? memory contro ller register descriptions all glmc registers are model specific registers (msrs) and are accessed via the rdmsr and wrmsr instruc- tions. the registers associated with the glmc are the standard geodelink device (gld) msrs and glmc specific msrs. table 6-5 and table 6-6 are register summary tables that include reset values and page references where the bit descriptions are provided. note: msr addresses are documented using the cpu core as the source. refer to section 4.1 "msr set" on page 45 for further details. table 6-5. standard geodelink? device msrs summary msr address type register name reset value reference 20002000h ro gld capabilities msr (gld_msr_cap) 00000000_000204xxh page 220 20002001h --- gld master configuration msr (gld_msr_config) - not used 00000000_00000000h page 220 20002002h r/w gld smi msr (gld_msr_smi) 00000000_00000000h page 220 20002003h r/w gld error msr (gld_msr_error) 00000000_00000000h page 221 20002004h r/w gld power management (gld_msr_pm) 00000000_00000000h page 222 20002005h r/w gld diagnostic (gld_msr_diag) 00000000_00000000h page 222 table 6-6. glmc specific msr summary msr address type register name reset value reference 20000010h ro row addresses bank0 dimm0, bank1 dimm0 (mc_cf_bank01) xxxxxxxx_xxxxxxxxh page 223 20000011h ro row addresses bank2 dimm0, bank3 dimm0 (mc_cf_bank23) xxxxxxxx_xxxxxxxxh page 223 20000012h ro row addresses bank4 dimm0, bank5 dimm0 (mc_cf_bank45) xxxxxxxx_xxxxxxxxh page 224 20000013h ro row addresses bank6 dimm0, bank7 dimm0 (mc_cf_bank67) xxxxxxxx_xxxxxxxxh page 224 20000014h ro row addresses bank0 dimm1, bank1 dimm0 (mc_cf_bank89) xxxxxxxx_xxxxxxxxh page 225 20000015h ro row addresses bank2 dimm1, bank3 dimm1 (mc_cf_bankab) xxxxxxxx_xxxxxxxxh page 225 20000016h ro row addresses bank4 dimm1, bank5 dimm1 (mc_cf_bankcd) xxxxxxxx_xxxxxxxxh page 226 20000017 ro row addresses bank6 dimm1, bank7 dimm1 (mc_cf_bankef) xxxxxxxx_xxxxxxxxh page 226 20000018h r/w refresh and sdram program (mc_cf07_data) 10071007_00000040h page 227 20000019h r/w timing and mode program (mc_cf8f_data) 18000008_287337a3h page 229 2000001ah r/w feature enables (mc_cf1017_data) 00000000_11080001h page 231 2000001bh ro performance counters (mc_cfperf_cnt1) 00000000_00000000h page 232 2000001ch r/w counter and cas control (mc_percnt2) 00000000_00ff00ffh page 233 2000001dh r/w clocking and debug (mc_cfclk_dbug) 00000000_00001300h page 233 2000001eh ro page open status (mc_cfpg_open) 00000000_0000ffffh page 235
220 amd geode? lx processors data book geodelink? memory controller register descriptions 33234h 6.2.1 standard geodelink? device (gld) msrs 6.2.1.1 gld capabilities msr (gld_msr_cap) 6.2.1.2 gld master configuration msr (gld_msr_config) - not used this register is not used in the glmc module. 6.2.1.3 gld smi msr (gld_msr_smi) this register is not used in the glmc module 2000001fh --- reserved --- --- 20000020h r/w pm sensitivity counters (mc_cf_pmctr) 00000000_00000006h page 236 msr address 20002000h ty p e r o reset value 00000000_000204xxh table 6-6. glmc specific msr summary msr address type register name reset value reference gld_msr_cap register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. 23:8 dev_id device id. identifies device (0204). 7:0 rev_id revision id . identifies device revision. see amd geode? lx processors specification update document for value. msr address 20002001h ty p e reset value 00000000_00000000h msr address 20002002h ty p e r / w reset value 00000000_00000000h
amd geode? lx processors data book 221 geodelink? memory controller register descriptions 33234h 6.2.1.4 gld error msr (gld_msr_error) msr address 20002003h ty p e r / w reset value 00000000_00000000h gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 errval[15:1] (rsvd) err_val0 errmas[15:1] (rsvd) err_mask0 gld_msr_error bit descriptions bit name description 63:32 rsvd reserved. 31:17 rsvd reserved. 16 err_val0 error value 0. synchronous error flag, sent out wit h gliu response packet. hardware sets error value; writes of 1 clears the erro r. the glmc only implements the ?type-excep- tion? error on bit 16, which is set when the gliu request?s type field is either an i/o type or snoop type. this bit will be set on such error condition, regardless of the value of err_mask0. an asynchronous error is also flagged via the mb_p_e rr output signal. note that when an error condition exists, the response packet that corresponds with the gliu request that caused the error may be re turned to the gliu out of order (i.e., ahead of response data for older, outstanding requests in the glmc). moreover, the older, out- standing requests may return corrupt data. (default = 0) 15:1 rsvd reserved. 0 err_mask0 error mask 0. masks the corresponding error in bit 16. the glmc only implements error mask 0 that corresponds to er ror bit 16. this bi t masks the reporting of the error event recorded in bit 16. (default = 0h)
222 amd geode? lx processors data book geodelink? memory controller register descriptions 33234h 6.2.1.5 gld power management (gld_msr_pm) 6.2.1.6 gld diagnostic (gld_msr_diag) this register is reserved for internal use by amd and should not be written to. msr address 20002004h ty p e r / w reset value 00000000_00000000h gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd pm1 rsvd pm0 gld_msr_pm bit descriptions bit name description 63:32 rsvd (ro) reserved (read only). reads back 0s. 31:3 rsvd reserved. 2pm1 power mode 1. clock gating for clock domains 0 (gliu clock) and 1 (glmc clock). once the glmc becomes idle, it enters pmode1 by 1) closing all banks with a ?precharge all? command to the dimms, 2) issuing a self-refresh command, 3) bringing cke1 and cke0 (balls f4 and e4 respectively) low and putting the address and control pins in tri_state mode, and 4) shutting off its gliu and glmc clocks on the next clock after the self- refresh. the glmc resumes to full power afte r any activity is de tected (i.e., a gliu request after reset). 0: disable clock gating. clocks are always on. (default) 1: enable active hardware clock gating. 1 rsvd reserved. 0pm0 power mode 0. clock gating for clock domain 0 (gliu clock). once the glmc becomes idle, it enters pmode0 by shutting off its gl iu clock on the next cycle. its glmc clock remains on to maintain the refresh counters, as do the sdram clocks. the glmc resumes full power either after any activity is detected, or when it needs to perform a refresh. 0: disable clock gating. clocks are always on. (default) 1: enable active hardware clock gating. msr address 20002005h ty p e r / w reset value 00000000_00000000h
amd geode? lx processors data book 223 geodelink? memory controller register descriptions 33234h 6.2.2 glmc specific msrs 6.2.2.1 row addresses bank0 di mm0, bank1 dimm0 (mc_cf_bank01) 6.2.2.2 row addresses bank2 di mm0, bank3 dimm0 (mc_cf_bank23) msr address 20000010h ty p e r o reset value xxxxxxxx_xxxxxxxxh mc_cf_bank01 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd mc_cf_bank1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd mc_cf_bank0 mc_cf_bank01 bit descriptions bit name description 63:54 rsvd reserved. reads back as 0. 53:32 mc_cf_bank1 memory configuration back 1. open row address (31:10) for bank1, dimm0. 31:22 rsvd reserved. reads back as 0. 21:0 mc_cf_bank0 memory configuration back 0. open row address (31:10) for bank0, dimm0. msr address 20000011h ty p e r o reset value xxxxxxxx_xxxxxxxxh mc_cf_bank23 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd mc_cf_bank3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd mc_cf_bank2 mc_cf_bank23 bit d escriptions bit name description 63:54 rsvd reserved. reads back as 0. 53:32 mc_cf_bank3 memory controller configuration bank 3. open row address (31:10) for bank3, dimm0. 31:22 rsvd reserved. reads back as 0. 21:0 mc_cf_bank2 memory controller configuration bank 2. open row address (31:10) for bank2, dimm0.
224 amd geode? lx processors data book geodelink? memory controller register descriptions 33234h 6.2.2.3 row addresses bank4 di mm0, bank5 dimm0 (mc_cf_bank45) 6.2.2.4 row addresses bank6 di mm0, bank7 dimm0 (mc_cf_bank67) msr address 20000012h ty p e r o reset value xxxxxxxx_xxxxxxxxh mc_cf_bank45 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd mc_cf_bank5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd mc_cf_bank4 mc_cf_bank45 bit d escriptions bit name description 63:54 rsvd reserved. reads back as 0. 53:32 mc_cf_bank5 memory controller configuration bank 5. open row address (31:10) for bank5, dimm0. 31:22 rsvd reserved. reads back as 0. 21:0 mc_cf_bank4 memory controller configuration bank 4. open row address (31:10) for bank4, dimm0. msr address 20000013h ty p e r o reset value xxxxxxxx_xxxxxxxxh mc_cf_bank67 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd mc_cf_bank7 313029282726252423222120191817161514131211109876543210 rsvd mc_cf_bank6 mc_cf_bank67 bit descriptions bit name description 63:54 rsvd reserved. reads back as 0. 53:32 mc_cf_bank7 memory controller configuration bank 7. open row address (31:10) for bank7, dimm0. 31:22 rsvd reserved. reads back as 0. 21:0 mc_cf_bank6 memory controller configuration bank 6. open row address (31:10) for bank6, dimm0.
amd geode? lx processors data book 225 geodelink? memory controller register descriptions 33234h 6.2.2.5 row addresses bank0 di mm1, bank1 dimm0 (mc_cf_bank89) 6.2.2.6 row addresses bank2 di mm1, bank3 dimm1 (mc_cf_bankab) msr address 20000014h ty p e r o reset value xxxxxxxx_xxxxxxxxh mc_cf_bank89 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd mc_cf_bank9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd mc_cf_bank8 mc_cf_bank89 bit descriptions bit name description 63:54 rsvd reserved. reads back as 0. 53:32 mc_cf_bank9 memory controller configuration bank 9. open row address (31:10) for bank1, dimm1. 31:22 rsvd reserved. reads back as 0. 21:0 mc_cf_bank8 memory controller configuration bank 8. open row address (31:10) for bank0, dimm1. msr address 20000015h ty p e r o reset value xxxxxxxx_xxxxxxxxh mc_cf_bankab register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd mc_cf_bankb 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd mc_cf_banka mc_cf_bankab bit descriptions bit name description 63:54 rsvd reserved. reads back as 0. 53:32 mc_cf_bankb memory controller configuration bank b. open row address (31:10) for bank3, dimm1. 31:22 rsvd reserved. reads back as 0. 21:0 mc_cf_banka memory controller configuration bank a. open row address (31:10) for bank2, dimm1.
226 amd geode? lx processors data book geodelink? memory controller register descriptions 33234h 6.2.2.7 row addresses bank4 di mm1, bank5 dimm1 (mc_cf_bankcd) 6.2.2.8 row addresses bank6 di mm1, bank7 dimm1 (mc_cf_bankef) msr address 20000016h ty p e r o reset value xxxxxxxx_xxxxxxxxh mc_cf_bankcd register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd mc_cf_bankd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd mc_cf_bankc mc_cf_bankcd bit descriptions bit name description 63:54 rsvd reserved. reads back as 0. 53:32 mc_cf_bankd memory controller configuration bank c. open row address (31:10) for bank5, dimm1. 31:22 rsvd reserved. reads back as 0. 21:0 mc_cf_bankc memory controller configuration bank b. open row address (31:10) for bank4, dimm1. msr address 20000017 ty p e r o reset value xxxxxxxx_xxxxxxxxh mc_cf_bankef register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd mc_cf_bankf 313029282726252423222120191817161514131211109876543210 rsvd mc_cf_banke mc_cf_bankef bit descriptions bit name description 63:54 rsvd reserved. reads back as 0. 53:32 mc_cf_bankf memory controller configuration bank f. open row address (31:10) for bank7, dimm1. 31:22 rsvd reserved. reads back as 0. 21:0 mc_cf_banke memory controller configuration bank e. open row address (31:10) for bank6, dimm1.
amd geode? lx processors data book 227 geodelink? memory controller register descriptions 33234h 6.2.2.9 refresh and sdram program (mc_cf07_data) msr address 20000018h ty p e r / w reset value 10071007_00000040h mc_cf07_data register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 d1_sz rsvd d1_mb rsvd d1_cb rsvd d1_psz d0_sz rsvd d0_mb rsvd d0_cb rsvd d0_psz 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd msr_ba rst_dll emr_qfc emr_drv emr_dll ref_int ref_stag ref_tst rsvd soft_rst prog_dram mc_cf07_data bit descriptions bit name description 63:60 d1_sz dimm1 size. 0000: reserved 0100: 64 mb 1000: 1 gb 0001: 8 mb (default) 0101: 128 mb 1001-1111: reserved 0010: 16 mb 0110: 256 mb 0011: 32 mb 0111: 512 mb 59:57 rsvd reserved. 56 d1_mb dimm1 module banks. number of module banks for dimm1. 0: 1 module bank. (default) 1: 2 module banks. 55:53 rsvd reserved. 52 d1_cb dimm1 component banks. number of component banks per module bank for dimm1. 0: 2 component banks. (default) 1: 4 component banks. 51 rsvd reserved. 50:48 d1_psz dimm1 page size. 000: 1 kb 100: 16 kb 001: 2 kb 101: 32 kb 010: 4 kb 110: reserved 011: 8 kb 111: dimm 1 not installed (default) 47:44 d0_sz dimm0 size. 0000: reserved 0100: 64 mb 1000: 1 gb 0001: 8 mb (default) 0101: 128 mb 1001-1111: reserved 0010: 16 mb 0110: 256 mb 0011: 32 mb 0111: 512 mb 43:41 rsvd reserved. 40 d0_mb dimm0 module banks. number of module banks for dimm0. 0: 1 module bank. (default) 1: 2 module banks. 39:37 rsvd reserved.
228 amd geode? lx processors data book geodelink? memory controller register descriptions 33234h 36 d0_cb dimm0 component banks. number of component banks per module bank for dimm0. 0: 2 component banks. (default) 1: 4 component banks. 35 rsvd reserved. 34:32 d0_psz dimm0 page size. 000: 1 kb 100: 16 kb 001: 2 kb 101: 32 kb 010: 4 kb 110: reserved 011: 8 kb 111: dimm0 not installed (default) 31:30 rsvd reserved. 29:28 msr_ba mode register set bank address. these are the bank select bits used for program- ming the ddr dimm?s extended mode register. t hese bits select whether the glmc is programming the mode register or the extended mode register. 00: program the dimm mode register. (default) 01: program the dimm extended mode regist er. bits [26:24] determine the program data. 10: reserved. 11: reserved. 27 rst_dll mode register reset dll. this bit represents a8 in the mode register, which when set to 1 resets the dll as part of the dimm initialization sequence. jedec recommends clearing this bit back to 0 on the final load-mode-register command before activating any bank. 0: do not reset dll. (default. 1: reset dll. 26 emr_qfc extended mode register fet control. this bit programs the dimm?s qfc# signal. the qfc# signal provides control for fet switches that are used to isolate module loads from the system memory busy at times when the given module is not being accessed. only pertains to x4 configurations. 0: enable. (default) 1: disable. 25 emr_drv extended mode register drive strength control. this bit selects either normal or reduced drive strength. 0: normal. (default) 1: reduced. 24 emr_dll extended mode register dll. this bit disables/enables the dll. 0: enable. (default) 1: disable. 23:8 ref_int refresh interval. this field determines the number of sdram clocks between refresh. this value multiplied by 16 is the average nu mber of clocks between refresh. the default value, 00h, disables refresh. 7:4 ref_stag refresh staggering. this field controls the number of clocks (0-16) between ref com- mands to different banks during refresh cycles. staggering is used to help reduce power spikes during refresh. note that with a setti ng of 0, no staggering occurs, so all module banks are refreshed simultaneously. (default = 1) 3 ref_tst test refresh. this bit, when set high, generates one refresh request that the glmc queues in its refresh request queue. since t he refresh queue is 8-deep, 8 sets/clears of this bit queues 8 refresh requests, thus forc ing a refresh request out to dram. this bit should only be used for initialization and test. (default = 0) mc_cf07_data bit descriptions (continued) bit name description
amd geode? lx processors data book 229 geodelink? memory controller register descriptions 33234h 6.2.2.10 timing and mode program (mc_cf8f_data) 2 rsvd reserved. 1soft_rst software reset. puts the glmc in a known state. does not change configuration regis- ters. the recommended sequence to use is: 1) make sure sdram interface has ?been idle for a while?. 2) set software reset, t hen clear software reset. 3) do a refresh cycle. accesses to memory may resume as normal following this. note that configuration regi sters are not scannable. to reproduce a problem in simulation requires saving the configuration registers with software in silicon and reprogramming the values in simulation. (default = 0) 0prog_dram program mode register in sdram. when this bit is set, the glmc will issue one load mode register command to the drams. it either programs the mode register (if msr_ba, bits [29:28] = 00), or the extended mode register (if msr_ba, bits [29:28] = 01). the mode register is programmed wi th cas latency (see msr 2000019h[30:28]), wrap type sequential, and burs t length of 4 for 64-bit data path, or burst length of 8 for 32- bit wide data path. the extended mode regist er in ddr dimms is programmed with the qfc#, drive strength and dll disable bits [26:24]. the extended mode register must be programmed first to enable the dlls, then the mode register. this bit must be set and cleared for each load mode register command. (default = 0) msr address 20000019h ty p e r / w reset value 18000008_287337a3h mc_cf07_data bit descriptions (continued) bit name description mc_cf8f_data register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 stale_req rsvd xor_bit_sel xor_mb0 xor_ba1 xor_ba0 rsvd trunc_dis reorder_dis rsvd hoi_loi rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 thz_dly cas_lat act2actref act2pre rsvd pre2act rsvd act2cmd act2act dplwr dplrd rsvd
230 amd geode? lx processors data book geodelink? memory controller register descriptions 33234h mc_cf8f_data bit descriptions bit name description 63:56 stale_req gliu max stale request count. non-high priority requests (pri = 0) are made high-pri- ority requests when the request is not serviced within max stale request count clocks. (default = 18h) 55:53 rsvd reserved. 52:51 xor_bit_sel xor bit select. selects which upper gliu address bit to xor with mb0, ba1 or ba0 (see "auto low order interleaving" on page 212). only applies to loi mode. (default = 00). 00: addr[18] 01: addr[19] 10: addr[20] 11: addr[21] 50 xor_mb0 xor mb0 enable. enables xoring of module bank select mb0 with upper gliu address bit selected by xo r_bit_sel (bits [52:51]). (default = 0, disabled) 49 xor_ba1 xor ba1 enable. enables xoring of component bank select ba1 with upper gliu address bit selected by xo r_bit_sel (bits [52:51]). (default = 0, disabled) 48 xor_ba0 xor ba0 enable. enables xoring of component bank select ba0 with upper gliu address bit selected by xo r_bit_sel (bits [52:51]). (default = 0, disabled) 47:42 rsvd reserved. 41 trunc_dis burst truncate disable. disables truncation of read/writ e bursts. this disable reduces performance and should only be used during debug. (default = 0, bursts enabled) 40 reorder_dis reorder disable. disables the reordering of requests. this bit must be set to 1. 39:34 rsvd reserved. 33 hoi_loi high / low order interleave select (hoi / loi). selects the address interleaving mode. hoi uses fixed upper address bits to map the gliu address to a component bank. loi uses variable lower address bits depending on page size, number of module banks, and number of component banks of the dimms, plus an option to xor with upper address bits. 1: hoi. 0: loi. (default) 32 rsvd reserved. 31 thz_dly thz delay. add 1 extra clock on read-to-write turnarounds to satisfy dram parameter t hz for higher frequencies. (default = 0) 30:28 cas_lat read cas latency. number of clock delays between read command and data valid. cas latency: 000: rsvd 010: 2 (default) 100: 4 110: 2.5 001: rsvd 011: 3 101: 1.5 111: 3.5 27:24 act2actref act to act/ref period. trc. minimum number of sdram clocks between active and active/auto refresh commands. (default = 8h) 23:20 act2pre act to pre period. tras. minimum number of clocks from act to pre commands on the same component bank. (default = 7h) 19 rsvd reserved. 18:16 pre2act pre to act period. trp. minimum number of sdram clocks between pre and act com- mands. (default = 011) 15 rsvd reserved. 14:12 act2cmd delay time from act to read/write. trcd. minimum number of sdram clocks between act and read/write commands. (6..2 valid). (default = 011)
amd geode? lx processors data book 231 geodelink? memory controller register descriptions 33234h 6.2.2.11 feature enab les (mc_cf1017_data) 11:8 act2act act(0) to act(1) period. trrd. minimum number of sdram clocks between act and act command to two different component banks within the same module bank. (default = 7h) 7:6 dplwr data-in to pre period. tdplw. minimum number of clocks from last write data to pre- charge command on the same component bank. (3..1 valid). default = 10) 5:4 dplrd data-in to pre period. tdplr. minimum number of clocks from last read data to pre- charge command on the same component bank.(3 ..1 valid) the count starts on the same clock that the last data would have been if the command was a write. (default = 10) 3 rsvd reserved. 2:0 rsvd reserved. msr address 2000001ah ty p e r / w reset value 00000000_11080001h mc_cf8f_data bit descriptions (continued) bit name description mc_cf1017_data register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd wr_to_rd rsvd rd_tmg_ctl rsvd ref2act pm1_up_dly rsvd wr2dat mc_cf1017_data bit descriptions bit name description 63:30 rsvd reserved. 29:28 write_to_rd write to read delay. twtr. minimum number of sdclks between last write data beat to next read command. (default = 01) 27 rsvd reserved. 26:24 rd_tmg_ctl read timing control. number of half-gliu clocks that the read data is delayed in arriving at the glmc beyond the cas latency delay. this number increases as the round-trip read delay increases. (default = 001) 23:21 rsvd reserved. 20:16 ref2act refresh to activate delay. trfc. minimum number of sdclks (0-31) between refresh and next command, usually an activate. (default = 8h) 15:8 pm1_up_dly pmode1 up delay. sets the delay in dram clocks from exit from pmode1 to accep- tance of the next gliu memory request. pmode1 power down involves a self-refresh command to dram. this is to satisfy a 200-cl ock delay from self-refresh exit to first read command (although this bit will delay all commands, read and write). (default = 0, no delay) 7:3 rsvd reserved.
232 amd geode? lx processors data book geodelink? memory controller register descriptions 33234h 6.2.2.12 performance counters (mc_cfperf_cnt1) 2:0 wr2dat write command to data latency. number of clocks between the write command and the first data beat. valid values are: [2,1,0], and must correspond to the installed dimms as follows: 0h: no delay. 1h: 1-clock delay for ddr unbuffered dimms. (default) msr address 2000001bh ty p e r o reset value 00000000_00000000h mc_cf1017_data bit descriptions bit name description mc_cfperf_cnt1 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 cnt1 313029282726252423222120191817161514131211109876543210 cnt0 mc_cfperf_cnt1 bit descriptions bit name description 63:32 cnt0 counter 0. performance counter 0. counts the occu rrence of events at the gliu inter- face. events are specified in cnt0_dat a (msr 2000001ch[7:0]). reset and stop con- trol on this counter is done via msr 200001ch[33:32]. (default = 0h) 31:0 cnt1 counter 1. performance counter 1. counts the occu rrence of events at the gliu inter- face. events are specified in cnt1_data (msr 2000001ch[23:16]. reset and stop con- trol on this counter is done via msr 200001ch[35:34]. (default = 0h)
amd geode? lx processors data book 233 geodelink? memory controller register descriptions 33234h 6.2.2.13 counter and cas control (mc_percnt2) 6.2.2.14 clocking and debug (mc_cfclk_dbug) msr address 2000001ch ty p e r / w reset value 00000000_00ff00ffh mc_perfcnt2 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd stop_cnt1 rst_cnt1 stop_cnt0 rst_cnt0 313029282726252423222120191817161514131211109876543210 rsvd mc_perfcnt2 bit descriptions bit name description 63:36 rsvd reserved. 35 stop_cnt1 stop counter 1. if set, stops counter 1. (default = 0) 34 rst_cnt1 reset counter 1. if set, resets counter 1. (default = 0) 33 stop_cnt0 stop counter 0. if set, stops counter 0. (default = 0) 32 rst_cnt0 reset counter 0. if set, resets counter 0. (default = 0) 31:0 rsvd reserved. msr address 2000001dh ty p e r / w reset value 00000000_00001300h mc_cfclk_dbug register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd b2b_dis mtest_rbex_en mtest_en 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd force_pre rsvd tristate_dis rsvd mask_cke1 mask_cke0 cntl_msk1 cntl_msk0 adrs_msk rsvd
234 amd geode? lx processors data book geodelink? memory controller register descriptions 33234h mc_cfclk_dbug bit descriptions bit name description 63:35 rsvd reserved. 34 b2b_dis back-to-back command disable. setting this bit disables the issuing of dram com- mands within back-to-back cycles in both mtest and normal functional mode. to maxi- mize performance, this should only be used in mtest mode, where the cycle following the command cycle should be idle for the logic analyzer to be able to properly capture and interpret the mtest data. (default = 0) (back-to-back commands allowed). 33 mtest_rbex_ en mtest rbex enable. enables the outputting of read byte enables information on reads with rbexs. 0: disable. (default) 1: enable. 32 mtest_en mtest enable . enables mtest debug mode, which multiplexes debug data onto the 13 dram address output pins, one cycle after the command cycle. (default = 0) 31:17 rsvd reserved. 16 force_pre force precharge-all. force precharge-all command before load-mode and refresh com- mands, even when banks are already all closed. normally, a precharge-all command only gets issued conditionally before a load-mode or refresh command: only if the module banks are not all closed yet. with this bit se t, the precharge-all will be issued uncondition- ally before the load-mode or refresh command. 0: disable. (default) 1: enable. 15:13 rsvd reserved. 12 tristate_dis tri-state disable. this bit controls the power saving feature that puts the glmc's address and control pins into tri-state mo de during idle cycles or during pmode1. 0: tri-stating enabled. 1: tri-stating disabled. (default) 11:10 rsvd reserved. 9:8 mask_cke[1:0] cke mask . mask output enables for cke[1:0]. after power-up or warm reset, software can complete all necessary in itialization tasks befor e clearing this mask to allow commu- nication with the dram. these bits can also be used to selectively mask off the cke sig- nal of a dimm that is not installed. 00: cke1 and cke0 unmasked. 01: cke1 unmasked, cke0 masked. 10: cke1 masked, cke0 unmasked. 11: cke1 and cke0 masked. (default) 7 cntl_msk1 control mask 1. mask output enable bit for dimm1?s cas1#, ras1#, we1#, cs[3:2]#. 0: unmasked. (default) 1: masked. 6 cntl_msk0 control mask 0. mask output enable bit for dimm0?s cas0#, ras0#, w0#, cs[1:0]#. 0: unmasked. (default) 1: masked. 5 adrs_msk address mask. mask output enable bit for ma and ba. (default = 0) 4:0 rsvd reserved.
amd geode? lx processors data book 235 geodelink? memory controller register descriptions 33234h 6.2.2.15 page open status (mc_cfpg_open) 6.2.2.16 reser ved register this register is reserved and should not be written to. msr address 2000001eh ty p e r o reset value 00000000_0000ffffh mc_cfpg_open register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pgopen1 pgopen0 mc_cfpg_open bit descriptions bit name description 63:16 rsvd reserved. reads back as 0. 15:8 pgopen1 page open dimm 1. page open indication of the second dimm. each bit position repre- sents a page and a 1 indicates an open page. all pages are initialized ?open?. after reset, a ?precharge all? command closes all the banks. 7:0 pgopen0 page open dimm 0. page open indication of the first dimm. each bit position represents a page and a 1 indicates an open page. all pages are initialized ?open?. after reset, a ?pre- charge all? command closes all the banks. msr address 2000001fh ty p e rw reset value 00000000_00000000h
236 amd geode? lx processors data book geodelink? memory controller register descriptions 33234h 6.2.2.17 pm sensitivity counters (mc_cf_pmctr) msr address 20000020h ty p e r / w reset value 00000000_00000006h mc_cf_pmctr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 pm1_sens 313029282726252423222120191817161514131211109876543210 pm0_sens mc_cf_pmctr bit descriptions bit name description 63:32 pm1_sens pmode1 sensitivity counter. counter that controls the glmc?s sensitivity to entering pmode1 power down mode. if pmode1 is enabled, pm1_sens starts counting down from its loaded value whenever the glmc becomes idle. if it times out and the glmc is still idle, the glmc goes into pmode1. if, however, the glmc resumes activity before time-out, the counter is reset to its loaded value and pmode1 is not entered. (default = 0h) 31:0 pm0_sens pmode0 sensitivity counter. counter that controls the glmc?s sensitivity to entering pmode0 power down mode. if pmode0 is enabled, pm0_sens starts counting down from its loaded value whenever the glmc becomes idle. if it times out and the glmc is still idle, the glmc goes into pmode0. if, however, the glmc resumes activity before time-out, the counter is reset to its loaded value and pmode0 is not entered. (default = 6h, to allow 32-bit bursts to finish).
amd geode? lx processors data book 237 graphics processor 33234h 6.3 graphics processor the graphics processor is based on the graphics proces- sor used in the amd geode? gx processor with several features added to enhance performance and functionality. like its predecessor, the amd geode lx processor?s graphics processor is a bitblt/vector engine that supports pattern generation, source expansion, pattern/source transparency, 256 ternary raster operations, alpha blenders to support alpha-blts, incorporated blt fifos, a geodelink? interface and the ability to throttle blts according to video timing. features added to the graphics processor include: ? command buffer interface ? hardware accelerated rotation blts ? color depth conversion ? palletized color ? full 8x8 color pattern buffer ? channel 3 - third dma channel ? monochrome inversion the block diagram of the amd geode lx processor?s graphics processor is shown in figure 6-10. table 6-7 on page 238 presents a comparison between the graphics processor features of the amd geode gx and lx proces- sors. figure 6-10. graphics processor block diagram pattern registers pattern expansion raster source aligner & expansion operation source & destination read fifos alpha blend unit write accumulation fifo geodelink? interface unit 0 (gliu0) channel 3 data flow control channel 3 data formatter 2k fifo and lut and pattern memory channel 3 fetch engine command buffer control logic and registers
238 amd geode? lx processors data book graphics processor 33234h table 6-7. graphics processor feature comparison feature amd geode? gx processor amd geode? lx processor color depth 8, 16, 32-bpp 8, 16, 32-bpp (a) rgb 4 and 8-bit indexed rops 256 (src, dest, pattern) 256 (2-src, dest and pattern) blt buffers fifos in graphics proc essor fifos in graphics processor blt splitting managed by hardware managed by hardware video synchronized blt/vector throttle by vblank throttle by vblank bresenham lines yes yes patterned (stippled) lines no yes screen to screen blt yes yes screen to screen blt with mono expansion ye s ye s memory to screen blt yes (through cpu writes) yes (throttled rep movs writes) accelerated text no no pattern size (mono) 8x8 pixels 8x8 pixels pattern size (color) 8x1 (32 pixels) 8x8 pixels 8x2 (16 pixels) 8x4 (8 pixels) monochrome pattern yes yes (with inversion) dithered pattern (4 color) no no color pattern 8, 16, 32-bpp 8, 16, 32-bpp transparent pattern monochrome monochrome solid fill yes yes pattern fill yes yes transparent source monochrome monochrome color key source transparency y with mask y with mask variable source stride yes yes variable destination stride yes yes destination write bursting yes yes selectable blt direction vertical and horizontal vertical and horizontal alpha blt yes (constant or /pix) yes (constant , /pix, or sep. channel) vga support decodes vga register decodes vga register pipeline depth 2 ops unlimited accelerated rotation blt no 8, 16, 32-bpp color depth conversion no 5:6:5, 1:5:5:5, 4:4:4:4, 8:8:8:8
amd geode? lx processors data book 239 graphics processor 33234h 6.3.1 command buffer the amd geode lx processor supports a command buffer interface in addition to the normal two-deep pipelined regis- ter interface. it is advised that software use either the com- mand buffer interface or the register interface. it is possible to use both, however, all pending operations should be allowed to complete before making the switch. the com- mand buffer interface is controlled through four registers that specify the starting ad dress of the command buffer, the ending address of the command buffer, the current write pointer and the current read pointer. the base address (top 12 bits) of the command buffer is specified in the gld_msr_config (msr a0002001h). during initial- ization, a block of memory is allocated to be the command buffer space. this block must be entirely contained within a non-cacheable 16 mb region of physical memory. the geode lx processor will not issue coherent transactions for the command buffer or any other memory operations. the starting address should be written to gp_cmd_top and the ending address should be written to gp_cmd_bot (gp memory offset 50h and 54h respec- tively). the starting address should also be written to gp_cmd_read (gp memory offset 58h). writing to gp_cmd_read automatical ly updates gp_cmd_write (gp memory offset 5ch). from this point, software can ini- tiate an action in the processor by writing a command buffer structure into memory at the write address (gp_cmd_write), then updating the write address to point to the next available space in the command buffer, either the next contiguous dword address, or the buffer starting address (gp_cmd_top) if the wrap bit is set in the command buffer control word. command buffers are allowed to wrap around the end of the command buffer space (i.e., whenever the end of the space is reached, the hardware will continue fetching at the beginning of the space creating a circular buffer). however, software may force a wrap before the end of the buffer space is reached by setting the wrap bit in the control word, which causes the hardware to reset its read pointer to the beginning of the buffer space when the current command buffer is com- plete. do not attempt to perform a blt that expects host source data for both the old source channel and channel 3 unless one of the channels is receiving its host source data through the command buffer, and the other is receiving it directly from the processor. if this rule is violated, the gp and/or the entire system may hang. the structure of a blt command buffer is as follows: table 6-8. blt command buffer structure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w 0 0 s rsvd write enables gp_raster_mode data gp_dst_offset data gp_src_offset data gp_stride data gp_wid_height data gp_src_color_fg data gp_src_color_bg data gp_pat_color_0 data gp_pat_color_1 data g p _ pat _ data _ 0 d a t a g p _ pat _ data _ 1 d a t a gp_ch3_offset data gp_ch3_mode_str data gp_ch3_widhi data gp_base_offset data gp_blt_mode data dtype rsvd dcount optional data word 0 optional data word 1 ... optional data word n
240 amd geode? lx processors data book graphics processor 33234h table 6-9. vector command buffer structure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w 0 1 s rsvd write enables gp_raster_mode data gp_dst_offset data gp_vec_err data gp_stride data gp_vec_len data gp_src_color_fg data gp_pat_color_0 data gp_pat_color_1 data g p _ pat _ data _ 0 d a t a g p _ pat _ data _ 1 d a t a gp_ch3_mode_str data gp_base_offset data gp_vector_mode data table 6-10. lut (lookup table) load command buffer structure 313029282726252423222120191817161514131211109876543210 w 1 0 s rsvd we gp_lut_index data dtype rsvd dcount optional data word 0 optional data word 1 ... optional data word n table 6-11. data only command buffer structure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w 1 1 0 rsvd 1 dtype rsvd dcount optional data word 0 optional data word 1 ... optional data word n
amd geode? lx processors data book 241 graphics processor 33234h where: 6.3.2 channel 3 channel 3 is an additional dma channel (in addition to the first two channels: source and destination) that can fetch data from memory or receive it through host source writes. this channel has all of the data conversion features built in to perform rotational blts, color depth conversions, pallet- ized color support (lut lookups), 8x8 color pattern, and patterned vector support. the data coming out of this dma pipeline can selectively be steered into the old source channel or the old pattern channel, whichever is more nat- ural for a given rop. note that not all data coming out of this pipeline can be arbitrarily roped with other data (i.e., rotational blt data can not be roped with any other chan- nel, alpha data is expected to be used as input to the alpha unit). the behavior of channel 3 is controlled through gp_ch3_mode_str (gp memory offset 64h). channel 3 is also set up to be mostly independent from the other two channels, so it calculates its own addresses and pixel counters based on the gp_ch3_offset and gp_ch3_widhi (gp memory offset 60h and 68h respec- tively). it is possible to set up this channel with a different width and height than the destination (i.e., a rotation blt will have width and height sw apped from the destination). as long as the number of pixe ls to be fetched is the same as the output, there should be no problem. if this channel has too few pixels to complete the blt and is not in host source mode, the blt will terminate when this channel has fetched all of the requested data, and the underflow bit will be set in gp_blt_status (gp memory offset 44h). if this channel has pixels left when the blt is complete, the extra pixels are discarded and the overflow bit is set in gp_blt_status. channel 3 has the ability to begin prefetching data for a pending blt before the active blt has completed. the pe bit in the gp_ch3_mode_str register (gp memory off- set 64h[19]) can be set to allow prefetching for that blt. prefetching can safely be set for any blt that does not require write data from the previous blt as read data on channel 3. the gp does no hazard checking to verify the safety of the prefetch. this feature will incrementally improve performance as it allows the gp to make use of bus bandwidth that would otherwise have gone unused. prefetching has the lowest bus priority and is only done opportunistically. the x and y bits (bits 29 and 28) in the gp_ch3_mode_str register do not need to be pro- grammed the same as the bits in the gp_blt_mode reg- ister (gp memory offset 40h). if they are the same, the result is a source copy. if both bits are programmed oppo- site from the gp_blt_mode register, then the result is a 180 rotation. if only one bit is opposite, the result is a flip in that direction. when the current operation is a vector, channel 3 can gen- erate byte enables to stylize the vector based upon the pro- grammed pattern. channel 3 cannot be used to generate any pixel data while rendering vectors. table 6-12. bit descriptions name description we write enable. one bit for each of the required dwords which follow in the command buffer. a set bit indicates that the field is valid and should be updated in the gp. a clear bit indicates the field should be skipped. w wrap bit. if set, then return to the top of command buffer space after executing this buffer. s stall bit. execution of this command will be stal led until the gp?s pipeline is empty. dtype data type. type of data that follows: 000: host source data to old host source channel 001: host source data to new channel 3 010: pattern data to gp_pat_color_2 - gp_pat_color5 (gp memory offset 20h-2ch) 011: write data for lut/color pattern space 1xx: reserved dcount dword count. number of dwords of data that follow.
242 amd geode? lx processors data book graphics processor 33234h 6.3.2.1 rotating blts this feature of the gp allows bitmaps to be rotated 90, 180 or 270. the 90 and 270 modes work by reading vertical strips of the source bitmap that are one cache line (32 bytes) wide starting at either the top right or bottom left corner of the bitmap. the output is written as tiles that are one cache line wide by either 8, 16 or 32 pixels tall, depending on the color depth of the input data stream. because the data is not writt en out in scan line order, none of the other channels can be correctly roped with the data, so this operation should be treated as a source copy. also, because the entire buffer memory will be used for the fetched data, the input data stream may not be indexed color (it may be declared as 8-bpp, but it will not be con- verted through lut lookups. this may be done on a sec- ond pass after the rotation). to program a rotation blt of 90 clockwise, the rotation bit should be on in the gp_c h3_mode_str register (gp memory offset 64h[23]), the x and y bits for channel 3 should be clear and set respectively, the x and y in the gp_blt_mode register (gp memory offset 40h[9:8]) should both be clear, gp_ch3_offset (gp memory off- set 60h) should point to the bottom left corner of the source and gp_dst_offset (gp memory offset 00h) should point to the top left corner of the destination. to program a rotation blt of 270 clockwise, the rotation bit should be on in the gp_ch3_mode_str register, the x and y bits for channel 3 should be set and clear respec- tively, the x and y in the gp_blt_mode register should both be clear, gp_ch3_offset should point to the top right corner of the source and gp_dest_offset should point to the top left corner of the destination. to program a rotation blt of 180 clockwise, the rotation bit should be off in the gp_ch3_mode_str register, the x and y bits for channel 3 should be opposite their counter- parts in the gp_blt_mode register, and gp_ch3_offset should point to the opposite corner from gp_dest_offset. for all rotations, it is required that both the source stride and the destination stride be aligned to a cache line bound- ary (i.e., bottom 5 bits of stri de are all 0s). do not attempt to rotate host source data. the fill algorithm would be too complex and the likelihood of causing a fifo underrun and hanging the gp is too high. note that for rotation blts, the pl bit in the gp_ch3_mode_str register (gp memory offset 64h[20]) may not be set. the ent ire buffer is needed for the rotation so the lut and pattern data may not be retained. 6.3.2.2 rotating video the gp is primarily an rgb engine that does not natively understand yuv data. however, it is possible to perform video rotations using the gp hardware assuming the data is formatted correctly. if the da ta is in 4:2:0 format with the y data separated from the uv data, the rotation can be performed by passing each channel of the image sepa- rately through the gp and setting the color depth appropri- ately. for the y data, the colo r depth should be set to 8-bpp 3:3:2. the same is true for t he u and v data if they are in separate channels. if the u and v data are combined in one buffer then the color depth should be set to 16-bpp 5:6:5. similarly, 4:4:4 format data can also be supported if each channel is stored in its own buffer. 6.3.2.3 color depth conversion if the bpp/fmt bits in t he gp_ch3_mode_str register (gp memory offset 64h]27:24]) are set different than the bpp/fmt bits in the gp_r aster_mode re gister (gp memory offset 38h[31:28]), th en the incoming data is con- verted to match the output form at. if the bgr bit (gp mem- ory offset 64h[22]) is set, then the red and blue channels of the data will be swapped prior to the depth conversion (if any). a 24-bpp source format is supported on channel 3 allowing packed rgb pixels to be unpacked as they are written into the frame buffer. for this format, the channel 3 width is specified in dwords, not pixels. as a result, the channel 3 offset for 24-bpp data must therefore be aligned to a dword boundary. bgr conversion is not possible in this format since this operation is done before the depth con- version. 24-bpp images may not be rotated, they would need to be converted into another format first.
amd geode? lx processors data book 243 graphics processor 33234h 6.3.2.4 palletized color support if the preserve lut data bit is set in the gp_ch3_mode_str register (gp memory offset 64h[20]) then 1k of the 2k buffer space will be allocated to be a lut. as long as this bit remains set, the lut data is preserved as written. setting this bit has the impact of slightly lowering performance since it limits the prefetch ability of the gp, or its abilit y to receive massive amounts of host source data. this is unlikely to be a significant issue, but if the lut is not needed for future blts, then clearing this bit is recommended. it is required to be cleared during rotations since the entire 2k buffer space is needed. if the bpp/fmt bits in t he gp_ch3_mod_str register (gp memory offset 64h[27:24]) indicate that the incoming data is either 4 or 8-bpp indexed mode, then the lut will be used to convert the data into 16 or 32-bpp mode as specified in the gp_raste r_mode register?s bpp/fmt field (gp memory offset 38h[31:28]). the lut should be loaded prior to initiating such a blt by writing an address to the gp_lut_index register (gp memory offset 70h) followed by one or more dword writes to the gp_lut_data register (gp memory offset 74h) that will be loaded into the lut starting at that address. the address automatically in crements with every write. addresses 00h-ffh are used for 8-bpp indexed pixels and addresses 00h-0fh are used for 4-bpp indexed pixels. the result of a lookup is always a dword. if the output format is only 16-bpp, then only the data in the two least signifi- cant bytes is used. for 4-bpp incoming data, two pixels are packed within a byte such that bits[7:4] co ntain the leftmost pixel and bits[3:0] contain the rightmost pixel. the pixel ordering for 4-bit pixels is shown in table 6-13. for host source data, the starting offset into the first dword is taken from gp_ch3_offset[1:0] (and gp_ch3_offset[28] if the data is 4-bpp). for data being fetched from memory, gp_ ch3_offset[23:0] specifies the starting byte and gp_ ch3_offset[28] specifies the nibble within the byte for 4-bpp mode. note that, regardless of the output pixel depth, palletized color has a throughput of no more than one clock per pixel. the luts share memory with the incoming data fifo, so the datapath first pops the in coming indexed pixels out of the fifo (8 or 16 at a time), then performs the lut lookup, one pixel per clock, for the next 8 or 16 clocks, then must pop more data out of the fifo. table 6-13. pixel ordering for 4-bit pixels 313029282726252423222120191817161514131211109876543210 pixel 6 pixel 7 pixel 4 pixel 5 pixel 2 pixel 3 pixel 0 pixel 1
244 amd geode? lx processors data book graphics processor 33234h 6.3.2.5 anti-aliased text support channel 3 can be setup to fetch 4-bpp alpha channel data that can be combined with either 16 or 32-bpp color or monochrome source data using the alpha unit in the gp. the depth and type in the gp_ch3_mode_str register should be setup to indicate 4-bpp alpha and the as bits in the gp_raster_mode register (gp memory offset 38h[19:17]) should be set to 110 to select the alpha from channel 3. 6.3.2.6 8x8 color pattern channel 3 can also be configured to source full color pat- terns into the gp. the patt ern data is stored in the 2k buffer using writes to the gp_lut_index and gp_lut_data registers (gp memory offset 70h and 74h, respectively) as done for loading the lut. addresses 100h-10fh are used for 8-bpp patterns, 100h-11fh are used for 16-bpp patterns and 100h-13fh are used for 32- bpp patterns. note that this data will not be persistent in the buffer. if channel 3 is later used in non-pattern mode, then the pattern data will no longer be present in the buffer. therefore it is usually necessary to reload the pattern data before any blt requiring 8x8 color pattern support. the depth of the pattern is det ermined by the bpp/fmt bits (gp memory offset 64h[27:24]) of the gp_ch3_mode_str register (4-bpp is not allowed in pattern mode). the output of the pattern hardware is con- verted to the depth specifie d in the bpp/fmt gp bits (memory offset 38h[31:28]) of the gp_raster_mode register if the two depths do not match. 6.3.2.7 patterned vectors when pattern mode is enabled during a vector operation, channel 3 generates a patterned (stippled) vector. this is a linear monochrome pattern that is stored in the lut at locations 100h and 101h. the first dword (100h) con- tains the pattern, which is a string of four to 32 bits starting at bit 0. the second dword is used to indicate the length of the pattern and is a string of four to 32 ones starting at bit 0. tables 6-14 and 6-15 show an example vector pattern and length. the result of this vector pattern/length would be a 14-bit long pattern that, when repeated, looks figure 6- 11. the dark pixels are rendered using the selected rop, while the light pixels are transparent. the rop may con- tain any combination of sour ce, destination and pattern. if pattern is enabled in the rop, it comes from the old (non- channel 3) pattern hardware. note that a vector pattern must be at least four pixels long. for shorter patterns (i.e., two on, one off), repeat the pattern in the pattern registers until it is at least four pixels long. figure 6-11. 14-bit repeated pattern table 6-14. example vector pattern 313029282726252423222120191817161514131211109876543210 00000000000000000000110011001111 table 6-15. example vector length 313029282726252423222120191817161514131211109876543210 00000000000000000011111111111111
amd geode? lx processors data book 245 graphics processor 33234h 6.3.2.8 channel 3 host source channel 3 also supports host source data writes. when the hs bit is set in the gp_ch3_mode_str register (gp memory offset 64h[18]), the channel 3 fetch engine is dis- abled and the fifos are filled via register writes to the gp_ch3_hsrc register (gp me mory offset 6ch) or its aliased space. if the pl bit in the gp_ch3_mode_str register (gp memory offset 64h[ 20]) is not set then the gp can accept 2 kb of data through host source writes before its buffers are full. however, since monochrome is not sup- ported on this channel, the output flow rate of data closely matches the input flow (worst ca se is 8:1 if output is 32-bpp and input is 4-bpp) so it is unlikely that the gp will ever fill up. if it does fill its 2k buffer, then writes from the gliu will be disabled until there is space available to store it. soft- ware should not have to poll this interface to keep from overrunning the fifos. it shou ld be noted that, while it is possible to program the gp to accept host source data on both the source channel and channel 3, this should not be done unless one of the channels is filled through the com- mand buffer and the other through direct writes to the reg- ister. if this is the case, it is recommended that the source channel be filled through the command buffer and channel 3 be filled through register writes, since this will eliminate polling and provide higher performance. it will probably require less memory as well since the data into the source channel will likely be monochrome and fit into a smaller command buffer. 6.3.2.9 channel 3 hints software should try to setup the blts to use channel 3 whenever possible. this channel is designed to have the highest performance, since it is capable of prefetching great quantities of data even before a blt actually starts. this channel must be used when performing rotating blts, color depth conversions, palletized color, or 8x8 color pat- terns. this channel can carry source data, destination data, per-pixel alpha data, or pattern data. this channel cannot be used for monochrome data, and cannot be used for source or destination data if it must be roped with 8x8 pattern data. if the pattern does not need to be 8x8, then the old pattern hardware should be used as this will free up channel 3 to be used for higher performance memory fetches and host source data. the source channel has the ne xt highest performance, and should be used if two channels are necessary or if the data cannot be carried on channel 3. this channel can be used to fetch destination data, and the performance will be higher than using the destination channel. the destination channel should only be used to carry desti- nation data when it cannot be carried on either of the other two channels. this should only be the case when the rop calls for source, destination and pattern, when the opera- tion is a vector, or when alpha requires an a and b chan- nel. in all other cases, performance will be higher if destination is fetched on either the source channel or chan- nel 3. 6.3.3 blt operation to perform a blt, several registers must first be config- ured by the driver to specify the operation of the blt engine. these registers specif y the source and destination offsets into the frame buffer, the width and height of the blt rectangle, and the raster mode or alpha blend mode. in addition, any source colors, pattern colors, and pattern data should be loaded before initiating a blt. blts are initiated by writing to the gp_blt_mode regis- ter (gp memory offset 40h). th is register indicates the need for source and destination data, and defines the type of source data, and the dire ction in which the blt should proceed. color blts may be performed from left to right or right to left, top to bottom or bottom to top. this allows data to be transferred within the screen space without corrupting the areas from where the data is being copied. when monochrome source is used, however, the blt must be performed from left to right. instead of blt buffers (l1 cache), source read, destina- tion read, and destination wr ite fifos are used to tempo- rarily store the data that flows through the graphics processor. overflowing the fifos is not possible since the transfer is managed by the hardware anywhere within the 16 mb frame buffer memory region. at the start of a blt, two cache lines of destination data and up to four cache lines of source data are fetched (if needed). source data is fetched in groups of four cache lines, when possible. source data may either be read from within the frame buffer memory space or received from the cpu via writes to the gp_hst_src register (gp memory offset 48h). in either case, the data may be monochrome or color, as specified in the gp_blt_mode register (gp memory off- set 40h). if no source color is specified, the contents of the gp_src_color_fg register (gp memory offset 10h) is used as the default. for a soli d fill, neither source, destina- tion, nor pattern are required an d the resulting output pixel is derived from the contents of the gp_pat_color_0 register (gp memory offset 18h). the destination of the blt is always within the frame buffer memory region and is always the specified color depth, never monochrome. a bit is provided in the mode registers to allow blts and vectors to be throttled. when this bit is set for a particular operation, that operation does not begin executing until the next time the video timing enters vertical blank (vblank). this function can be used to improve 2d quality by mini- mizing tearing that occurs when writing to the frame buffer while the image is being drawn to the screen.
246 amd geode? lx processors data book graphics processor 33234h 6.3.4 vector operation generating a vector requires a similar setup to a blt. reg- isters must be written to spec ify the x and y offsets of the starting position of the vector within the frame buffer, the vector length, and the three error terms required by the bresenham algorithm. in addition, any pattern colors and pattern data should be loaded before initiating the vector. source data is not fetched when rendering vectors. instead, the contents of the gp_src_color_fg register (gp memory offset 10h) are used as the constant color for the vector. vectors are initiated by wr iting to the gp_vector_mode (gp memory offset 3ch) register. this register also indi- cates the need for destination data, and defines the major axis (x or y) and the major and minor directions (incre- menting or decrementing) of the vector. as in the blt operation, vectors can be throttled by video timing to prevent tearing. setting the th bit in the gp_vector_mode register (gp memory offset 3ch[4]) causes the graphics processor to wait until the next time that video timing enters vblank before beginning to ren- der the vector. 6.3.5 pipelined operation most of the graphics registers are pipelined. when the reg- isters are programmed and the operation begins, the con- tents of the registers are mo ved from slave registers to master registers, leaving the slave registers available for another operation. a second blt or vector operation can then be loaded into the slave registers while the first opera- tion is rendered. if a second blt is pending in the slave registers, additional write operations to the graphics regis- ters will corrupt the register values of the pending blt. software must prevent this from happening by checking the primitive pending bit in the gp_blt_status register (gp memory offset 44h[2]). the gp_pat_color_2 through gp_pat_color_5 (gp memory offset 20h-2ch) registers are not pipelined. if they are used in a new graphics operation, they should not be written when the primitive busy bit (gp memory offset 44h[0]) is set and the primitive pending bit is not set in the gp_blt_status register, and the active operation is using these registers. writi ng to these registers when a blt is active corrupts that operation. 6.3.6 pattern generation the graphics processor contains hardware support for 8x8 monochrome patterns (expanded to two colors), and color patterns. color patterns can be 8x4 in 8-bpp mode, 8x2 in 16-bpp mode, and 8x1 in 32-bpp mode. pattern alignment is based on the destination x and y lsbs of the pixel being drawn, so software can perform pattern justifications by adjusting these two parameters. for solid fill primitives, the pattern hardware is disabled and the pattern color is always sourced from the gp_pat_color_0 register (gp memory offset 18h). 6.3.6.1 monochrome patterns monochrome patterns are enabled by selecting mono- chrome pattern mode in the gp_raster_mode register (gp memory offset 38h). pixels that correspond to a clear bit in the pattern are rendered using the color specified in the gp_pat_color_0 (gp memory offset 18h) register, and pixels that correspond to a set bit in the pattern are rendered using the color specified in the gp_pat_color_1 register (gp memory offset 1ch). if the pattern transparency bit is set in the gp_raster_mode register (gp memory offset 38h), those pixels corresponding to a clear bit in the pattern data are not drawn, leaving the frame buffer pixels at these loca- tions untouched. the pattern itself is loaded into the gp_pat_data_0 and gp_pat_data_1 registers, with row 0 loaded into gp_pat_data_0 (gp memory offset 30h[7:0] (bit 7 being the left-most pixel on the screen)), and row 7 loaded into gp_pat_data_1 (gp memory offset 34h[31:24], see table 6-16).
amd geode? lx processors data book 247 graphics processor 33234h 6.3.6.2 color patterns color patterns are enabled by selecting the color pattern mode in the gp_raster_mode register (gp memory offset 38h). in this mode, both of the gp_pat_data reg- isters and all six of the gp_pat_color registers are combined to provide a total of 256 bits of pattern. the num- ber of lines that the pattern can hold is dependent upon the number of bits per pixel. when performing a blt that needs a deeper color pattern than is supported (such as 8x8), software is responsible for breaking the blt into blocks such that the height of each block does not exceed the depth of the pattern. after each block is completed, software must update the patte rn registers before continu- ing with the next block of the blt. as a result of having a programmable stride value, it is now possible to reduce the number of passes required to perform a blt requiring a color pattern, by multiplying the stride value by the number of passes that are required to perform the blt. for exam- ple, in 8-bpp mode, where only an 8x4 pattern fits, the stride value could be doubled such that all of the even lines would be blted during the first pass, and all of the odd lines during the second pass. the pattern registers should be programmed with the even lines on the first pass and the odd lines on the second pas s, and the y offset value should be the start of the bitmap on the first pass and the start of the second line of the bitmap on the second pass. the algorithm can be extended to handle 8x2 and 8x1 pat- terns in four and eight passes. this only works, however, when the source and destination are non-overlapping. when performing an overlapping blt, it is necessary to fall back to breaking the blt into four, two, or one consecutive lines and reprogramming the pattern registers between each block. pattern transparency is not supported in color pattern mode. in 8-bpp mode, there is a total of four lines of pattern, each line with eight pixels as illustrated in table 6-17 on page 248 . table 6-16. example of monochrome pattern bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gp_pat_data_0[7:0] - 14h gp_pat_data_0[15:8] - 22h gp_pat_data_0[23:16] - 41h gp_pat_data_0[31:24] - 80h gp_pat_data_1[7:0] - 41h gp_pat_data_1[15:8] - 22h gp_pat_data_1[23:16] - 14h gp_pat_data_1[31:24] - 08h
248 amd geode? lx processors data book graphics processor 33234h in 16-bpp mode, there is a total of two lines of pattern, each line with eight pixels as illustrated in table 6-18. in 32-bpp mode, there is only one line of pattern with eight pixels. the orderi ng of the registers in the line from left to right is as f ol- lows: 1) gp_pat_color_5 2) gp_pat_color_4 3) gp_pat_color_3 4) gp_pat_color_2 5) gp_pat_color_1 6) gp_pat_color_0 7) gp_pat_data_1 8) gp_pat_data_0. table 6-17. example of 8-bit color pattern (3:3:2 format) byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 gp_pat_data_1 (02024002h) gp_pat_data_0 (40024002h) 02 02 40 02 40 02 40 02 gp_pat_color_1 (0240e340h) gp_pat_color_0 (0240e340h) 02 40 e3 403 02 40 e3 40 gp_pat_color_3 (40e300e3h) gp_pat_color_2 (40e300e3h) 40 e3 00 e3 40 e3 00 e3 gp_pat_color_5 (0240e340h) gp_pat_color_4 (0240e340h) 02 40 e3 40 02 40 e3 40 table 6-18. example of 16-bit color pattern (5:6:5 format) byte 15:14 byte 13:12 byte 11:10 byte 9:8 byte 7:6 byte 5:4 byte 3:2 byte 1:0 gp_pat_color_1 (00100010h) gp_pat_color_0 (40000010h) gp_pat_data_1 (02028002h) gp_pat_data_0 (80028002h) 0010 0010 4000 0010 4000 0010 4000 0010 gp_pat_color_5 (00104000h) gp_pat_color_4 (f81f4000h) gp_pat_color_3 (0280e380h) gp_pat_color_2 (0280e380h) 0010 4000 f81f 4000 0010 4000 f81f 4000
amd geode? lx processors data book 249 graphics processor 33234h 6.3.7 8x8 color patterns the new channel 3 hardware provides the capability of per- forming blts with 64 pixel color patterns at all color depths. to setup this mode, software first loads the pattern data into the lut beginning at address 100h the least sig- nificant byte of this first dword contains the upper left most pixel of the pattern. for 8-bpp mode, the most signifi- cant byte of the next dw ord contains the upper right most pixel of the pattern. in 16-bpp mode, the upper right most pixel is contained in the most significant bytes of the fourth dword, and for 32-bpp mode, the eighth dword contains the upper right most pi xel. the next line of the pat- tern begins at the dword that follows the last pixel of the previous line, such that the pattern is packed into the space required to hold it. so for 8-bpp mode, the top left pixel is in the least significant byte of the dword at address 100h in the lut, the top right pixel is in the most significant byte of the dword at address 101. the bottom left pixel is in the least significant byte of th e dword at address 10eh and the bottom right pixel is in the most significant byte of the dword at address 10fh. to enable this mode, the en and pm bits should be set in the gp_ch3_mode_str register (gp memory offset 64h[31, 21]): en, pm. the ps, hs, ro, x, and y bits should not be set in the gp_ch3_mode_str register. the bpp/fmt bits in the gp_ch3_mode_str register (bits [27:24]) indicate the color depth of the pattern data. if this does not match t he bpp/fmt bits in the gp_raster_mode register (gp memory offset 38h[31:28]), then the pattern is translated to the depth specified by the gp_raster_mode register. 6.3.8 source data when called for by the raster operation or alpha blender, software should set the source required bits in the gp_blt_mode register (gp memory offset 40h) so that source data is fetched from the frame buffer memory or can be written by the host to the gp_hst_src register (gp memory offset 48h). regardless of its origination, source data can either be monochrome (expanded to two colors) or color. the hardware aligns the incoming source data to the appropriate pixel lanes for writing to the destina- tion. source data is only used when in blt mode. in vector mode, gp_src_color_fg (gp memory offset 10h) is forced onto the source channel. 6.3.8.1 source data formats the graphics processor expects to see the left-most pixels on the screen in the least significant bytes of the dword and the right-most pixels in the most significant bytes. for monochrome data within a byte, the left-most pixels are in the most significant bits of the byte, and the right-most pix- els are in the least signific ant bits. these formats are shown more clearly in table 6-19, table 6-20, table 6-21, and table 6-22. table 6-19. 32-bpp 8:8:8:8 color data format byte 3 byte 2 byte 1 byte 0 alpha/unused red green blue table 6-20. 16-bpp color data format format byte 3 byte 2 byte 1 byte 0 right pixel data left pixel data 5:6:5 red green blue red green blue 4:4:4:4 alpha red green blue alpha red green blue 1:5:5:5 a red green blue a red green blue table 6-21. 8-bpp 3:3:2 color data format byte 3 byte 2 byte 1 byte 0 right pixel data (3:3:2) pixel 2 data pixel 1 data left pixel data (3:3:2) table 6-22. monochrome data format byte 3 byte 2 byte 1 byte 0 01234567012345670123456701234567 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 right most pixel left most pixel
250 amd geode? lx processors data book graphics processor 33234h 6.3.8.2 host source for source data that is not already in the frame buffer region of memory, software can use the gp_hst_src register (gp memory offset 48h) for loading the data into the graphics processor. this is achieved by selecting host source as the origination of the source data when setting up the blt. after writing to the gp_blt_mode register (gp memory offset 40h) to initiate the blt, software must first check to make sure that the host source blt is active by checking that the bp bit of the gp_blt_status regis- ter (gp memory offset 44h[0]) is not set before proceeding with successive writes to the gp_hst_src register (gp memory offset 48h). enough writes must be generated to complete the requested blt operation. any extra writes, or writes when host source data is not required, are ignored, not saved, and will not be used for the next blt. writes to this register are buffered into the source fifo to decouple the processor from the graphics processor. the source fifo is currently two cache lines deep, allowing the pro- cessor to load up to 64 bytes of data. if more data is needed, the driver can then poll the she (source fifo half empty) bit of the gp _blt_status register (gp memory offset 44h[3]). when this bit is set, the source fifo can accept at least one more cache line of data. writ- ing to the graphics processor while the host source fifo is full causes the graphics processor to drop the writes, which means that the blt is corrupt and most likely will not complete. since there is not enough host source data left, the graphics processor hangs waiting for more source data. the two lsbs of the source offset are used to deter- mine the starting byte of the host source data and the xlsbs are used in the case of monochrome source data to determine the starting bit. the starting pixel of the source data is aligned to the starting pixel of the destination data by the hardware. in monoch rome byte-packed mode, the hardware begins blting at the specified pixel, and after width pixels have been transferred, skips the remaining bits in the byte plus the number specified in xlsbs, and begins the next line at that location. in unpacked mono- chrome mode or color mode , the hardware discards any data remaining in the dword after width pixels have been transferred and begins the next line at the byte speci- fied by the two lsbs of the offset in the next dword received. examples of these two modes are shown in table 6-23 and table 6-24, with offset set to 0h, xlsbs set to 2h, and width set to 8h. table 6-23. example of byte-packed monochrome source data byte 3 byte 2 byte 1 byte 0 01234567012 3 45670123456701234567 16 17 101 1121314150607 00 01 02 03 04 05 36 37 30 31 32 33 34 35 26 27 20 21 22 23 24 25 56 57 50 51 52 53 54 55 46 47 40 41 42 43 44 45 skip specified by xlsbs trailing bits at end of line table 6-24. example of unpacked monochrome source data byte 3 byte 2 byte 1 byte 0 012345670123456701234567012 3 4567 06 07 00 01 02 03 04 05 16 17 101 112131415 26 27 20 21 22 23 24 25 skip specified by xlsbs trailing bits at end of line
amd geode? lx processors data book 251 graphics processor 33234h 6.3.8.3 source expansion the graphics processor contains hardware support for color expansion of monochrome source data. those pixels corresponding to a clear bit in the source data are rendered using the color specified in the gp_src_color_bg reg- ister (gp memory offset 14h), and the pixels that are set in the source data are rendered using the color specified in the gp_src_color_fg register (gp memory offset 10h). 6.3.8.4 source transparency if the source transparency bit is set in the gp_raster_mode register (gp memory offset 38h[11]), not all source pixels result in a write to the frame buffer. in monochrome mode, source pixels that are clear are inhibited from writing to the frame buffer, so only fore- ground colored pixels are written. in color mode, the source pixel is compared to the value stored in the gp_src_color_ fg register (gp memory offset 10h). the resulting compare is masked by the value in the gp_src_color_bg register (gp memory offset 14h), allowing color keying on specific channels within a pixel. if all the bits that ar e not masked compare with their corresponding bits in the gp_src_color_fg register, then the pixel write is inhibited. for example, to make all blue pixels transparent in 8-bpp mode, gp_src_color_fg is loaded with 03h (hardware expands this into four blue pixels) and gp_src_color_bg (gp memory offset 14h) is loaded with ffh (perform compare on all bits). to make all pixels transparent that have more than 50% in their alpha chan- nel for 32-bpp data, load gp_src_color_fg with 80000000h and gp_src_color_bg with 80000000h. 6.3.9 destination data when required by the raster operation or alpha blender, destination data is fetched from the frame buffer memory. this data is required to be in color at the depth specified (8, 16, or 32-bpp). source or pattern transparent mode does not necessarily require destination data to be fetched, since transparent pixels are i nhibited from being written to the frame buffer rather than re-written with the destination data. transparency is never keyed off of destination data. 6.3.10 raster operations (rop) the gp_raster_mode register (gp memory offset 38h) specifies how the patter n data, source data, and des- tination data are combined to produce the output from the graphics processor. the definition of the rop value matches that of the microsoft ? api. this allows microsoft windows ? display drivers to load the raster operation directly into hardware. see table 6-25 and table 6-26 for the definition of the rop value. table 6-25. gp_raster_mode bit patterns pattern (bit) source (bit) dest ination (bit) output (bit) 00 0 rop[0] 00 1 rop[1] 01 0 rop[2] 01 1 rop[3] 10 0 rop[4] 10 1 rop[5] 11 0 rop[6] 11 1 rop[7] table 6-26. common raster operations rop description f0h output = pattern cch output = source 5ah output = pattern xor destination 66h output = source xor destination 55h output = ~destination 33h output = ~source
252 amd geode? lx processors data book graphics processor 33234h 6.3.11 image compositing using alpha whereas the raster operation allows different streams of data to be logically combined, alpha channel composition allows two streams of data to be mathematically combined based on the contents of t heir alpha channel, which is an additional channel to the red, blue, and green data con- tained in the stream. the use of alpha channel composition allows the streams of data to be combined in more com- plex functions than that available from the raster operation. for example, assume that image a, containing a blue trian- gle, is to be combined with image b, containing a red trian- gle. these images can be combined such that image a sits on top of image b or vice versa. the alpha values in these images reflect the percentage of a given pixel that is cov- ered by the image. in image a, for instance, a pixel com- pletely within the triangle has an alpha value of 1, while a pixel completely outside of the triangle has an alpha value of 0. a pixel on the edge of the triangle has a value between 0 and 1 depending on how much of it is covered by the triangle. when combining these images such that a appears over b, pixels within the blue triangle appear blue, pixels outside the blue triangle but within the red triangle appear red, and pixels entirely outside of both triangles are black. pixels on the edge of either triangle have their color scaled by the percentage of the pixel that lies within the tri- angle. when working with images using alpha channels, it is assumed that each pixel of the entire image is premulti- plied by the alpha values at that pixel. this is assumed since every compositing operation on the data stream requires this multiplication. if an image has not been pre- multiplied, the graphics processor can perform this multi- plication in a single pass prior to setting up the composition operation. by setting up the graphics processor to fetch destination data, this operation can be done in-place with- out requiring a temporary storage location to hold the multi- plied image. once the image is premultiplied, it can be manipulated through alpha composition without ever hav- ing to perform this multiplication step again. table 6-27 describes the various ways that the two images can be composited using the alpha blender. for some of these cases, a third alpha value, in addition to the image stream data alphas is needed. this alpha, r , is specified in the gp_raster_mode register (gp memory offset 38h). the two channels specified, a and b, represent the two streams of image data being fetched by the graphics processor as source and destination data. use the cs bit to select whether channel a gets source data or destination data. channel b always gets the data not selected on channel a. note that if the combination of os and as bits in the gp_raster_mode register select data from one channel and from another, then both source and destina- tion data are required to correctly perform the blt. it is up to software to assure that the appropriate controls are set in the gp_blt_mode register (gp memory offset 40h) to fetch the required data. see section 6.3.10 "raster opera- tions (rop)" on page 251 for details on how to program these functions. alpha blending is not supported for 8-bpp color depth. for 16 and 32-bpp, the alpha unit supports all of the formats. note that the 0:5:6:5 format does not support an alpha channel with the data. when using 0:5:6:5, alpha must always be selected from the register or else it is the con- stant 1 (100%) and selecting a or b yields indeterminate results. to perform the premultiply of a given data stream, use the ?a? operation in table 6-27, but set the alpha select to a (as = 00) instead of 1. in this case, the enable bits should be set so that the operation only applies to the rgb values (en = 01). the operation ?a stop b? requires two passes through the alpha unit. the first pass creates an ?a in b? image and the second pass uses this intermediate image and performs an ?a over b? operation. the operation ?a xor b? requires three passes through the alpha unit. the first two perform ?b held out by a? on each image independently, and the final pass adds the two images together using ?a plus b.? the result of an alpha calculation is clamped at the maxi- mum pixel value. thus, if the result of a + (1- )b (the only calculation that could possibly overflow) does overflow in a given color channel, then the result for that channel is all 1s. table 6-27. alpha blending modes operation diagram f a f b description as bits os bits clear 0 0 resulting image is clear. a 1 ( ) 0 display only one of the images (or multiply an image by its alpha). 011 (00) 00 (00)
amd geode? lx processors data book 253 graphics processor 33234h a over b 1 1- display image a on top of image b. wherever image a is transpar- ent, display image b. 000 10 a in b b 0 use image b to mask image a. wherever image b is non-trans- parent, display image a. 001 00 b held out by a 01- a use image a to mask image b. wherever image a is transpar- ent, display image b. 000 01 a stop b b 1- a use image b to mask image a. display a if both images are non- transparent, otherwise display b. 001 000 00 10 a xor b 1- b 1- a display images only where they do not overlap. 001 000 01 10 darken a r 0 multiply rgb channels of image a by specified value. (use enables to apply to rgb.) 010 00 opaque a r 0 multiply channel of image a by a specified value. (use enables to apply to alpha.) 010 00 fade a r 0 multiply all channels of image a by a specified value. 010 00 fade a plus fade b r 1? r blend images a and b using r to specify percentage of a and b in the resulting image. 010 11 a plus b 1 1 add images a and b. 010 ( = 0) 10 table 6-27. alpha blending modes (continued) operation diagram f a f b description as bits os bits
254 amd geode? lx processors data book graphics processor register definitions 33234h 6.4 graphics processor register definitions the registers associated with the graphics processor (gp) are the standard geodelink? device (gld) msrs and graphics processor configuration registers. table 6-28 and table 6-29 are register summary tables that include reset values and page references where the bit descrip- tions are provided. the standard gld msrs (accessed via the rdmsr and wrmsr instructions) control the graphics processor?s behavior as a gliu module. these registers should be programmed at configuration time and left alone thereafter. they do not need to be modified by software to set up any of the graphics primitives. t he msrs are 64 bits wide, although not all bits are used in each register. unused bits marked as ?write as read? re turn the value that was last written to them. all other unused bits return 0. all of the gp registers are ac cessible by the cpu through memory mapped reads and writes on the gliu. note that due to the pipelining operation of the gp, the value returned during a read is the value stored in the slave reg- ister, while the value in the master register is the actual value being used by an ongoing blt or vector operation. also note that the command buffer has the ability to write into the slave registers. there is no reason, therefore, to read registers other th an the gp_blt_status, gp_int_cntrl, and command buffer registers while the command buffer is active. reserved bits, marked as ?write as read,? indicate that there is a real register ba cking those bits, which may be used in some future implementation of the gp. reserved register bits that do not have a register backing them always return a 0, regardless of what value software decides to write into them. the gp register space occupi es 4 kb of the memory map. the bottom 256 bytes are defined as access to gp?s pri- mary registers. the remainder of the lower 1k of address space is used to alias the host source register for the source channel, allowing rep movs access. the upper 3k of address space is used to alias the host source regis- ter for channel 3. this is the only aliasing that is supported by the gp, so all register accesses should use the full 12- bit offset. table 6-28. standard geodelink? device msrs summary msr address type register name reset value reference a0002000h ro gld capabilities msr (gld_msr_cap) 00000000_0003d4xxh page 256 a0002001h r/w gld master configuration msr (gld_msr_config) 00000000_00000000h page 256 a0002002h r/w gld smi msr (gld_msr_smi) 00000000_00000000h page 257 a0002003h r/w gld error msr (gld_msr_error) 00000000_00000000h page 257 a0002004h r/w gld power management msr (gld_msr_pm) 00000000_00000000h page 258 a0002005h r/w gld diagnostic msr (gld_msr_diag) 00000000_00000000h page 258 table 6-29. graphics processor configuration register summary gp memory offset type group register name reset value reference 00h r/w address config destination offset (gp_dst_offset) 00000000h page 259 04h r/w address config source offset (gp_src_offset) 00000000h page 259 04h r/w vector config vector error (gp_vec_err) 00000000h page 260 08h r/w address config stride (gp_stride) 00000000h page 260 0ch r/w blt config blt width/height (gp_wid_height) 00000000h page 261 0ch r/w vector config vector length (gp_vec_len) 00000000h page 261
amd geode? lx processors data book 255 graphics processor register definitions 33234h 10h r/w color config source color foreground (gp_src_color_fg) 00000000h page 262 14h r/w color config source color background (gp_src_color_bg) 00000000h page 263 18h-2ch r/w pattern config pattern color (gp_pat_color_x) 00000000h page 265 30h-34h r/w pattern config pattern data (gp_pat_data_x) 00000000h page 265 38h r/w blt config raster mode (gp_raster_mode) 00000000h page 265 3ch wo vector config vector mode (gp_vector_mode) 00000000h page 267 40h wo blt config blt mode (gp_blt_mode) 00000000h page 268 44h ro blt config status (gp_blt_status) 00000008h page 269 44h ro reset gen reset (gp_reset) none 48h wo blt data host source (gp_hst_src) xxxxxxxxh page 269 4ch r/w address config base offset (gp_base_offset) 01004010h page 270 50h r/w command buff command top (gp_cmd_top) 01000000h page 270 54h r/w command buff command bottom (gp_cmd_bot) 00ffffe0h page 271 58h r/w command buff command read (gp_cmd_read) 00000000h page 271 5ch r/w command buff command write (gp_cmd_write) 00000000h page 272 60h r/w channel3 offset (gp_ch3_offset) 00000000h page 272 64h r/w channel3 stride (gp_ch3_mode_str) 00000000h page 273 68h r/w channel3 width/height (gp_ch3_widhi) 00000000h page 275 6ch wo channel3 host source (gp_ch3_hsrc) xxxxxxxxh page 275 70h r/w channel3 lut index (gp_lut_index) 00000000h page 276 74h r/w channel3 lut data (gp_lut_data) xxxxxxxxh page 276 78h r/w interrupt control interrupt control (gp_int_cntrl) 0000ffffh page 277 3ff:100h wo blt data host source (gp_hst_src) (alias) xxxxxxxxh page 269 fff:400h wo channel3 host source (gp_ch3_hsrc) (alias) xxxxxxxxh page 275 table 6-29. graphics processor configuration register summary gp memory offset type group register name reset value reference
256 amd geode? lx processors data book graphics processor register definitions 33234h 6.4.1 standard geodelink? device (gld) msrs 6.4.1.1 gld capabilities msr (gld_msr_cap) this msr contains the revision and device ids for the particu lar implementation of the graphics processor. this register is read only. 6.4.1.2 gld master configur ation msr (gld_msr_config) this msr contains the gliu priority domain bits and priority level bits that are sent out to the gliu on every geodelink transaction. msr address a0002000h ty p e r o reset value 00000000_0003d4xxh gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd clkdom did rid gld_msr_cap bit descriptions bit name description 63:27 rsvd reserved. 26:24 clkdom clock domain. number of clock domains. the gp has one clock domain. 23:8 did device id. identifies device (03d4h). 7:0 rid revision id. identifies device revision. see amd geode? lx processors specification update document for value. msr address a0002001h ty p e r / w reset value 00000000_00000000h gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd cbase rsvd gld_msr_config bit descriptions bit name description 63:28 rsvd reserved. 27:16 cbase command buffer base. 16m region aligned to 1m boundary. see section 6.3.1 "com- mand buffer" on page 239 for details. 15:0 rsvd reserved.
amd geode? lx processors data book 257 graphics processor register definitions 33234h 6.4.1.3 gld smi msr (gld_msr_smi) this msr contains the smi and mask bits for the gp. an smi is asserted whenever an illegal address or an illegal type is detected on the gliu and the mask bit is not set. this also causes the mb_p_asmi output to be asserted. this signal remains asserted until the smi is cleared or the mask bit is set. an illegal address is defined as a memory mapped access to an address offset greater than 07fh or an msr access to an address greater than 20000007h. an illegal type is flagged if the gp receives a transaction whose type is not on e of the following: ncoh_read, ncoh_write, ncoh_read_bex, msr_read, msr_write, bex, null. 6.4.1.4 gld error msr (gld_msr_error) this msr contains the errors and mask bits for the gp. an error is asserted whenever an illegal address or an illegal type is detected on the gliu and the mask bit is not set. this also causes the internal mb_p_asmi output to be asserted if the mask bit (msr a0002002h[0]) is not set. the error bits remain asserted until they are cleared. an illegal address is defined as a memory mapped access to an address offset greater than 07fh or an msr access to an address greater than 20000007h. an illegal type is flagged if the gp receives a tr ansaction whose type is not o ne of the following: ncoh_read, ncoh_write, ncoh_read_bex, ms r_read, msr_write, bex, null. msr address a0002002h ty p e r / w reset value 00000000_00000000h gld_msr_smi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd s 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd m gld_msr_smi bit descriptions bit name description 63:33 rsvd reserved. read returns 0. 32 s smi. indicates address or type violation. wr ite = 1 clears bit, write = 0 has no effect. 31:1 rsvd reserved. read returns 0. 0m mask. ignore address and type violations when set; also disable asmi output. msr address a0002003h ty p e r / w reset value 00000000_00000000h gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 3130292827262524232221201918171615141312111098765432 1 0 rsvd ae te rsvd am tm
258 amd geode? lx processors data book graphics processor register definitions 33234h 6.4.1.5 gld power management msr (gld_msr_pm) this msr contains the power management controls for the gp . since there is only one clock domain within the gp, most bits in this register are unused. this register allows the gp to be switched off by disabling the clocks to this block. if hard - ware clock gating is enabled, the gp will turn off its clocks whenever there is no blt busy or pending and no gliu transac- tions destined to the gp. a register or msr write causes the gp to wake up temporarily to service the request, then return to power down. a write to the gp_b lit_mode or gp_vector_mode regist ers (gp memory offset 40h and 3ch respectively) causes the gp to wake up for the duration of the requ ested operation. if software clock gating is enabled, a write to the prq bit causes the gp to stop its clocks the next ti me that it is idle. it automatic ally wakes itself up when it i s busy again, clearing the prq bit. 6.4.1.6 gld diagnostic msr (gld_msr_diag) this register is reserved for internal use by amd and should not be written to. gld_msr_error bit descriptions bit name description 63:18 rsvd reserved. read returns 0. 17 ae address error. 1 indicates address violation. write = 1 clears bit, write = 0 has no effect. 16 te type error. 1 indicates type error. write = 1 clears bit, write = 0 has no effect. 15:2 rsvd reserved. read returns 0. 1am address mask. ignore address violations when set. 0tm type mask. ignore type violations when set. msr address a0002004h ty p e r / w reset value 00000000_00000000h gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd prq 313029282726252423222120191817161514131211109876543210 rsvd pm gld_msr_pm bit descriptions bit name description 63:33 rsvd reserved. read returns 0. 32 prq software power request. if software clock gating is enabled, disable the clocks the next time the device is not busy. this bit is cleared when the device wakes up. 31:2 rsvd reserved. read returns 0. 1:0 pm power mode. 00: disable clock gating. clocks are always on. 01: enable active hardware clock gating. 10: enable software clock gating. 11: enable hardware and software clock gating. msr address a0002005h ty p e r / w reset value 00000000_00000000h
amd geode? lx processors data book 259 graphics processor register definitions 33234h 6.4.2 graphics processor configuration registers 6.4.2.1 destination of fset (gp_dst_offset) gp_dst_offset is used to give a starting location for the des tination of a blt or vector in the destination region of mem- ory. it consists of three fields, the offset, xlsbs and ylsbs . the offset is a pointer, wh ich when added to the desti- nation base address, gives the memory address of the first byte of the blt or vector. for a left-to-right direction blt or a vector, the address should be aligned to the least significant byte of the first pixel, since this is the leftmost byte. for a right- to-left direction blt, the address should be aligned to the most significant byte of the first pixel, since this is the rightmo st byte of the blt. the address alignment must also be correct with respect to the pixel depth. in 32-bpp mode, the address specified must be aligned to the least significant or most si gnificant byte of a dword, depending upon blt direction. pix- els may not straddle a dword boundary. in 16-bpp mode, the address specified must be aligned to a 16-bit boundary. the xlsbs and ylsbs are used to inform the hardwa re of the location of the pixel within the pattern memory for pattern align- ment. 6.4.2.2 source offset (gp_src_offset) gp_src_offset is used during a blt to give a starting locati on for the source in the source region of memory. in this mode, the register consists of two fi elds, the offset and xlsbs. the offset is a pointer, which when added to the source base address, gives the memory location of the byte cont aining the first pixel of the blt. as in the destination offset, this value must be aligned correctly for blt direction and pixe l depth. when host source data is used, the two lsbs of the offset must still be initialized with the byte location of the first source pi xel in the host source data stream. the xlsbs are used when the source is monochrome to give an offset wit hin the specified byte to the bit representing the starting pixel. in byte-packed mode, the xlsbs are used to index into the first byte of every new line of source data. in unpacked mode, both the offset and xlsbs are used to index into th e first dword of every new line of source data. gp memory offset 00h ty p e r / w reset value 00000000h gp_dst_offset register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ylsbs xlsbs rsvd offset gp_dst_offset bit descriptions bit name description 31:29 ylsbs y lsbs. indicates y coordinate of starting pixel within pattern memory. 28:26 xlsbs x lsbs. indicates x coordinate of starting pixel within pattern memory. 25:24 rsvd reserved. write as read. 23:0 offset offset. offset from the destination base address to the first destination pixel. gp memory offset 04h ty p e r / w reset value 00000000h gp_src_offset register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd xlsbs rsvd offset gp_src_offset bit descriptions bit name description 31:29 rsvd reserved. write as read. 28:26 xlsbs x lsbs. offset within byte to first monochrome pixel.
260 amd geode? lx processors data book graphics processor register definitions 33234h 6.4.2.3 vector error (gp_vec_err) this register specifies the axial and diagonal error terms us ed by the bresenham vector algorithm. gp_vec_err shares the same storage space as gp_src_offset and thus a write to one of these registers will be reflected in both, since they both have the same offset. the name change is only for documentation purposes. 6.4.2.4 stride (gp_stride) the gp_stride register is used to indica te the byte width of the destination and source images. whenever the y coordi- nate is incremented, this value is added to the previous start address to generate the start address for the next line. stride values up to 64 kb minus one are supported. adding the gp_s tride to the offset gives the byte address for the first pixel of the next line of a blt. in the case of monochro me source, the xlsbs specified in the gp_src_offset register are used to index into the first byte of every line to extract the first pixel. note that the display controller may not support variable strides for on-screen space, especially when compression is enabled. refer to dc memory offset 034h[15:0] for frame buffer pi tch. display controller restri ctions do not apply to source stride. when copying from on-screen frame buffer space (e.g., wi ndow move), the values of s_ stride and d_stride should match. when copying from off-screen space, s_stride should be the number of bytes to add to get from one line in the source bitmap to the next. this allows software to linearly pack a bitmap into off-screen space (e.g., for an 800x600 mono- chrome bitmap packed linearly into off-screen space, bytes per line is 100 , so s_stride should be written with 100). 25:24 rsvd reserved. write as read. 23:0 offset offset. offset from the source base address to the first source pixel. gp memory offset 04h ty p e r / w reset value 00000000h gp_src_offset bit descriptions (continued) bit name description gp_vec_err register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a_err d_err gp_vec_err bit description bit name description 31:16 a_err axial error term. axial error term (2?s complement format). 15:0 d_err diagonal error term. diagonal error term (2?s complement format). gp memory offset 08h ty p e r / w reset value 00000000h gp_stride register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s_stride d_stride
amd geode? lx processors data book 261 graphics processor register definitions 33234h 6.4.2.5 blt width/heig ht (gp_wid_height) this register is used to specify the width and the height of the blt in pixels. note that operations that extend beyond the bounds of the frame buffer space ?wrap? into the other end of the frame buffer. 6.4.2.6 vector length (gp_vec_len) this register is used to specify the length of the vector in pixels and the initial e rror term. note that this is the same regi ster as gp_wid_height, and that writing to one overwrites the other. they are separa ted for documentation purposes. as with blt operations, vectors that extend below or above the frame buffer space wrap to the other end of the frame buffer. gp_stride bit descriptions bit name description 31:16 s_stride source stride. width of the source bitmap (in bytes). 15:0 d_stride destination stride. width of the destination scan line (in bytes). gp memory offset 0ch ty p e r / w reset value 00000000h gp_wid_height register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd wid rsvd hi gp_wid_height bit descriptions bit name description 31:28 rsvd reserved. write as read. 27:16 wid width. width in pixels of the blt operation. 15:12 rsvd reserved. write as read. 11:0 hi height. height in pixels of the blt operation. gp memory offset 0ch ty p e r / w reset value 00000000h gp_vec_len register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd len i_err gp_vec_len bit descriptions bit name description 31:28 rsvd reserved. write as read. 27:16 len length. length of the vector in pixels. 15:0 i_err initial error. initial error for re ndering a vector (2?s complement format).
262 amd geode? lx processors data book graphics processor register definitions 33234h 6.4.2.7 source color foreground (gp_src_color_fg) when source data is monochrome, the contents of this regist er are used for expanding pixe ls that are set in the mono- chrome bitmap, thus replacing the monochrome bit with a color that is appropriatel y sized for the destination. when source data is color, this register contains the color ke y for transparency. the value(s) in this register is xor?ed with the color source data, after which the gp_src_color_bg regist er (gp memory offset 14h) is used to mask out bits that are don?t cares. if all bits of a pixel that are not masked o ff compare, and source transparency is enabled, then the write of that pixel will be inhibited and the frame buffer data will be unchanged. otherwise, the frame buffer will be written with the color data resulting from the raster operation. if no source is required for a given blt, the value of this regist er is used as the default source data into the raster operati on. this register should only be written after setting the bpp in gp_raster_mode (gp memory offset 38h), since the value written is replicated as necessary to fill the register. thus a write to this register in 8-bpp mode takes the least significan t data byte and replicates it in the four bytes of the register. in 16 -bpp mode, the least significan t two bytes are replicated i n the upper half of the register. a read returns the replicated data. gp memory offset 10h ty p e r / w reset value 00000000h gp_src_color_fg register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 src _fg gp_src_color_fg bit descriptions bit name description 31:0 src_fg source foreground. mono source mode: foreground source color. color source mode: color key for transparency.
amd geode? lx processors data book 263 graphics processor register definitions 33234h 6.4.2.8 source color backgr ound (gp_src_color_bg) when source data is monochrome, the contents of this regi ster are used for expanding pixels that are clear in the mono- chrome bitmap, thus replacing the monochrome bit with a color that is appropriatel y sized for the destination. when source data is color, this register contains the color key mask for transparency. the value(s) in this register are inverted and or?ed with the result of the compare of the source data and the gp_src_color_fg register. thus, a bit that is clear implies that bit position is a don?t care for transparency, and a bit that is set implies that bit position must match in both the source data and gp_src_color_ fg register. if the result of the or pr oduces all ones for an entire pixel and transparency is enabled, then the write of that pixe l is inhibited and the destination data is unchanged. this register should only be written after setting the bpp/fmt bits in gp_raster_mode (gp memory offset 38h[31:28]), since the value written is repl icated as necessary to fill the register. t hus a write to this register in 8-bpp mo de takes the least significant data byte and replicates it in all four bytes of the register. in 16-bpp mode, the least significan t two bytes are replicated in the upper half of the register. a read returns the replicated data. gp memory offset 14h ty p e r / w reset value 00000000h gp_src_color_bg register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 src _bg gp_src_color_bg bit descriptions bit name description 31:0 src_bg source background. mono source mode: background source color. color source mode: color key mask for transparency.
264 amd geode? lx processors data book graphics processor register definitions 33234h 6.4.2.9 pattern color (gp_pat_color_x) in solid pattern mode, the pattern hardware is disabled and gp_pat_color_0 is selected as the input to the raster oper- ation. in monochrome pattern mode, gp_pat_color_0 and gp_pat_color_1 are used for expanding the monochrome pat- tern into color. a clear bit in the pattern is replaced with th e color stored in gp_pat_color_0 and a set bit in the pattern is replaced with the color stored in gp_pat_color_1. in color pattern mode, these registers each hold part of the pattern according to table 6-30. these registers should only be written after setting the bpp/fmt and pm bits in gp_raster_mode (gp memory offset 38h[31:28, 9:8]), since the value written may be replicated if necessary to fill the register. if the pattern is color, no repl ica- tion is performed and the data is written to the registers exactly as it is received. if the pattern is monochrome, the write data is expanded if the color depth is le ss than 32-bpp. thus a write to these re gisters in 8-bpp monochrome pattern mode takes the least significant data byte and replicates it in the four bytes of the register. in 16-bpp monochrome pattern mode, the least significant two bytes are replicated in the upper half of the register. a read returns the replicated data. gp memory offset 18h gp_pat_color_0 1ch gp_pat_color_1 20h gp_pat_color_2 24h gp_pat_color_3 28h gp_pat_color_4 2ch gp_pat_color_5 ty p e r / w reset value 00000000h table 6-30. pat_color usage for color patterns register 8-bpp mode 16-bpp mode 32-bpp mode gp_pat_color_0 line 1, pixels 3-0 line 0, pixels 5-4 line 0, pixel 2 gp_pat_color_1 line 1, pixels 7-4 line 0, pixels 7-6 line 0, pixel 3 gp_pat_color_2 line 2, pixels 3-0 line 1, pixels 1-0 line 0, pixel 4 gp_pat_color_3 line 2, pixels 7-4 line 1, pixels 3-2 line 0, pixel 5 gp_pat_color_4 line 3, pixels 3-0 line 1, pixels 5-4 line 0, pixel 6 gp_pat_color_5 line 3, pixels 7-4 line 1, pixels 7-6 line 0, pixel 7 gp_pat_color_x register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pat_color_x gp_pat_color_x bit descriptions bit name description 31:0 pat_color_x pattern color x. mono pattern mode: pattern color for expansion. color pattern mode: color pattern.
amd geode? lx processors data book 265 graphics processor register definitions 33234h 6.4.2.10 pattern data (gp_pat_data_x) in solid pattern mode, these registers are not used. in monochrome pattern mode, gp_pat_data_0 and gp_pat_d ata_1 combine to hold the entire 8x8 pattern (64 bits). gp_pat_data_0[7:0] is the first line of the pattern, with bit 7 correspond ing to the leftmost pixel on the screen. gp_pat_data_1[31:24] is the last line of the pattern. in color pattern mode, these registers each hold part of the pattern according to table 6-31. 6.4.2.11 raster mode (gp_raster_mode) this register controls the manipulation of the pixel data through the graphics pipelin e. refer to section section 6.3.10 "ras- ter operations (rop)" on page 251 for more information on the functionality of the rop and section 6.3.11 "image com- positing using alpha" on page 252 for information on alpha blending and compositing. this register is byte writable to allow modification of the rop and other control bits wit hout having to rewrite the bpp and fmt every time. gp memory offset 30h gp_pat_data_0 34h gp_pat_data_1 ty p e r / w reset value 00000000h table 6-31. pat_data usage for color patterns register 8-bpp mode 16-bpp mode 32-bpp mode gp_pat_data_0 line 0, pixels 3-0 line 0, pixels 1-0 line 0, pixel 0 gp_pat_data_1 line 0, pixels 7-4 line 0, pixels 3-2 line 0, pixel 1 gp_pat_data_x register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pat _ data _ x gp_pat_data_x bit descriptions bit name description 3 1 : 0 pat _ data _ x pattern data x. mono pattern mode: pattern data. color pattern mode: color pattern. gp memory offset 38h ty p e r / w reset value 00000000h gp_raster_mode register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bpp/fmt rsvd en os as cs rsvd si pi st pt pm rop/a r
266 amd geode? lx processors data book graphics processor register definitions 33234h gp_raster_mode bit descriptions bit name description 31:28 bpp/fmt color depth and format. 0000: 8-bpp, 3:3:2 format. 0100: 16-bpp, 4:4:4:4 format. 0101: 16-bpp, 1:5:5:5 format. 0110: 16-bpp, 0:5:6:5 format. 1000: 32-bpp, 8:8:8:8 format. all others: undefined. 27:24 rsvd reserved. write as read. 23:22 en alpha enable bits. also used to select how to apply the specified operation. 00: alpha disabled/rop enabled. 01: alpha operation applies to only the rgb values of the pixel. output alpha is from channel b if the os is 01; otherwise from channel a. 10: alpha operation applies to only the alpha of the pixel. output rgb is from channel b if the os is 01; otherwise from channel a. 11: alpha operation applies to all channels of the pixel (argb). 21:20 os alpha operat ion select. determines the alpha operation to be performed if enabled. 00: a ? a. 01: (1-a)*b. 10: a + (1-a)*b. 11: a ? a + (1-a)*b. * channel a is added in this case only if the selected is also from channel a. 19:17 as alpha select. chooses which alpha value to use for the multiplication. 000: a a 100: color a 001: a b 101: color b 010: a r 110: a r 011: constant 1 111: constant 1 16 cs channel select. determines which data stream gets put on which channel. 0: a is source, b is destination. 1: a is destination, b is source. 15:14 rsvd reserved. write as read. 13 si source invert. inverts the sense of monochrome source data. 12 pi pattern invert. inverts the sense of monochrome pattern data. 11 st source transparency. enables transparency for monochrome source data and color keying for color source data. 0: disable. 1: enable. 10 pt pattern transparency. enables transparency for monochrome pattern data. 0: disable. 1: enable. 9:8 pm pattern mode. specifies the format of the pattern data. 00: solid pattern. pattern data always sourced from gp_pat_color_0 (gp memory offset 18h). 01: mono pattern. 10: color pattern. 11: undefined.
amd geode? lx processors data book 267 graphics processor register definitions 33234h 6.4.2.12 vector mode (gp_vector_mode) writing to this register configures the vector mode and initiates the rendering of the vector. if a blt or vector operation is already in progress when this register is written, the blt pending bit in gp_blt_status (gp memory offset 44h)is set and the vector is queued to begin when the current operation is complete. software should not write to any register (other than gp_host_src if required) while the blt pending bit is set since it will corrupt the pendi ng vector operation. setting the th bit causes the vector operation to wait until the next vblank before beginning rendering. software may still queue another operation behind a throttled vector as long as the blt pending bit is clear. 7:0 rop/a r raster operations (rop). combination rule for source, pattern and destination when performing raster operations. (see section 6. 3.10 "raster operations (rop)" on page 251.) alpha value (a r ). alpha value that can be used for so me of the alpha compositing oper- ations. gp memory offset 3ch ty p e w o reset value 00000000h gp_raster_mode bit descriptions (continued) bit name description gp_vector_mode register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd cp th dr dn dj yj gp_vector_mode bit descriptions bit name description 31:6 rsvd reserved. write to 0. 5cp checkpoint. generates interrupt when this vector is completed if checkpoint interrupt is enabled. 4th throttle. 0: operation begins immediately. 1: operation waits until next vblank before beginning. 3dr destination required. 0: destination data is not needed for operation. 1: destination data is needed from frame buffer. 2dn minor direction. 0: negative minor axis step. 1: positive minor axis step. 1dj major direction. 0: negative major axis step. 1: positive major axis step 0yj y major. 0: x major vector. 1: y major vector.
268 amd geode? lx processors data book graphics processor register definitions 33234h 6.4.2.13 blt mode (gp_blt_mode) writing to this register configures the blt mode and initiates t he rendering of the blt. if a bl t or vector operation is alread y in progress when this register is writte n, the blt pending bit in gp_blt_status (gp memory offset 44h) is set and the blt is queued to begin when the current operation is complete . software should not write to any register (other than gp_host_src if required) while the blt pending bit is set sinc e it will corrupt the pending blt. setting the th bit causes the blt operation to wait until the next vblank before b eginning. software may still queue another operation behind a throttled blt as long as the blt pending bit is clear. gp memory offset 40h ty p e w o reset value 00000000h gp_blt_mode register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd cp th x y sm rsvd dr sr gp_blt_mode bit descriptions bit name description 31:12 rsvd reserved. write to 0. 11 cp checkpoint. generates interrupt when this blt is completed if checkpoint interrupt is enabled. 10 th throttle. blt does not begin until next vblank. 0: disable. 1: enable. 9x x direction. 0: indicates a positive increment for the x position. 1: indicates a negative increment for the x position. 8y y direction. 0: indicates a positive increment for the y position. 1: indicates a negative increment for the y position. 7:6 sm source mode. specifies the format of the source data. 00: source is color bitmap. 01: source is unpacked monochrome. 10: source is byte-packed monochrome. 11: undefined. 5:3 rsvd reserved. write as read. 2dr destination required. 0: no destination data is required. 1: indicates that destination data is needed from frame buffer. 1:0 sr source required. 00: no source data. 01: source from frame buffer. 10: source from gp_hst_src regi ster (gp memory offset 48h). 11: undefined.
amd geode? lx processors data book 269 graphics processor register definitions 33234h 6.4.2.14 status and reset (gp_blt_status, gp_reset) this register is used to provide software with the current st atus of the gp in regards to operations pending and currently executing. a write to this register has no effect unless byte 3 is 69h, which causes a reset of the gp, losing all state inform a- tion and discarding any active or pending blt or vector. this is only intended to be used during debug to restore the gp in the event of a hang. it is not required as part of the initialization or power on sequence for gp. 6.4.2.15 host source (gp_hst_src) this register is used by software to l oad source data that is not originated in the frame buffer memory region. when per- forming a blt that requires host source data, software should first set up all of the configurat ion registers that are required and initiate the blt by writing to the gp_blt_mode register (gp memory offset 40h). this initiates the blt in hardware, which then waits for writes to the gp_hst_src register. softw are should then perform enough writes to this register to complete the blt operation. writes to th is register are moved immediately into the source fifo, allowing the cpu to per- form successive writes. the eh bit in the gp_blt_status (gp memory offset 44h[5]) register indicates that the gp can accept another cache line (32 bytes) of data. this register is also aliased to the a ddress range 100h-3ffh to allow the processo r to move large blocks of data to the gp through the repeat movs instruction. t he gp throttles the incoming data by holding off register writes on the gliu when the source fifo is full. gp memory offset 44h ty p e r o reset value 00000008h gp_blt_status register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd uf rp eh ce she pp in pb gp_blt_status bit descriptions bit name description 31:8 rsvd reserved. 7uf underflow. if bit is set, channel 3 had too few pixels to complete the blt. 6rp read pending. if bit is set, read request is waiting for data from gliu. 5eh expecting host source data. if bit is set, current blt is expecting to receive host source data on channel 3. 4ce command buffer empty. if bit is set, read and write pointers are equal. 3she source fifo half empty. if bit is set, source fifo can accept another cache line of host source data. 2pp primitive pending. if bit is set, a second blt or vector is in the queue behind the currently executing operation. 1in interrupt pending. if bit is set, the gp interrupt signal is active. 0pb primative busy. if bit is set, an operation is currently executing in the gp. gp memory offset 48h ty p e w o reset value xxxxxxxxh gp_hst_src register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hst_src
270 amd geode? lx processors data book graphics processor register definitions 33234h 6.4.2.16 base offset (gp_base_offset) this register is used to define the physical base addresses of the regions used for all gp read and write operations to mem- ory. each base defines a 16 mb region that begins on a 4 mb boundary. thus the top two bits of the offset [23:22] are added to the base to identify the correct 4 mb region in me mory for a given transfer. because there are different bases defined for each potential source of data, each can come fr om a different memory region. if a memory operation goes beyond the 16 mb region that has been assigned, it wraps back to the beginning of the 16 mb region. 6.4.2.17 command top (gp_cmd_top) this register defines the starting address of the command buffer within the command buffer region. bits [23:0] of this regis- ter are combined with the cbase in gld_ msr_config (msr a0002001h) to form the 32-bit address. this register should only be changed when the gp is not actively executin g out of the command buffer, which can be checked by reading the ce bit in the gp_blt_status register (gp memory offs et 44h[4]) or by verifying that gp_cmd_read (gp memory offset 58h) and gp_cmd_write (gp memo ry offset 5ch) have the same value. gp_hst_src bit descriptions bit name description 31:0 hst_src host source data. used during blt in host source mode. gp memory offset 4ch ty p e r / w reset value 01004010h gp_base_offset register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dbase sbase ch3base rsvd gp_base_offset bit descriptions bit name description 31:22 dbase destination base. base address of destination data region in physical memory. 21:12 sbase source base. base address of source data region in physical memory. 11:2 ch3base channel 3 base. base address of channel 3 data region in physical memory. 1:0 rsvd reserved. gp memory offset 50h ty p e r / w reset value 01000000h gp_cmd_top register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd cmd_top rsvd gp_cmd_top bit descriptions bit name description 31:24 rsvd reserved. read returns 0. 23:5 cmd_top command top. starting address of the command buffer in the command buffer region. 4:0 rsvd reserved. read returns 0.
amd geode? lx processors data book 271 graphics processor register definitions 33234h 6.4.2.18 command bo ttom (gp_cmd_bot) this register defines the ending address of the command buffer wit hin the command buffer region. bits [23:0] of this register are combined with the cbase in gld_msr_config (msr a 0002001h) to form t he 32 bit address. th is register should only be changed when the gp is not actively executing out of the command buffer, which can be checked by reading the ce bit in gp_blt_status (gp memory offset 44h[4]) or by verifying that gp_cmd_read and gp_cmd_write (gp mem- ory offset 58h and 5ch respectively) have the same value. 6.4.2.19 command read (gp_cmd_read) this register points to the location from wh ich the gp fetches the next command buffer data. as data is fetched, this register increments. when this register equals gp_cmd_bot (gp me mory offset 54h) and the data has been fetched, it is reloaded with the value from gp_cmd_top (gp memory offset 50h). if the current command buffer had the w (wrap) bit set in the command word, then this register is reset to gp _cmd_top after the execution of the current command buffer. typically, this register is read only by the software, and is used in combination with gp _cmd_write (gp memory offset 5ch) to determine how much space is available in the command buffer for new commands. however, this register can be written. a write to this register also affects the gp_cmd_write register such t hat when creating and initializing a new command buffer in memory, the read and write pointers can be updated simultaneously to point to the beginning of the buffer without the gp thinking that the bu ffer was non-empty and beginning to fetch. this register must not be written while the gp is actually executing command buff ers as this could cause the gp to hang. gp memory offset 54h ty p e r / w reset value 00ffffe0h gp_cmd_bot register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd cmd_bot rsvd gp_cmd_bot bit descriptions bit name description 31:24 rsvd reserved. read returns 0. 23:5 cmd_bot command bottom. ending address of the command buffer in the command buffer region. 4:0 rsvd reserved. read returns 0. gp memory offset 58h ty p e r / w reset value 00000000h gp_cmd_read register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd cmd_read gp_cmd_read bit descriptions bit name description 31:24 rsvd reserved. read returns 0. 23:0 cmd_read command read. pointer to the tail of the command buffer in the command buffer region.
272 amd geode? lx processors data book graphics processor register definitions 33234h 6.4.2.20 command wr ite (gp_cmd_write) this register points to the next location to be written wit h command buffer data from the processor. after the processor writes out a complete command buffer starting at this address, it should write to this register to update the value to point to the next location to be written. this wr ite is what queues the gp that there is co mmand buffer data that needs to be fetched and activates the command buffer logic within gp. if the wrap bit is set in a command buffer control word, this register should be written with the same value as that found in gp_cmd_top (gp memory offset 50h) after the cpu has com- pleted loading the command buffer in memory. 6.4.2.21 offset (gp_ch3_offset) the gp_ch3_offset register is used during a blt to give a starting location for the blt data in the channel 3 region of memory. the register consists of two fields to compose th e address, the offset and nibble select. the offset field is a pointer, which when added to the channel 3 base address, give s the memory location of the byte containing the first pixel of the blt. as in the destination and sour ce offsets, this value must be aligned correctly for blt direction and pixel depth. when host source data is used, the two lsbs of offset must still be initialized with the byte location of the first source pixel in the host source data stream. nibble select is used wh en the source is 4-bpp, to give an offset within the specified byte to the nibble representing the starti ng pixel. both the offset lsbs and nibble select are used to index into the first dword of every new line of source data. for a rotation of 90 counterclockw ise, the offset should point to the top rightm ost byte of the source bitmap. for a rotation of 90 clockwise, the offset should point to the bottom leftmost byte of the source bitmap. for a rotation of 180, the offset should point to the opposite corner from that pointed to by the destination offset (e.g., if gp_blt_mode (gp memory off- set 40h) indicates a left to right, top to bottom fill, then the de stination offset should point to the upper left corner and t he channel 3 offset should point to the botto m right most byte of the source bitmap). gp memory offset 5ch ty p e r / w reset value 00000000h gp_cmd_write register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd cmd_write gp_cmd_write bit descriptions bit name description 31:24 rsvd reserved. read returns 0. 23:0 cmd_write command write. pointer to where the next command buffer will be written in the com- mand buffer region. gp memory offset 60h ty p e r / w reset value 00000000h gp_ch3_offset register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ylsbs xlsbs n rsvd offset
amd geode? lx processors data book 273 graphics processor register definitions 33234h 6.4.2.22 stride (gp_ch3_mode_str) the gp_ ch3_mode_str register has multiple uses. the stride field is used to indicate the byte width of the channel 3 bitmaps. whenever the y coordinate is incremented, this value is added (or subtracted if the y bit is set) to (from) the previ- ous start address to generate the start address for the next line. stride values up to 64 kb minus one are supported. the remaining fields of this register describe the type, size and source of the channel 3 data. the output of channel 3 can be used to replace either source or pattern data into the rop unit. the ps bit is used to select which pipeline the data will be placed on. if the fmt indicates that the incoming data is al pha, then the incoming data can be used as alpha data in the alpha blend unit if the as bits in the gp_raster_mode (gp me mory offset 38h[19:17]) regi ster are set to 110. if the bpp/fmt bits in the gp_raster_mode register (bits [31:28]) indica te the output pixel is 32-bp p, then the incoming alpha data is converted to 8 bits and is consum ed at the rate of one pixel per clock. if the bpp/fmt bits are set for 16-bpp, then the incoming alpha data is converted to 4 bits and is consumed at the rate of two pixels per clock. alpha blending is not sup- ported in 8-bpp mode. some operating systems store color data in reverse color order (blue/green/red). this data can be converted into the cor- rect display order by setting the bgr bit. this works for all i nput formats except for alpha, so if the incoming data is alpha, do not set this bit. rotation is controlled by the ro bit. if this bit is set, the direction of rotation is determined by the x and y bits. when thi s bit is set, the gp_dst_offse t (gp memory offset 00h) should point to the upper left corner of the destination and the x and y bits in the gp_blt_mode (gp memory offset 40h[9,8] ) should not be set. the output must be left to right, top to bottom. the output is actually written in horizontal strips, 8, 16 or 32 pixels high and as wide as the output. for 8-bpp rota- tion, 1k of buffer space is the minimum required to perform the operation. having 2k available allows data to be prefetched while the previous tile is being written out. setting the pl bit limits the buffer size to 1k as it preserves the lut data in t he other 1k of the buffer. this bit should be set when performing any indexed color blt or if it is likely that the lut data that has been loaded will be needed again for a future blt. the performance is higher when this bit is not set. gp_ch3_offset bit descriptions bit name description 31:29 ylsbs ylsbs. y coordinate of starting pixe l within color pattern memory. 28:26 xlsbs xlsbs. x coordinate of starting pixe l within color pattern memory. 25 n nibble select. nibble address for 4-bpp pixels/alpha. 0 starts at the leftmost nibble, 1 starts at the rightmost. 24 rsvd reserved. write as read. 23:0 offset offset. offset from the channel 3 base address to the first source pixel. gp memory offset 64h ty p e r / w reset value 00000000h gp_ch3_mode_str register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en ps x y bpp/fmt ro bgr pm pl pe hs rsvd stride gp_ch3_mode_str bit descriptions bit name description 31 en enable. 0: channel 3 is off. old pipelines behave exactly as they used to. 1: channel 3 is on. data is forced into eit her source or pattern pipeline from channel 3. 30 ps pipeline select. 0: channel 3 data directed to /replaces old pattern pipeline. 1: channel 3 data directed to/replaces old source pipeline
274 amd geode? lx processors data book graphics processor register definitions 33234h 29 x x direction for fetch. data is reversed if fetch direction does not match destination direction. 0: left to right direction. 1: right to left direction. 28 y y direction for fetch. data is reversed if fetch direction does not match destination direction. 0: top to bottom direction. 1: bottom to top direction. 27:24 bpp/fmt color depth and format of input. 0000: 8-bpp 3:3:2. 0001: 8-bpp indexed. 0010: 8-bpp alpha. 0100: 16-bpp 4:4:4:4. 0110: 16-bpp 0:5:6:5. 0111: 4:2:2 yuv. 1000: 32-bpp. 1011: 24-bpp packed. 1101: 4-bpp indexed. 1110: 4-bpp alpha. all others: undefined. 23 ro rotate bitmap. 0: disable rotation. 1: enable rotation direction determined by x and y. see section 6.3.2.1 "rotating blts" on page 242. 22 bgr bgr mode (applies only when 16-bpp or 32-bpp). 0: pass through (or yuy2 for 4:2:2 mode). 1: swap red and blue channels on output (or uyvy for 4:2:2 mode). 21 pm pattern mode. 0: bitmap mode, data from memory or host source. 1: pattern mode. 20 pl preserve lut data. 0: entire 2k buffer available for fetch data. 1: 1k reserved for lut. 19 pe prefetch enable. when this bit is set, data may be fetched while the blt is still pending. 18 hs host source. 0: data fetched from memory. 1: data written through host source writes. 17:16 rsvd reserved. 15:0 stride stride. increment between lines of bitmap in bytes. gp_ch3_mode_str bit de scriptions (continued) bit name description
amd geode? lx processors data book 275 graphics processor register definitions 33234h 6.4.2.23 width/heig ht (gp_ch3_widhi) this register is used to specify the wi dth and the height of the bi tmap to be fetched on channel 3 in pixels. this need not match the destination width and height, as in the case of a rotation blt where the width and height are swapped, but the total number of pixels should be equal to the number of pixels in the destination. 6.4.2.24 host source (gp_ch3_hsrc) this register is used by software to load channel 3 data when the channel 3 pattern mode bit is not set, the channel 3 enable bit is set, and the channel 3 host source bit is set.th is register is also aliased to the address range 400h-fffh allowing the processor to load large blocks of data to the gp using the repeat movs instruction. gp memory offset 68h ty p e r / w reset value 00000000h gp_ch3_widhi register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd wid rsvd hi gp_ch3_widhi bit descriptions bit name description 31:28 rsvd reserved. write as read. 27:16 wid width. width in pixels of the blt operation. 15:12 rsvd reserved. write as read. 11:0 hi height. height in pixels of the blt operation. gp memory offset 6ch ty p e w o reset value xxxxxxxxh gp_ch3_hsrc register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hst_src gp_ch3_hsrc bit descriptions bit name description 31:0 hst_src host source data. used during blt in host source mode
276 amd geode? lx processors data book graphics processor register definitions 33234h 6.4.2.25 lut inde x (gp_lut_index) this register is used to initialize the lut_index pointer t hat is used for subsequent lut operations. all lut accesses are dword accesses so only the 9 lsbs of the pointer are used to index into the 2 kb lut. addresses 000h-0ffh are used for 8-bit indexed lut data. addresses 000h-00fh are used fo r 4-bit indexed lut data. addresses 100h-13fh are used for storing color patterns. all addresses are used for storing incoming data (unless the pl bit is set in the gp_ch3_mode_str register, gp memory offset 64h[20]), but none of the remain ing addresses have any significance to software. 6.4.2.26 lut data (gp_lut_data) this register is used to store data into the lut for indexed color translations and color patterns. the 32 bits written to this register are stored in the lut at the location specified in the gp_lut_index register (gp memory offset 70h). a read of this register returns the cont ents of the lut at the location specified by th e gp_lut_index register. either a read or write of this register will cause the gp_lut_index register to incr ement, so the lut can be loaded through successive writes to the gp_lut_data register. gp memory offset 70h ty p e r / w reset value 00000000h gp_ch3_hsrc register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd lut_index gp_ch3_hsrc bit descriptions bit name description 31:9 rsvd reserved. 8:0 lut_index lut index. used to initialize the lut_index pointer that is used for subsequent lut operations. the lut_index automatically increments on a write to the gp_lut_data register (gp memory offset 74h). when performing a read, bit 31 must be set to cause the hardware to perform the read and update the gp_lut_data register. if this bit is not set, then a write is assumed and the read will not be performed. gp memory offset 74h ty p e r / w reset value xxxxxxxxh gp_ch3_hsrc register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lut_data gp_ch3_hsrc bit descriptions bit name description 31:0 lut_data lut_data. used to store data into the lut for indexed color translations and color pat- terns.
amd geode? lx processors data book 277 graphics processor register definitions 33234h 6.4.2.27 interrupt co ntrol (gp_int_cntrl) this register is used to control the inte rrupt signal from the gp. it contains a 16-b it mask and a 16-bit interrupt detect. the mask portion is read/write. a bit set in the mask register disabl es the corresponding interrupt bit. at reset, all interrupts a re disabled. the interrupt detect bits are automatically set by th e hardware to indicate that the corresponding condition has occurred and that the mask bit for that condition is not set. the interrupt detect bits remain set until they are cleared by a write to the gp_int_cntrl register. writin g a 1 to an interrupt detect bit clears the bit. writing a 0 to an interrupt detect b it has no effect. therefore, all of the interrupts in the gp ma y be cleared by reading the gp_int_cntrl register and writing back the value that was read. whenever any of the interrupt detect bits are set in this register, the in bit will be set in the gp_blt_status register (gp memory offset 44h[1]). gp memory offset 78h ty p e r / w reset value 0000ffffh gp_int_cntrl register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd i1 i0 rsvd m1 m0 gp_int_cntrl bit descriptions bit name description 31:18 rsvd reserved. read returns 0. 17 i1 gp idle detect interrupt. 16 i0 command buffer empty detect interrupt. 15:2 rsvd reserved. read returns 1. 1m1 gp idle mask bit. 0m0 command buffer empty mask bit.
278 amd geode? lx processors data book display controller 33234h 6.5 display controller the display controller (dc) module retrieves graphics, video, and overlay streams from the frame buffer, serial- izes the streams, performs any necessary color lookups and output formatting, and interfaces to the vp for driving the display device. features ? 512x64-bit display fifo ? 64x64x2-bit hardware cursor ? 64x vertical resolution x2-bit hardware icon overlay ? 3x261x8-bit palette/gamma ram (including five exten- sion colors) ? display refresh compression ? 64x64-bit compressed line buffer ? flexible timing generator ? support for video blanking interval (vbi) data ? support for interlaced modes up to 1920x1080 ? 3-tap flicker filter for support of interlaced ntsc and pal display modes ? flexible memory addressing ? video overlay support ? independent vga block for complete hardware vga implementation ? dirty/valid ram and controller to monitor memory traffic in support of displa y refresh compression ? six 512x64-bit line buffers to support downscaling and flicker filtering ? 3x5-tap graphics filter for scaling and filtering the dc module consists of a gui (graphical user inter- face) block, a vga block, and back-end scaling/filter. the gui is compatible with the display controller found in the gx processor. the vga block provides hardware compati- bility with the vga graphics standard. the gui and vga blocks share a single display fifo and display refresh memory interface to the memory controller. the vga block passes 8-bpp and syncs to the gui, which expands the pixels to 24-bpp via the clut (color lookup table). the vga block also passes the information to the graphics filter for scaling and interlaced display support. this stream is then passed to the video processor (vp), which is used for video overlay. the vp forwards this information to the dac (digital-to-analog converter), which generates the analog red, green, and blue signals and buffers the sync signals, that are then sent to the di splay. the vp output can also be rendered as yuv data that can be output on the video out- put port. the dc block diagram is shown in figure 6-12. figure 6-12. display controller high-level block diagram vga block graphical user interface block fifo host i/f fifo pixel, syncs, dispen display memory i/f display refresh memory control 8-bit pixel, syncs, display enable ctl dirty/valid flags video data output to vp dirty/valid ram and control gliu0 port gliu0 memory port geodelink? interface unit 0 (gliu0) clut graphics scaler/ filter
amd geode? lx processors data book 279 display controller 33234h the gui block, shown in figure 6-13, provides sophisti- cated graphics functionality suitable for a gui environment such as windows ? xp, windows ce, or linux ? operating systems. the gui is optimized for high resolution and high color depth display modes. figure 6-13. gui block diagram compressed graphics decompressor cursor & display fifo compressor video 32 32 64 64 64 display 24 display crt_hsync crt_vsync ena_disp dclk pclk vid_clk vid_data[32:0] pixel[31:0] 32 video vid_rdy vid_val vp_vsync timing generator control serializer address generator icon overlay (512x64-bit) serializer line buffer (64x64-bit) gliu 32 palette ram (3x261x8 bit) line buffer (3x1024 pixels) scaling filter line buffer (2x1024 pixels) flicker filter synchronizing line buffer (1x1024 pixels) 32 32 32 32 32
280 amd geode? lx processors data book display controller 33234h the vga block, shown in figure 6-14, provides hardware support for a compatible vga solution. it consists of an independent crt controller and pixel formatting units. it also provides the standard vga host memory data manip- ulation functions such as colo r compare, set, reset, etc. this block provides complete support for all vga text and graphics modes. figure 6-14. vga block diagram crtc pixel formatter shared fifo fifo control syncs dispen syncs dispen 8-bit pixel clock control display memory i/f control display memory i/f data fifo r/w data fifo control fifo read data vga dac i/o unit host memory i/f unit host cpu i/f gui clut i/o control host memory i/f
amd geode? lx processors data book 281 display controller 33234h 6.5.1 gui functional overview 6.5.1.1 display mode support the display modes listed in table 6-32 are supported by the gui block. 32- and 24-bpp display support is provided across all resolutions. the dot clock source (dotclk) is provided by a pll. available memory bandwidth deter- mines the resolutions and color depths that will function without display tearing. memory controller configuration, gliu frequency, and other demands on the memory con- troller set the available bandwidth. the gliu frequency determines the memory controller frequency. other demands on the memory controller such as the cpu and bus masters affect on available bandwidth are difficult to predict. use of the video overlay feature additionally decreases the bandwidth available for screen refresh. the minimum gliu frequency criteria listed in table 6-32 must be met for quality operation of the display. this fre- quency provides sufficient memory bandwidth for the mem- ory controller to maintain reliable display refresh under all operating conditions, including the video overlay. as a gen- eral rule, table 6-32 indicates what the minimum relation- ship of dotclk to gliu frequency should be at the various color depths. bandwidth requirements for the vga engine are not listed in this table. most graphics modes require the same band- width as comparable 8-bpp display modes listed in table 6- 32. text modes generally require higher bandwidth. sup- ported text modes require a gliu clock frequency of 100 mhz or more to obtain the necessary memory bandwidth. table 6-32. display modes resolution color depth (bpp) refresh rate (hz) dot clock (mhz) min. gliu frequency (mhz) 640 x 480 8, 16, or 24/32 60 25.175 75 8, 16, or 24/32 70 28.560 75 8, 16, or 24/32 72 31.500 75 8, 16, or 24/32 75 31.500 75 8, 16, or 24/32 85 36.000 75 8, 16, or 24/32 90 37.889 400 8, 16, or 24/32 100 43.163 400 800 x 600 8, 16, or 24/32 60 40.000 75 8, 16, or 24/32 70 45.720 75 8, 16, or 24/32 72 49.500 75 8, 16, or 24/32 75 49.500 75 8, 16, or 24/32 85 56.250 75 8, 16, or 24/32 90 60.065 400 8, 16, or 24/32 100 68.179 400 1024 x 768 8, 16 or 24/32 60 65.000 75 8, 16, or 24/32 70 75.000 100 8, 16, or 24/32 72 78.750 100 8, 16, or 24/32 75 78.750 100 8, 16, or 24/32 85 94.500 100 8, 16, or 24/32 90 100.187 400 8, 16, or 24/32 100 113.310 400 1152x864 8, 16, or 24/32 60 81.600 100 8, 16, or 24/32 70 97.520 100 8, 16, or 24/32 72 101.420 200 8, 16, or 24/32 75 108.000 200 8, 16, or 24/32 85 119.650 200 8, 16, or 24/32 90 129.600 400 8, 16, or 24/32 100 144.000 400
282 amd geode? lx processors data book display controller 33234h 1280 x 1024 8, 16, or 24/32 60 108.000 200 8, 16, or 24/32 70 129.600 200 8, 16, or 24/32 72 133.500 200 8, 16, or 24/32 75 135.000 200 8, 16, or 24/32 85 157.500 200 8, 16, or 24/32 90 172.800 400 8, 16, or 24/32 100 192.000 400 1600 x 1200 8, 16, or 24/32 60 162.000 200 8, 16, or 24/32 70 189.000 200 8, 16, or 24/32 72 198.000 233 8, 16, or 24/32 75 202.500 233 8, 16, or 24/32 85 229.500 266 8, 16, or 24/32 90 251.182 400 8, 16, or 24/32 100 280.640 400 1920x1440 8, 16, or 24/32 60 234.000 266 8, 16, or 24/32 70 278.400 400 8, 16, or 24/32 72 288.000 400 8, 16, or 24/32 75 297.000 400 8, 16, or 24/32 85 341.349 400 television modes 720x483 sd ntsc up to 32 59.94i 27.000 200 640x480 sd ntsc up to 32 up to 60.00i 27.000 200 768x576 sd pal up to 32 50.00i 27.000 200 720x576 sd pal up to 32 50.00i 27.000 200 1280x720 hd up to 32 up to 60.00i up to 74.750 200 1280x768 hd up to 32 50.00i 74.750 200 1440x720 hd up to 32 60.00i 74.750 400 1440x768 hd up to 32 50.00i 74.750 400 1920x1080 hd up to 32 up to 60.00i up to 148.500 400 table 6-32. display modes (continued) resolution color depth (bpp) refresh rate (hz) dot clock (mhz) min. gliu frequency (mhz)
amd geode? lx processors data book 283 display controller 33234h 6.5.1.2 display fifo the dc module incorporates a 512-entry x 64-bit display fifo that queues up all disp lay data, including graphics frame buffer data, compressed display buffer data, cursor and icon overlay data, and video overlay yuv data. when the video output port is enabled, 32 slots of the display fifo are allocated for the video transfer buffer. the dfhpsl and dfhpel (dc memory offset 004h[11:8] and [15:12]) bits are used to set the thresholds for high-pri- ority memory request assertion. these levels can be tuned for a particular display mode to optimize memory band- width utilization. 6.5.1.3 hardware cursor and icon overlays the gui supports a 64x64x2-bit hardware cursor overlay. the 2-bit codes are defined in table 6-33. a hardware icon overlay is also supported for applications that require a fixed sprite overla y. this is particularly useful in portable applications for disp lay status indica tors that are independent of the applicati on that is running. when enabled, the icon overlay is displayed on each active scan line. the icon is 64 pixels wide and supports three colors plus transparency as shown in table 6-34. the display of cursor and icon overlays is controlled by cure (bit 1) and clr_cur (bit 2) in dc_general_cfg (dc memory offset 004h), which take effect on the next vertical sync after the bits are programmed. the cursor is always displayed on top of the icon if both are enabled. the cursor and icon are inserted into the graphics stream prior to mixing the video overlay data. since the back- ground color-keyed value generally does not match the cursor or icon colors, the cursor and icon may be displayed on top of any active video. note that the cursor and icon features are not available in vga modes. table 6-33. cursor display encodings and mask xor mask color displayed 0 0 cursor color 0 - palette index 100h 0 1 cursor color 1 - palette index 101h 1 0 transparent - background pixel 1 1 inverted - bitwise inversion of background pixel table 6-34. icon display encodings and mask xor mask color displayed 0 0 icon color 0 - palette index 102h 0 1 icon color 1 - palette index 103h 1 0 transparent - background pixel 1 1 border color - palette index 104h
284 amd geode? lx processors data book display controller 33234h cursor/icon buffer formats in 2-bpp mode, the cursor buffer is stored as a linear dis- play buffer containing interlaced and and xor qwords (8-byte segments). each qword contains the appropriate mask for 64 pixels. even qwords contain the and masks and odd qwor ds contain the xor masks. the masks are stored ?in display orde r? with the le ftmost pixel being most significant and the rightmost pixel being least significant. for 32-bpp cursors, the cursor pixels include an alpha value, and are alpha blended with the underlying graphics pixels. for the purposes of cursor overlay, the cursor alpha value is used. if the graphics stream includes an alpha value, that value is not used for the purposes of cursor overlay. however, the graphics alpha value is retained in the resulting pixel stream. the cursor buffer stores 192 bytes of data per scan line (for 48 horizontal pixels) in 32-bpp mode. in this mode, the cur- sor size is 48 pixels wide and 64 pixels high, and so the buffer is 12 kb in size. in 2-bpp mode, cursor buffer includes 16 bytes of data per scan line (for 64 horizontal pixels). the cursor is 64x64, therefore the cursor buffer is 1 kb in size. the dc contains logic to address the overlay of the cursor on top of a color key region. table 6-35 indicates what pixel value is output from the dc?s rendering engine when the cursor is overlayed on the color key region. note that this behavior varies slightly when the graphics are represented in 32-bpp mode, which includes a per- pixel alpha value. table 6-35. cursor/color key/alpha interaction cursor per-pixel alpha color key match, per- pixel alpha no per-pixel alpha color key match, no per-pixel alpha no cursor color = graphics color alpha = graphics alpha color = graphics color alpha = 00 color = graphics color alpha = ff color = graphics color alpha = 00 2-bpp cursor (cursor color) color = cursor color alpha = graphics alpha or ff (config- urable) color = cursor color alpha = ff color = cursor color alpha = ff color = cursor color alpha = ff 2-bpp cursor (invert color) color = invert graph- ics color alpha = graphics alpha or ff (config- urable) color = invert graphics color alpha = ff color = invert graphics color alpha = ff color = invert graphics color alpha = ff 2-bpp cursor (transparent) color = graphics color alpha = graphics alpha color = graphics color alpha = 00 color = graphics color alpha = ff color = graphics color alpha = 00 color cursor (with alpha) color = blend cur- sor/graphics alpha = pp alpha or ff (configurable) color = cursor color alpha = cursor alpha color = blend cursor/graphics alpha = ff color = cursor color alpha = cursor alpha
amd geode? lx processors data book 285 display controller 33234h 6.5.1.4 display re fresh compression to reduce the system memory contention caused by the display refresh, the gui block contains compression and decompression logic for compressing the frame buffer image in real time as it is sent to the display. the dc does not modify the standard frame buff er, but rather, it utilizes a separate compressed display buffer for updating the dis- play under certain conditions. this compressed display buffer can be allocated within the extra off-screen memory within the graphics memory region. coherency of the compressed di splay buffer is maintained by use of dirty and valid bits for each line. whenever a line has been successfully compressed , it is retrieved from the compressed display buffer for all future accesses until the line becomes dirty again. dirty lines are retrieved from the normal uncompressed frame buffer. the compression logic has the ability to insert a ?static? frame every other display frame, during which time dirty bits are ignored and the valid bits are read to determine whether a line should be retrieved from the frame buffer or compressed display buffer. this allows a latency of one frame between pixels actually being rendered and showing up on the display. this effect typically goes unnoticed for traditional 2d applications but may result in increased tear- ing in single-buffered animation sequences. this feature may be used to tune for maximum performance or optimal display quality. the compression algorithm used commonly achieves com- pression ratios between 10:1 and 50:1, depending on the nature of the display data. the compression algorithm employed is lossless and therefore results in no loss of visual quality. this high level of compression provides higher system performance by reducing typical latency for normal system memory access, higher graphics perfor- mance by increasing available drawing bandwidth to the memory subsystem, and lower power consumption by sig- nificantly reducing the number of off-chip memory accesses required for refreshing the display. these advan- tages become more pronounced as display resolution, color depth, and refresh rate ar e increased, and as the size of the installed dram increases. as uncompressed lines are fed to the display, they are compressed and stored in an on-chip compressed line buffer (64x64 bits). lines will not be written back to the compressed display buffer in the dram unless a success- ful compression has resulted, so there is no penalty for pathological frame buffer images where the compression algorithm is sub-optimal. 6.5.1.5 dirty/valid ram the dc module incorporates the dirty/valid ram (dvram) in the display controller module. the dirty/valid ram controller directly snoops gliu0 request packets on the memory data port. the dirty/valid ram may be used to monitor locations in memory other than the frame buffer. (compression and decompression must be disabled in order for the display controller to continue to function properly.) this may be used for scenarios where software (or the graphics pro- cessor) must modify or re-render a frame whenever corre- sponding modifications occur in an offscreen graphics buffer. the ?palletized? bit is set upon writes to the corre- sponding region of memory. however, it is up to software to clear the dirty bit by writing to the dirty/valid ram access register (dc memory offset 08ch). 6.5.1.6 palette/gamma ram the gui block contains a 261x24 color lookup table ram used for palletized display modes (indexes 0-255), cursor colors (indexes 256-257), and the gui mode border color (index 260). this color lookup table is also used by the vga block to map the 8-bit vga pixels to a 24-bit rgb color value. in true color display modes (16, 24, or 32-bpp), the color lookup table can be used as a gamma correction ram. 6.5.1.7 display address generator the gui block supports flexible address generation for the frame buffer, compressed display buffer, cursor and icon buffers, and video buffers (yuv 4:2:2 or 4:2:0 format). a separate start offset register is provided for each display buffer. the start offset may be programmed to be relative to frame buffer space (up to 256 mb). 6.5.1.8 display timing generator the gui block includes a flexible timing generator capable of handling up to a 1920x1440 resolution display. horizon- tal timings are programmable with 1-pixel granularity. verti- cal timings are programmable with scan line granularity. the timing registers are master -slaved such that a new tim- ing set may be programmed while the working set is still active. the trup configuration bit (dc_display_cfg, dc memory offset 008h[6]) is used to allow the new set of timings to take effect at the st art of vertical sync. as long as the horizontal and vertical total counts do not change when a new timing set is loaded, the sync pulses should remain stable and the display should not glitch.
286 amd geode? lx processors data book display controller 33234h 6.5.1.9 video o verlay support the gui block also supports a video overlay function. the dc has flexible addressing capability for yuv 4:2:2 and yuv 4:2:0 display surfaces. video data is stored in a sepa- rate buffer within the off-screen frame buffer. independent surface pitch control is provided for y and u/v. the dc fetches the contents of the video and transmits it to the video processor once per frame. the video processor provides enhanced overlay scaling and filtering options. the width of the video output port is 32 bits. this allows the display of high-resolution video source material (up to 1920 horizontal pixels) mixed with high-resolution graphics data. table 6-36 illustrates the minimum video port bandwidth required for a number of different graphics display resolu- tions. table 6-36. video bandwidth resolution refresh rate (hz) line rate (khz) video source size (b) video port bandwidth required (mb/s) 640x480 60 31.5 1440 45.4 2160 68.0 85 43.3 1440 62.4 2160 93.5 800x600 60 37.9 1440 54.5 2160 81.9 85 53.7 1440 77.3 2160 116.0 1024x768 60 48.4 1440 69.7 2160 105 85 68.7 1440 98.9 2160 148.4 1280x1024 60 64.0 1440 92.2 2160 138 85 91.1 1440 131 2160 197 1600x1200 60 75.0 1440 108 2160 162 70 87.5 1440 126 2160 189
amd geode? lx processors data book 287 display controller 33234h 6.5.1.10 output formats video output data sequencing the order that video data is transmitted from the dc to the vp depends on the format of the video data. for yuv 4:2:0 mode, the entire stream of y data is transmitted for a source line, followed by the entire stream of u data for the line, and finally, the entire stream of v data for the line. the size of the u and v streams are always one-half the size of the y stream. the data is not in terlaced as in the yuv 4:2:2 mode. the data ordering is shown in table 6-37. for yuv 4:2:2 mode, yuv data is interlaced in a single stream, with a maximum size of 1440 bytes. in yuv 4:2:2 mode, four orde rs of yuv data are supported. the data format is selectable via the video configuration register (vp memory offset 000h) in the video processor module. the data ordering is shown in table 6-38. 6.5.2 vbi data vbi (video blanking interval) data is fetched by the dc at the start of each frame. the data is fetched from a buffer in memory, separately from video or graphics data. it is pre- sented to the vp on the graphics port. vbi data is provided via a path that circumvents the gamma correction palette and the graphics filter. the data presented to the vp/vop is only the data in memory. there are no additional head- ers attached by the dc. configuration registers in the dc determine how many lines of vbi data are sent during each field; the lines can be enabled/disabled independently of one another. if a line is disabled, no data is fetched (from memory) for that line, and the memory line pointer is not incremented. thus, non-contiguous lines of screen vbi must be stored contiguously in memory if there are no active vbi lines between them. the dc can be pro- grammed to fetch multiple fields worth of vbi data from lin- ear frame buffer space without resetting to the start of the buffer on each field. this minimizes the interrupt overhead required to manage vbi data. vbi data streams of up to 4 kb per scan line are supported. the vbi horizontal timings are controlled in a manner simi- lar to the horizontal active timings. the reference point for the horizontal (pixel) counter is the start of active video. this means that if the vbi data is to be active before this point on the line (i.e., to the left of, and above active video), it may be necessary to set th e vbi horizontal start point to a large number (less than the horizontal total, but larger than the vbi horizontal end point). the line counter used to calculate vbi offsets is incr emented at the start of each hsync, and not at the start of active video. this means that even if the vbi horizontal timings are such that it starts during the horizontal ?back porch? region, the line counts and enables are the same as if the vbi horizontal timing was the same as the graphics timing. 6.5.3 genlock the dc has the ability to use an external source to deter- mine the timing and frequency of vsync. this is primarily used in systems in which the vip is providing video data to be displayed in a native screen resolution and frame rate. the dc can also be configured to detect the loss of vsync in this case, and temporarily generate its own vsync pulse until the external source resumes generation of video data and synchronization. this is accomplished through the use of a vsync timeout counter. the dc can also generate an interrupt when a loss of synchronization is detected. table 6-37. yuv 4:2:0 video data ordering sequence data type max size (bytes) 1 y stream 1920 2 u stream 960 3 v stream 960 table 6-38. yuv 4:2:2 video data ordering mode yuv ordering (note 1) note 1. u = cb, v = cr. 0 u y0 v y1 1 y1 v y0 u 2y0 u y1 v 3 y0 v y1 u
288 amd geode? lx processors data book display controller 33234h 6.5.4 vga block functional overview the vga block provides full hardware support for a vga graphics subsystem. it is comp atible with the ibm vga as defined in the ibm video sub system technical reference manual. this section provides an overview of vga features and functions. 6.5.4.1 vga modes a vga ?mode? is a programm ed vga configuration defined by the vga bios that produces a graphics frame buffer format and a screen image wit h specific characteristics. the base vga function provides coded text modes for text- based applications, and graphics modes for graphics- based applications. many of these modes are compatible with older graphics adapter standards, such as mono- chrome display adapter, color graphics adapter, and enhanced graphics adapter. text modes there are five text modes defined by vga bios as shown table 6-39. each of the text modes provid es a coded frame buffer con- sisting of a 16-bit value for each character. the low byte is the ascii character code for the character to display, and the high byte is an attribute byte that determines how the character is displayed (foreground, background colors, blink, underline, etc.). there are two formats defined by bios for the attribute byte: color and monochrome as shown in table 6-40. graphics modes the graphics modes defined by vga bios are shown in table 6-41. figure 6-15. vga frame buffer organization table 6-39. vga text modes bios mode # screen size in characters attribute type buffer address compatibility 0, 1 40 x 25 color b8000h- bffffh cga 2, 3 80 x 25 color b8000h- bffffh ega, vga 7 80 x 25 mono- chrome b0000h- b7fffh mda table 6-40. text mode attribute byte format bit color definition monochrome definition 7 blink blink 6 background color (r) background 5 background color (g) background 4 background color (b) background 3 foreground intensity/font select foreground intensity/font select 2 foreground color (r) foreground 1 foreground color (g) foreground table 6-41. vga graphics modes bios mode # screen size in pixels # of colors frame buffer format buffer address 4, 5 320 x 200 4 packed pixel b8000h-bffffh 6 640 x 200 2 packed pixel b8000h-bffffh 0xd 320 x 200 16 planar a0000h-affffh 0xe 640 x 200 16 planar a0000h-affffh 0xf 640 x 400 4 planar a0000h-affffh 0x10 640 x 350 16 planar a0000h-affffh 0x11 640 x 480 2 planar a0000h-affffh 0x12 640 x 480 16 planar a0000h-affffh 0x13 320 x 200 256 packed pixel a0000h-affffh 3210 byte byte byte byte 64 kb dwords
amd geode? lx processors data book 289 display controller 33234h 6.5.5.2 graphi cs controller the graphics controller mana ges the cpu interaction with video memory, and contains the video serializers that feed the front end of the attribute controller. several memory read and write modes are supported that provide various forms of acceleration for vga graphics operations. a high- level diagram of the graphics controller is shown in figure 6-16. figure 6-16. graphics controller high-level diagram memory map 3 data memory map 2 data memory map 1 data memory map 0 data write read m serializers cpu data pix out character gen data attribute byte each bus is 8 bits except for pix out, video mode mode latch u x which is 4 bits. note:
290 amd geode? lx processors data book display controller 33234h 6.5.5.3 write modes there are four write modes supported by the graphics con- troller (mode 0, 1, 2, and 3). these write modes provide assistance to the cpu when the frame buffer is in a planar graphics format. figure 6-17 shows the data flow logic that supports these modes. figure 6-17. write mode data flow cpu data [7:0] rotator data rotate [2:0] set/reset [3:0] 3210 3210 b writemode2 b b b b enable set/reset [3:0] 3210 bit mask [7:0] -a/+a*b write mode 3 a read data latch [31:0] alu function [1:0] 31:24 23:16 15:8 7:0 map 3 write data map 2 write data map 1 write data map 0 write data f abababab ab ab ab ab ab dmsdmsdmsdms n d memory maps 8 8 8 8 8 8 8 8 8 8 8 8 8 8
amd geode? lx processors data book 291 display controller 33234h 6.5.5.4 read modes there are two read modes provided to assist the cpu with graphics operations in planar modes. read mode 0 simply returns the frame buffer data. read mode 1 allows the cpu to do a single color compare across eight pixels. figure 6- 18 shows the data flow for read modes. figure 6-19 on page 292 shows how the color compare logic in figure 6- 18 works. figure 6-18. read mode data flow memory read data [31:0] read map select [1:0] chain2 chain4 cpu a[1:0] select read map logic readmode1 b cpu read data [7:0] in [31:0] out [7:0] color compare in [31:0] out [7:0] color compare [3:0] color don?t care [3:0] ab logic
292 amd geode? lx processors data book display controller 33234h figure 6-19. color compare operation 8x4 input and compare result [7:0] cc3 cc2 cc1 cc0 memory data [31:0] 31:24 23:16 15:8 7:0 color compare [3:0] 3210 color don?t care [3:0] 3210 d[7:0] c xor or ccx[7:0] e color compare block detail ecd ecd ec d ecd
amd geode? lx processors data book 293 display controller 33234h 6.5.6 graphics scaler/filter the dc incorporates a 3x5 tap filter to be used for up/ downscaling of the graphics image. in order to support the filter, three lines of buffering are also included. these three line buffers support a frame buffer resolution of up to 1024 pixels wide. for wider images , the buffers are automatically reconfigured into one line, and scaling is not supported. for frame buffer images up to and including 1024 pixels in width, vertical downscaling of up to (but not including) 2:1 is supported and horizontal downscaling of up to (but not including) 2:1 is supported. the filter is organized as five 3-tap vertical filters that feed the five taps of a horizontal f ilter. the filter supports 1/256 inter-pixel quantization (i.e., 256-phase) in both the hori- zontal and vertical directions. the filter coefficients are 10 bits wide. scaling is controlled by adjusting the horizontal and vertical filter scale factors (through configuration register 90). these numbers represent binary rational numbers in a 2.14 format. at the start of each frame, the h phase adder and v phase adder are reset to 0. at the start of each scan line, the v phase adder is added to v phase and the result is stored in v phase adder. th e integer portion of the value in v phase adder indicates on which line the filter kernel is centered. the most significant eight bits of the fractional portion of this value determine the vertical phase for the purpose of determining the filter coefficients. the h phase adder mechanism is similar but operates on pixels instead of lines. a block diagram of the filter is shown in figure 6-20. figure 6-20. graphics filter block diagram v phase adder h phase adder v. coefficient ram x x x + address h phase v phase line buffer selection and routing address address for h. coefficient ram line buffer line buffer line buffer to horizontal latches
294 amd geode? lx processors data book display controller 33234h figure 6-20. graphics filter block diagram (continued) 2 pixel latch x x x + x x x + 2 pixel latch h. coefficient ram x x x x x + addresses for h. coefficient ram from h phase adder the entire structure is r eplicated for each pixel component (red, green, blue, and alpha).
amd geode? lx processors data book 295 display controller 33234h to support the flicker filter, the scaling filter then feeds two additional line buffers. these buffers are 1024 pixels wide. the scaling filter directly feeds a tap of the 3x1-tap flicker filter. (the other two taps are fed by the two line buffers.) all filtering is performed in the geodelink i/f clock domain. the result from the flicker filter feeds a final line buffer, which is used to synchronize the data stream to the dot clock domain. when the flicker filter is enabled, the final image width is dictated by this final line buffer, which is 1024 pixels wide. when the flicker filter is disabled, the two line buffers normally used to feed the flicker filter are used as one line buffer, that feeds the final synchronizing line buffer. this enables scaling to image sizes up to 2048 pix- els wide, provided that interlacing is not required. figure 6- 21 illustrates the flicker filter and line buffer path. figure 6-21. flicker filter and line buffer path 1024-pixel line buffers graphics scaler filter delay 1024-pixel line buffers 3-tap ver tical flicker filter 1024-pixel line buffers
296 amd geode? lx processors data book display controller 33234h 6.5.7 color key elimination additional logic, not shown in the diagrams, is used to pre- serve the color key color. this logic, when enabled, adjusts the alpha value for each filter input pixel in which a color key match is detected. the filt er then uses the alpha value to determine if a pixel matches the color key. for informa- tion on the interaction of cursor and color key, table 6-35 on page 284. the filter contains specialized logic to remove color key pix- els from the blended output and replace them with nearby pixels. this prevents halo effects if the color key contrasts sharply with the surrounding graphics image. for each of the 3-tap vertical filters, except the center one, the replacement algorithm is as follows: ? if the top pixel is the only color key pixel, the center pixel is used in its place. ? if the bottom pixel is the only color key pixel, the center pixel is used in its place. ? if the center pixel is the only color key pixel, the top pixel is used in its place. ? if any two pixels are color key pixels, the remaining pixel is output to the ho rizontal filter. ? if all pixels are color key pixe ls, the bottom pixel is output to the horizontal filter. (the vertical output is a color key pixel and the alpha value is set accordingly.) for the center 3-tap vertical filter, the algorithm is as fol- lows: ? if the top pixel is a color key pixel, the center pixel is used in its place. ? if the bottom pixel is a color key pixel, the center pixel is used in its place. ? if the center pixel is a color key pixel, the center pixel is output to the horizontal filter regardless of the values of the other two pixels. (the vertical output is a color key pixel, and the alpha value is set accordingly.) the horizontal filter algorithm follows. assume that the pixel inputs are numbered 1-5, left to right. ? if pixel 1 is a color key pixel and pixel 2 is not, pixel 2 is used in place of pixel 1. ? if pixel 1 and pixel 2 are both color key pixels, pixel 3 is used in place of pixel 1. ? if pixel 2 is a color key pixel, pixel 3 is used in place of pixel 2. ? if pixel 5 is a color key pixel and pixel 4 is not, pixel 4 is used in place of pixel 5. ? if pixel 4 and pixel 5 are both color key pixels, pixel 3 is used in place of pixel 5. ? if pixel 4 is a color key pixel, pixel 3 is used in place of pixel 4. ? if pixel 3 is a color key pixel, pixel 3 is output from the filter regardless of the values of pixels 1, 2, 4, and 5. (the result is a color key pixel; the alpha value is set accordingly.) if the center pixel matches the color key, it is passed through directly. if the center pixel does not match the color key, then any other filter inpu t pixel that matches the color key is discarded and replaced by a nearby non-color-key- matching neighbor. 6.5.8 using the graphics filter from a software perspective, the amd geode lx proces- sor dc appears much like its predecessor in the amd geode gx processor design. the graphics filter is disabled by default, and the timing and addressing regis- ters operate as before. one significant change is the addi- tion of color key detection logic to the dc block. this logic was previously only in the vp. when enabling the vp for the purpose of scaling the output image, some additional parameters must be programmed (these parameters need not be programmed if the graph- ics filter/scaler is to remain disabled.): ? the horizontal and vertical size of the source image ? the horizontal and vertical scaling factors to be used to scale the source image ? the filter coefficients the timing registers (dc memory offsets 040h-058h) should be programmed based on the parameters for the resulting output image. note that this image may differ in size from the frame buffer image. the frame buffer image size is used to determine the value to be written to the frame buffer active region register (dc memory offset 05ch). the scaling factors are programmed into the graphics fil- ter scale register (dc memory offset 090h). these fields are 16 bits each (horizontal and vertical). the 16 bits repre- sent the ratio of the destination image size to the source image size. they are right-shift ed 14 bits to represent frac- tional values between 0 and 3.99993896484375. however, due to hardware limitations, the downscale factors cannot exceed 2.0. thus the image can be downscaled by nearly 2x in the horizontal and vertical directions. the image can be upscaled by up to 16384x, although the crtc does not support images beyond 1920x1440 pixels, so it is unlikely that scale factors beyond about 4x would ever be used. vbi data is not filtered. the scaling factors in the graphics filter scale register have no effect on vbi data. the filter supports 256 sub-pixel phases in both the hori- zontal and vertical directions. each coefficient is 10 bits, and is represented as a 2?s compliment number, right- shifted 9 bits to represent values between -1 and 0.998046875. the coefficients must be loaded into the rams by software, using the ir q/filter control register, fil- ter coefficient data register 1, and filter coefficient data register 2 (dc memory offsets 094h-09ch).
amd geode? lx processors data book 297 display controller 33234h 6.5.9 interlaced modes for interlaced modes, the v_active and v_total fields are configured for the odd field. the even field vertical timing registers (dc memory offsets 0e4h-0ech) are configured for the corresponding even field. figure 6-22 on page 298 shows a representative timing diagram for the odd and even timing register settings in interlaced modes, and table 6-43 on page 298 presents the (decimal) timing values for some common interlaced modes. the dc is capable of producing an interlaced output using any of three separate mechanisms. it can fetch the graph- ics data in an interlaced manner, flicker filter the graphics data, or use the same graphics data for both odd and even fields, (which would effectively line-double the resulting image). when the vga is being used, interlaced address- ing is not supported, and scaling must be used. when the frame buffer source image or the output image is wider than 1024 active pixels, the flicker filter is not supported. when scaling and/or interleaving is enabled, the size of the frame buffer image (in pixels) will vary from the size of the output image. table 6-42 and table 6-44 on page 299 indi- cates how the dc?s timing register fields should be pro- grammed for supported scaling and interlacing modes. (note that for vga modes, t here are several vga registers that can affect the size of the frame buffer image. these registers are not enumerated in the table.) table 6-42. programming image sizes mode pre-scale horizontal width pre-scale height post-scaler width post-scaler height final (output) width final (output) height default (no vga, scal- ing, interlacing, or flicker filter) h_active v_active h_active v_active h_active v_active scaling only fb_h_active fb_v_active h_active v_active h_active v_active interlacing only (no flicker filter) h_active v_active or v_active_eve n (alternating) h_active v_active or v_active_eve n (alternating) h_active v_active or v_active_eve n (alternating) interlacing with flicker fil- ter h_active v_active + v_active_eve n + 1 (note 1) h_active v_active + v_active_eve n + 11 h_active v_active or v_active_eve n (alternating) interlacing with inter- laced addressing (no flicker filter) h_active v_active or v_active_eve n (alternating) h_active v_active or v_active_eve n (alternating) h_active v_active or v_active_eve n (alternating) interlacing with scaler (no flicker filter, no interlaced addressing) fb_h_active fb_v_active h_active v_active or v_active_eve n (alternating) h_active v_active or v_active_eve n (alternating) interlacing with scaler and flicker filter fb_h_active fb_v_active h_active v_active + v_active_eve n + 11 h_active v_active or v_active_eve n (alternating) vga (no scaling, interlac- ing, or flicker filter) vga crtc vga crtc vga crtc vga crtc vga crtc vga crtc vga with scaling (no interlacing or flicker filter vga crtc vga crtc h_active v_active h_active v_active vga with scaling and interlacing (no flicker fil- ter) vga crtc vga crtc h_active v_active or v_active_eve n (alternating) h_active v_active or v_active_eve n (alternating) vga with scaling, inter- lacing, and flicker filter vga crtc vga crtc h_active v_active + v_active_eve n + 11 h_active v_active or v_active_eve n (alternating) note 1. because the register value represents the image size minus 1, an additional 1 is added when these two register values ar e added together to retain the convention.
298 amd geode? lx processors data book display controller 33234h 6.5.10 interlaced timing examples figure 6-22 shows how the dc's timing registers are used to control timings for interlaced display modes. the smtpe standards define the even and odd fields as starting at vsync, while the register se ttings define the timings based on the start of the active display region, as is com- mon in (non-interlaced) vesa timing standards. as a result, the v_sync_end and v_total register settings each define a region that begins in the odd field and ends in the next even field. similarly, the v_sync_even_end and v_total_even register settings each define a region that begins in the even field and ends in the next odd field. all register values are in hex; assuming vsync pulse width of one line. table 6-43 lists timings for various interlaced modes for ref- erence. the user should verify these timings against cur- rent specifications for their application.) table 6-44 on page 299 provides the corresponding register settings (hexadec- imal values) for these modes. the vsync pulse is assumed to be one line wide. further information on these registers can be found in section 6.6.5 on page 327. figure 6-22. interlaced timing settings . vsync vertical display active odd field even field back porch front porch back porch front porch active region active region v_active_end v_total v_sync_start v_sync_end v_active_even_end v_total_even v_sync_even_start v_sync_even_end back porch table 6-43. vertical timing in number of lines timing set odd field even field back porch active front porch back porch active front porch 525 16 242 2 17 241 3 625 22 288 2 23 288 2 720i 12 360 3 13 360 2 1080i 20 540 3 20 540 2 1080i 50 hz 80 540 5 80 540 5
amd geode? lx processors data book 299 display controller 33234h table 6-44. timing register settings for interlaced modes timing set parameter odd register even register formula v_active_end (odd_active-1) (even_active-1) v_total (odd_active + odd_fp + even_bp - 1) (even_active + even_fp + odd_bp - 1) v_sync_start (odd_active + odd_fp - 1) (even_active + even_fp - 1) v_sync_end (odd_active + odd_f p + odd_vsync - 1) (even_acti ve +even_fp + even_vsync - 1) 525 v_active_end f1 f0 v_total 106 105 v_sync_start f5 f5 v_sync_end f6 f6 625 v_active_end 11f 11f v_total 138 137 v_sync_start 121 121 v_sync_end 122 122 720i v_active_end 167 167 v_total 177 177 v_sync_start 16a 169 v_sync_end 16b 16a 1080i v_active_end 21b 21b v_total 232 231 v_sync_start 21e 21d v_sync_end 21f 21e 1080i 50 hz v_active_end 21b 21b v_total 270 270 v_sync_start 220 220 v_sync_end 221 221
300 amd geode? lx processors data book display controller register descriptions 33234h 6.6 display controller register descriptions this section provides information on the registers associ- ated with the display controller (dc) (i.e., gui and vga blocks), including the standard geodelink? device (gld) msrs and the display controller specific msrs (accessed via the rdmsr and wrmsr instructions). table 6-45 through table 6-50 are register summary tables that include reset values and page references where the bit descriptions are provided. note: the msr address is derived from the perspective of the cpu core. see section 4.1 "msr set" on page 45 for more details on msr addressing. table 6-45. standard geodelink? device msrs summary msr address type register name reset value reference 80002000h ro gld capabilities msr (gld_msr_cap) 00000000_0003e4xxh page 305 80002001h r/w gld master configuration msr (gld_msr_config) 00000000_00000000h page 305 80002002h r/w gliu0 device smi msr (gld_msr_smi) 00000000_00000000h page 306 80002003h r/w gld error msr (gld_msr_error) 00000000_00000000h page 308 80002004h r/w gld power management msr (gld_msr_pm) 00000000_00000015h page 310 80002005h r/w gliu0 device diagnostic msr (gld_msr_diag) 00000000_00000000h page 310 table 6-46. dc specific msrs summary msr address type register name reset value reference 80000012h r/w dc ram control msr (dc_ram_ctl_msr) 00000000_02020202h page 311 table 6-47. dc configuration control register summary dc memory offset type register name reset value reference configuration and status registers 000h r/w dc unlock (dc_unlock) 00000000h page 312 004h r/w dc general configuration (dc_general_cfg) 00000000h page 314 008h r/w dc display configuration (dc_display_cfg) 00000000h page 317 00ch r/w dc arbitration configuration (dc_arb_cfg) 00000000h page 319 memory organization registers 010h r/w dc frame buffer start address (dc_fb_st_offset) xxxxxxxxh page 321 014h r/w dc compression buffer start address (dc_cb_st_offset) xxxxxxxxh page 322 018h r/w dc cursor buffer start address (dc_curs_st_offset) xxxxxxxxh page 322
amd geode? lx processors data book 301 display controller register descriptions 33234h 020h r/w dc video y buffer start address offset (dc_vid_y_st_offset) xxxxxxxxh page 323 024h r/w dc video u buffer start address offset (dc_vid_u_st_offset) xxxxxxxxh page 323 028h r/w dc video v buffer start address offset (dc_vid_v_st_offset) xxxxxxxxh page 324 02ch r/w dc dirty/valid region top (dc_dv_top) 00000000h page 324 030h r/w dc line size (dc_line_size) xxxxxxxxh page 325 034h r/w dc graphics pitch (dc_gfx_pitch) xxxxxxxxh page 326 038h r/w dc video yuv pitch ( dc_vid_yuv_pitch) xxxxxxxxh page 326 timing registers 040h r/w dc horizontal and total timing (dc_h_active_timing) xxxxxxxxh page 328 044h r/w dc crt horizontal blanking timing (dc_h_blank_timing) xxxxxxxxh page 329 048h r/w dc crt horizontal sync timing (dc_h_sync_timing) xxxxxxxxh page 329 050h r/w dc vertical and total timing (dc_v_active_timing) xxxxxxxxh page 330 054h r/w dc crt vertical blank timing (dc_v_blank_timing) xxxxxxxxh page 331 058h r/w dc crt vertical sync timing (dc_v_sync_timing) xxxxxxxxh page 331 05ch r/w dc frame buffer active region register (dc_fb_active) xxxxxxxxh page 332 cursor position and co unt status registers 060h r/w dc cursor x position (dc_cursor_x) xxxxxxxxh page 332 064h r/w dc cursor y position (dc_cursor_y) xxxxxxxxh page 333 06ch ro dc line count/status ( dc_line_cnt/status) xxxxxxxxh page 333 palette access and fifo diagnostic registers 070h r/w dc palette address (dc_pal_address) xxxxxxxxh page 335 074h r/w dc palette data (dc_pal_data) xxxxxxxxh page 336 078h r/w dc display fifo diagnostic (dc_dfifo_diag) xxxxxxxxh page 336 07ch r/w dc compression fifo diagnostic (dc_cfifo_diag) xxxxxxxxh page 337 video downscaling registers 080h r/w dc video downscaling delta (dc_vid_ds_delta) 00000000h page 338 gliu0 control registers 084h r/w dc gliu0 memory offset (dc_gliu0_mem_offset) 00000000h page 339 088h r/w dc dirty/valid ram control (dc_dv_ctl) 00000000h page 339 table 6-47. dc configuration control register summary (continued) dc memory offset type register name reset value reference
302 amd geode? lx processors data book display controller register descriptions 33234h 08ch r/w dc dirty/valid ram access (dc_dv_access) 0000000xh page 340 graphics scaling control registers 090h r/w dc graphics filter scal e (dc_gfx_scale) 40004000h page 341 094h r/w dc irq/filter control (dc_irq_filt_ctl) 00000000h page 342 098h r/w dc filter coeffi cient data register 1 (dc_filt_coeff1) xxxxxxxxh page 343 09ch r/w dc filter coefficient data register 2 (dc_filt_coeff2) xxxxxxxxh page 344 vbi control registers 0a0h r/w dc vbi even control (dc_vbi_even_ctl) xxxxxxxxh page 344 0a4h r/w dc vbi odd control (dc_vbi_odd_ctl) xxxxxxxxh page 345 0a8h r/w dc vbi horizontal control (dc_vbi_hor) xxxxxxxxh page 345 0ach r/w dc vbi odd line enab le (dc_vbi_ln_odd) xxxxxxxxh page 346 0b0h r/w dc vbi even line enab le (dc_vbi_ln_even) xxxxxxxxh page 346 0b4h r/w dc vbi pitch and size (dc_vbi_pitch) xxxxxxxxh page 347 color key control registers 0b8h r/w dc color key (dc_clr_key) 00000000h page 347 0bch r/w dc color key mask (dc_clr_key_mask) 00xxxxxxh page 348 0c0h r/w dc color key horizontal position (dc_clr_key_x) 00000000h page 348 0c4h r/w dc color key vertical position (dc_clr_key_y) 00000000h page 348 interrupt and genlock registers 0c8h r/w dc interrupt (dc_irq) 00000003h page 349 0d4h r/w dc genlock control (dc_genlk_ctl) xxxxxxxxh page 350 even field video address registers 0d8h r/w dc even field video y start address offset (dc_vid_even_y_st_offset) xxxxxxxxh page 351 0dch r/w dc even field video u start address offset (dc_vid_even_u_st_offset) xxxxxxxxh page 352 0e0h r/w dc even field video v start address offset (dc_vid_even_v_st_offset) xxxxxxxxh page 352 even field vertical timing registers 0e4h r/w dc vertical and total timing for even fields (dc_v_active_even_timing) xxxxxxxxh page 353 0e8h r/w dc crt vertical blank timing for even fields (dc_v_blank_even_timing) xxxxxxxxh page 354 0ech r/w dc crt vertical sync timing for even fields (dc_v_sync_even_timing) xxxxxxxxh page 354 table 6-47. dc configuration control register summary (continued) dc memory offset type register name reset value reference
amd geode? lx processors data book 303 display controller register descriptions 33234h table 6-48. vga block configuration register summary dc memory offset type register name reset value reference 100h r/w vga configuration (vga_config) 00000000h page 355 104h ro vga status (vga_status) 00000000h page 355 table 6-49. vga block standard register summary i/o read address i/o write address register name/group reset value reference 3cch 3c2h (w) vga miscellaneous output 02h page 356 3c2h -- vga input status register 0 00h page 357 3bah or 3dah (note 1 ) -- vga input status register 1 01h page 357 3cah 3bah or 3dah (note 1) vga feature control xxh page 357 3c4h vga sequencer index 0xh page 358 3c5h vga sequencer data xxh page 358 3b4h or 3d4h (note 1) crtc index 00h page 362 3b5h or 3d5h (note 1) crtc data 00h page 363 3ceh vga graphics controller index xxh page 373 3cfh vga graphics controller data xxh page 374 3c0h attribute controller index/data xxh page 379 3c1h (r) 3c0h (w) 3c8h 3c7h (palette read mode) video dac palette address 00h page 382 3c8h (palette write mode) 3c7h-- video dac state 00h page 383 3c9h video dac palette data 00h page 383 3c6h video dac palette mask 00h page 384 note 1. the i/o addresses are determined by bit 0 of the miscell aneous output register. see the description of this register in section 6.6.17.1 on page 356 for more information.
304 amd geode? lx processors data book display controller register descriptions 33234h table 6-50. vga block extended register summary vga crtc index type register name reset value reference 0030h r/w extendedregisterlock ffh page 385 043h r/w extendedmodecontrol 00h page 385 044h r/w extendedstartaddress 00h page 385 047h r/w writememoryaperture 00h page 386 048h r/w readmemoryaperture 00h page 386 060h r/w blinkcounterctl 00h page 386 061h ro blinkcounter 00h page 387 070h r/w vgalatchsavres 00h page 387 071h r/w dacifsavres 00h page 387
amd geode? lx processors data book 305 display controller register descriptions 33234h 6.6.1 standard geodelink? device (gld) registers (msrs) 6.6.1.1 gld capabilities msr (gld_msr_cap) 6.6.1.2 gld master configur ation msr (gld_msr_config) msr address 80002000h ty p e r o reset value 00000000_0003e4xxh gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. set to 0. 23:8 dev_id device id. identifies device (03e4h). 7:0 rev_id revision id. identifies device revision. see amd geode? lx processors specification update document for value. msr address 80002001h ty p e r / w reset value 00000000_00000000h gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pri1 rsvd pri0 rsvd pid gld_msr_config bit descriptions bit name description 63:11 rsvd reserved. set to 0. 10:8 pri1 secondary priority level. this value is the priority level the dc uses when performing high priority gliu0 accesses. this is the case when the fifos are nearly empty. 7 rsvd reserved. set to 0. 6:4 pri0 primary priority level. this value is the priority level the dc uses for most accesses (i.e., when the display fifo is not in danger of being emptied). 3 rsvd reserved. set to 0. 2:0 pid priority id. this value is the priority id (pid) value used when the dc initiates gliu0 transactions.
306 amd geode? lx processors data book display controller register descriptions 33234h 6.6.1.3 gliu0 device smi msr (gld_msr_smi) msr address 80002002h ty p e r / w reset value 00000000_00000000h gld_msr_smi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd vga_res_change_smi rsvd isr1r_smi miscior_smi dacior_smi daciow_smi at r i o r _ s m i at r i ow _ s m i gfxior_smi gfxiow_smi seqior_smi seqiow_smi crtcior_smi crtciow_smi crtcio_smi vga_bl_smi isr0_smi misc_smi vg_bl_smi 313029282726252423222120191817161514131211109876543210 rsvd vga_res_change_mask rsvd isr1r_msk miscior_msk dacior_msk daciow_msk at r i o r _ m s k at r i ow _ m s k gfxior_msk gfxiow_msk seqior_msk seqiow_msk crtcior_msk crtciow_msk crtcio_msk vga_bl_msk isr0_msk misc_msk vg_bl_msk gld_msr_smi bit descriptions bit name description 63:61 rsvd reserved. set to 0. 60 vga_res_ change_smi vga resolution change smi. reading a 1 indicates that the vga?s output image size has changed while scaling is enabled. the handler for this smi should update the hori- zontal and/or vertical scale factor(s) accordingly. 59:49 rsvd reserved. set to 0. 48 isr1r_smi input status register 1 read smi. reading a 1 indicates that the vga input status register 1 has been read; writing this bit to 1 clears it. 47 miscior_smi miscellaneous output register read smi. reading a 1 indicates that the vga mis- cellaneous output register has been read; writing this bit to 1 clears it. 46 dacior_smi video dac register read smi. reading a 1 indicates that one or more of the vga?s video dac registers has been read; writing a 1 to this bit clears it. 45 daciow_smi video dac register write smi. reading a 1 indicates that one or more of the vga?s video dac registers has been written; writing a 1 to this bit clears it. 44 atrior_smi attribute register read smi. reading a 1 indicates that one or more of the vga?s attribute registers has been read; writing a 1 to this bit clears it. 43 atriow_smi attribute register write smi. reading a 1 indicates that one or more of the vga?s attribute registers has been written; writing a 1 to this bit clears it. 42 gfxior_smi graphics controller re gister read smi. reading a 1 indicates that one or more of the vga?s graphics controller registers has bee n read; writing a 1 to this bit clears it. 41 gfxiow_smi graphics controller re gister write smi. reading a 1 indicates that one or more of the vga?s graphics controller registers has been written; writing a 1 to this bit clears it.
amd geode? lx processors data book 307 display controller register descriptions 33234h 40 seqior_smi sequencer register read smi. reading a 1 indicates that one or more of the vga?s sequencer registers has been read; writing a 1 to this bit clears it. 39 seqiow_smi sequencer register write smi. reading a 1 indicates that one or more of the vga?s sequencer registers has been written; writing a 1 to this bit clears it. 38 crtcior_smi crtc register read smi. reading a 1 indicates that one or more of the vga?s crtc registers has been read; writing a 1 to this bit clears it. 37 crtciow_smi crtc register write smi. reading a 1 indicates that one or more of the vga?s crtc registers has been written; writi ng a 1 to this bit clears it. 36 crtcio_smi crtc invalid register i/o smi. reading a 1 indicates that this smi has been gener- ated; writing a 1 to this bit clears it; writing 0 has no effect. 35 vga_bl_smi vga vertical blank smi. reading a 1 indicates that the asmi corresponding to vga vertical blank has been triggered. writing a 1 to this bit clears it (and deactivates the asmi signal); writing a 0 to this bit has no effect. 34 isr0_smi input status register 0 smi. reading a 1 indicates that a synchronous smi was gen- erated because of a read to vga input status register 0. writing a 1 to this bit clears it; writing a 0 has no effect. 33 misc_smi miscellaneous out put register smi. reading a 1 indicates that a synchronous smi was generated due to a write to the miscellaneous output register. writing a 1 to this bit clears it; writing a 0 has no effect. 32 vg_bl_smi dc vertical blank smi. reading a 1 indicates that the asmi corresponding to dc ver- tical blank has been triggered. writing a 1 to this bit clears it (and deactivates the asmi signal); writing a 0 has no effect. 31:29 rsvd reserved. set to 0. 28 vga_res_ change_mask vga resolution change smi mask. when set to 1, disables generation of an asyn- chronous smi when all of the following conditions occur at once: - the vga timing engine is enabled. - scaling is enabled. - the horizontal or vertical resolution of the image produced by the vga timing engine changes. 27:17 rsvd reserved. set to 0. 16 isr1r_msk input status register 1 read smi mask. when set to 1, disables generation of the smi that indicates that vga input status register 1 has been read. 15 msicior_msk miscellaneous output register read smi. when set to 1, disables generation of the smi that indicates that the vga miscellaneous output register has been read. 14 dacior_msk video dac register read smi. when set to 1, disables gen eration of the smi that indicates that one or more of the vga?s video dac registers has been read. 13 daciow_msk video dac register write smi. when set to 1, disables generation of the smi that indicates that one or more of the vga?s video dac registers has been written. 12 atrior_msk attribute register read smi. when set to 1, disables gener ation of the smi that indi- cates that one or more of the vga?s attribute registers has been read. 11 atriow_msk attribute register write smi. when set to 1, disables generation of the smi that indi- cates that one or more of the vga?s attribute registers has been written. 10 gfxior_msk graphics controller re gister read smi. when set to 1, disables generation of the smi that indicates that one or more of the vga?s graphics controller registers has been read. gld_msr_smi bit descriptions (continued) bit name description
308 amd geode? lx processors data book display controller register descriptions 33234h 6.6.1.4 gld error msr (gld_msr_error) 9gfxiow_msk graphics controller re gister write smi. when set to 1, disables generation of the smi that indicates that one or more of the vga?s graphics controller registers has been written. 8 seqior_msk sequencer register read smi. when set to 1, disables generation of the smi that indicates that one or more of the vga?s sequencer registers has been read. 7 seqiow_msk sequencer register write smi. when set to 1, disables generation of the smi that indicates that one or more of the vga?s sequencer registers has been written. 6 crtcior_msk crtc register read smi. when set to 1, disables gener ation of the smi that indi- cates that one or more of the vga?s crtc registers has been read; writing a 1 to this bit clears it. 5crtciow_msk crtc register write smi. when set to 1, disables generation of the smi that indi- cates that one or more of the vga?s crtc registers has been written. 4 crtcio_msk crtc invalid register i/o smi mask. when set to 1, disables generation of a syn- chronous smi when a non-implemented vga crt controller register is read or writ- ten. 3vga_bl_msk vga vertical blank smi mask. when set to 1, disables generation of the vga vertical blank smi. 2 isr0_msk input status register 0 smi mask. when set to 1, disables generation of the vga input status register smi. 1misc_msk miscellaneous output register smi mask. when set to 1, disables generation of the miscellaneous output register synchronous smi. 0vg_bl_msk dc vertical blank smi mask. when set to 1, disables the dc vertical blank smi when set to 1. msr address 80002003h ty p e r / w reset value 00000000_00000000h gld_msr_smi bit descriptions (continued) bit name description gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd cwd_check_err syncbuf_err dfifo_err smi_err addr_err type_err 313029282726252423222120191817161514131211109876543210 rsvd cwd_check_mask syncbuf_mask dfifo_err_mask smi_err_mask addr_err_mask type_err_mask
amd geode? lx processors data book 309 display controller register descriptions 33234h gld_msr_error bit descriptions bit name description 63:38 rsvd reserved. set to 0. 37 cwd_check_err control word check error. reading a 1 indicates that an invalid control word was read from the display fifo, which is indicati ve of a fifo underrun. writing a 1 to this bit clears it. 36 syncbuf_err synchronizer buffer error. reading a 1 indicates that the display pipe attempted to read the synchronizer buffer while it was invalid. this is indicative of a synchronizer buffer underrun. writing a 1 to this bit clears it. 35 dfifo_err display fifo underrun error. reading a 1 indicates that the asynchronous error signal is being driven because the display fifo has ?run dry?. this implies that at least one frame of the display was corrupted. writing a 1 to this bit clears it; writing a 0 has no effect. 34 smi_err uncleared smi error. reading a 1 indicates that the asynchronous error signal is being driven because a second smi occurred while the first smi went unserviced. 33 addr_err unexpected address error. reading a 1 indicates that the exception flag was set because the dc received a gliu0 transaction request. 32 type_err unexpected type error. reading a 1 indicates that an asynchronous error has occurred because the dc received a gliu0 transaction with an undefined or unex- pected type. 31:6 rsvd reserved. set to 0. 5 cwd_check_msk control word check error mask. when set to 1, disables generation of the asyn- chronous error signal when an invalid control word is read from the data fifo. 4 syncbuf_msk synchronizer buffer error mask. when set to 1, disables generation of the asyn- chronous error signal when invalid data is read from the synchronizer buffer. 3 dfifo_err_mask display fifo underrun error mask. when set to 1, disables generation of the asyn- chronous error signal when at least one frame of the display was corrupted. 2 smi_err_mask uncleared smi error mask. when set to 1, disables generation of the asynchronous error signal when a second smi occurred while the first smi went unserviced. 1 addr_err_mask unexpected address error mask. when set to 1, disables generation of an excep- tion flag when the dc receives a gliu0 request. 0 type_err_mask unexpected type error mask. when set to 1, disables generation of the asynchro- nous error signal when the dc received a gliu0 transaction with an undefined or unexpected type.
310 amd geode? lx processors data book display controller register descriptions 33234h 6.6.1.5 gld power management msr (gld_msr_pm) 6.6.1.6 gliu0 device diagno stic msr (gld_msr_diag) this register is reserved for internal use by amd and should not be written to. msr address 80002004h ty p e r / w reset value 00000000_00000015h gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd vga_glclk_pmode dclk_pmode glclk_pmode gld_msr_pm bit descriptions bit name description 63:6 rsvd reserved. set to 0. 5:4 vga_glclk_ pmode vga gliu0 clock power management mode. this field controls the internal clock gating for the gliu0 clock to the vga module. 00: clock is not gated. 01: enable active hardware clock gating. ha rdware automatically det ermines when it is idle, and internally disables the gliu0 clock whenever possible. 10: reserved. 11: reserved. 3:2 dclk_pmode dot clock power management mode. this field controls the internal clock gating for the dot clock to all logic other than the vga unit. 00: clock is not gated. 01: enable active hardware clock gating. ha rdware automatically det ermines when it is idle, and internally disables the dot clock whenever possible. 10: reserved. 11: reserved. 1:0 g:clk_pmode gliu0 clock power management mode. this field controls the internal clock gating for the gliu0 clock to all logic other than the vga unit. 00: clock is not gated. 01: enable active hardware clock gating. ha rdware automatically det ermines when it is idle, and internally disables the gliu0 clock whenever possible. 10: reserved. 11: reserved. msr address 80002005h ty p e r / w reset value 00000000_00000000h
amd geode? lx processors data book 311 display controller register descriptions 33234h 6.6.2 display controller specific msrs 6.6.2.1 spare msr 6.6.2.2 dc ram control msr (dc_ram_ctl_msr) msr address 80000011h ty p e r / w reset value 00000000_00000000h spare_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd disable_vfifo_wm rsvd spare_msr bit descriptions bit name description 63:7 rsvd reserved. 6disable_ vfifo_wm disable video fifo watermarks. when set, the video watermarks in dc_arb_cfg[19:12] have no effect. 5:0 rsvd reserved. msr address 80000012h ty p e r / w reset value 00000000_02020202h dc_ram_ctl_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd cfifo_ctl rsvd dv_ram_ctl dc_ram_ctl_msr bit descriptions bit name description 63:11 rsvd reserved. 10:8 cfifo_ctl cfifo ram delay control. 7:3 rsvd reserved. 2:0 dv_ram_ctl dv ram delay control.
312 amd geode? lx processors data book display controller register descriptions 33234h 6.6.3 configuration and status registers all dc registers are dword accessible only. 6.6.3.1 dc unlock (dc_unlock) this register is provided to lock the most critical memo ry-mapped dc registers to prevent unwanted modification (write operations). read operations are always allowed. dc memory offset 000h ty p e r / w reset value 00000000h dc_unlock register map 313029282726252423222120191817161514131211109876543210 rsvd dc_unlock
amd geode? lx processors data book 313 display controller register descriptions 33234h dc_unlock bit descriptions bit name description 31:16 rsvd reserved. 15:0 dc_unlock unlock code. this register must be written with th e value 4758h in order to write to the protected registers. the fo llowing registers are protect ed by the locking mechanism: dc_general_cfg (dc memory offset 004h) dc_display_cfg (dc memory offset 008h) dc_arb_cfg (dc memory offset 00ch) dc_fb_st_offset (dc memory offset 010h) dc_cb_st_offset (dc memory offset 014h) dc_curs_st_offset (dc memory offset 018h) dc_vid_y_st_offset (dc memory offset 020h) dc_vid_u_st_offset (dc memory offset 024h) dc_vid_v_st_offset (dc memory offset 028h) dc_line_size (dc memory offset 030h) dc_gfx_pitch (dc memory offset 034h) dc_vid_yuv_pitch (dc memory offset 038h) dc_h_active_timing (dc memory offset 040h) dc_h_blank_timing (dc memory offset 044h) dc_h_sync_timing (dc memory offset 048h) dc_v_active_timing (dc memory offset 050h) dc_v_blank_timing (dc memory offset 054h) dc_v_sync_timing (dc memory offset 058h) dc_dfifo_diag (dc memory offset 078h) dc_cfifo_diag (dc memory offset 07ch) dc_vid_ds_delta (dc memory offset 080h) dc_gliu0_mem_offset (dc memory offset 084h) dc_dv_ctl (dc memory offset 088h) dc_gfx_scale (dc memory offset 090h) dc_irq_filt_ctl (dc memory offset 094h) dc_filt_coeff1 (dc memory offset 098h) dc_filt_coeff2 (dc memory offset 09ch) dc_vbi_even_ctl (dc memory offset 0a0h) dc_vbi_odd_ctl (dc memory offset 0a4h) dc_vbi_hor_ctl (dc memory offset 0a8h) dc_vbi_ln_odd (dc memory offset 0ach) dc_vbi_ln_even (dc memory offset 0b0h) dc_vbi_pitch (dc memory offset 0b4h) dc_clr_key (dc memory offset 0b8h) dc_clr_key_mask (dc memory offset 0bch) dc_clr_key_x (dc memory offset 0c0h) dc_clr_key_y (dc memory offset 0c4h) dc_genlk_ctl (dc memory offset 0d4h) dc_vid_even_y_st_offset (d c memory offset 0d8h) dc_vid_even_u_st_offset (d c memory offset 0dch) dc_vid_even_v_st_offset (dc memory offset 0e0h) dc_v_active_even_timing ( dc memory offset 0e4h) dc_v_blank_even_timing (dc memory offset 0e8h) dc_v_sync_even_timing (dc memory offset 0ech)
314 amd geode? lx processors data book display controller register descriptions 33234h 6.6.3.2 dc general config uration (dc_general_cfg) this register contains general control bits for the dc. unless otherwise noted in the bit descriptions table, settings written to this register do not take effect until the star t of the following frame or interlaced field. dc memory offset 004h ty p e r / w reset value 00000000h dc_general_cfg register map 313029282726252423222120191817161514131211109876543210 dbug dbsl cfrw diag crc_mode sgfr sgre sige sig_sel frc8pix rsvd yuvm vdse vgaft fdty stfm dfhpel dfhpsl vgae dece cmpe filt_sig_sel vide clr_cur cure dfle dc_general_cfg bit descriptions bit name description 31 dbug debug mode. effective immediately. 0: disable 1: enable. 30 dbsl debug select. effective immediately. 0: fifo control signals transmitted to debug port. 1: memory control signals transmitted to debug port. 29 cfrw compressed line buffer read/write select. effective immediately. only has effect if in di ag mode (bit 28 = 1). 0: write address enabled to compressed line buffer (clb) in diagnostic mode. 1: read address enabled to clb in diagnostic mode. 28 diag ram diagnostic mode. effective immediately. 0: normal operation. 1: ram diagnostic mode. this bit allows te stability of the on-chip display fifo and clb via the diagnostic access registers. a low to high transition rese ts the display fifo and compressed line buffer read and write pointers. 27 crc_mode crc mode. effective immediately. this bit selects the crc algorithm used to compute the signature. 0: nxt_crc[23:0] <= {crc [22:0], (crc[23], crc[3], crc[2])} ^ data[23:0]. 1: nxt_crc = (reset) ? 32?h01 :( {crc[30:0], 1?b0} ^ ((crc[31]) ? 32?h04c11db7 : 0) )^ data. 26 sgfr signature free run. effective immediately. 0: capture display signature for one frame. 1: capture display signature cont inuously for multiple frames. when this bit is cleared, the signature accumulation stops at the end of the current frame. 25 sgre signature read enable. effective immediately. 0: reads to dc_pal_data (dc memory offset 074h[23:0]) return palette data. 1: reads to dc_pal_data (dc memory offs et 074h[23:0]) return signature data. the palette address register content s are ignored in this case. note that the automatic pal- ette address increment mechanism will still operate even though the address is ignored.
amd geode? lx processors data book 315 display controller register descriptions 33234h 24 sige signature enable. effective immediately. 0: crc signature is reset to 000001h and held (no capture). 1: crc logic captures the pixel data signature with each pixel clock beginning with the next leading edge of vertical blank. note th at the crc logic treats each 24-bit pixel value as an autonomous 24-bit value (rgb color components are not captured sepa- rately in 8-bit signature registers). 23 sig_sel signature select. effective immediately. 1: causes the crc signature to be generated based on data being fed into the graphics scaling filter. this data stream does not include border/overscan pixels. 0: clearing this bit allows bit 4 to select be tween the crc calculatio n at the output of the scaler filter or the crc signat ure based on the data being output from the dc, including border/overscan pixels. also note that the crc calculation can be affected by the vbi crc enable bit, located in dc_vbi_even_ctl (dc memory offset 0a0h[31]). 22 frc8pix force 8-pixel character width. when vga mode is enabled, setting this bit forces the character width to be 8 pixels, overriding the se tting in bit 0 (8-dot character width) of the vga?s sequencer clocking mode register (index 01h). this causes the selection of an 8-pixel character width. this bit should be set for 640x480 flat panels when vga fixed timing mode is enabled. 21 rsvd reserved. always set to 0. 20 yuvm yuv mode. selects yuv display mode for video overlay. 0: yuv 4:2:2 display mode. 1: yuv 4:2:0 display mode. 19 vdse video downscale enable. 0: send all video lines to the display filter. 1: use dc_vid_ds_delta (dc memory offs et 080h[31:18]) as a digital differential analyzer (dda) delta value to skip certain video lines to support downscaling in the display filter. 18 vgaft vga fixed timing. when in vga mode (vgae bit 7 = 1), this bit indicates that the gliu block (dc) timing generator should provide the display timings. the vga will slave its display activity to the regular dc sync and display enable signals. the vga image will be centered on the screen, but not scaled to fi ll the screen. if upscaling is desired, the scaler filter should be used instead of this feature. the final image must have at least six more active lines than the native vga display settings indicate (i.e., at least three lines of bor- der on the top and bottom of the image). 17 fdty frame dirty mode. 0: frame buffer writes mark associated scan line dirty. used when fb_pitch (dc mem- ory offset 034h[15:0]) is equal to 1 kb, 2 kb, or 4 kb. 1: frame buffer writes mark entire frame as dirty. used when fb_pitch (dc memory offset 034h[15:0]) is not equal to 1 kb, 2 kb, or 4 kb. 16 stfm static frame mode. when compression is enabled (cmpe bit 5 = 1), this bit controls the update of dirty scan lines. 0: update dirty scan lines every frame. 1: update dirty scan lines every other frame. 15:12 dfhpel display-fifo high priority end level. this field specifies the depth of the display fifo (in multiples of 256 bytes) at which a high-pri ority request previously issued to the mem- ory controller will end. the value is dependent upon display mode. this field should always be non-zero and should be larger than the start level. note that the settings in the dc_arb_cfg register (dc memory offset 00ch) can also affect the priority of requests. dc_general_cfg bit desc riptions (continued) bit name description
316 amd geode? lx processors data book display controller register descriptions 33234h 11:8 dfhpsl display-fifo high priority start level. this field specifies the depth of the display fifo (in multiples of 256 bytes) at which a high-priority request is sent to the memory controller to fill up the fifo. the value is dependent upon display mode. this field should always be non-zero and should be less than the hi gh-priority end level. note that the set- tings in the dc_arb_cfg register (dc memory offset 00ch) can also affect the priority of requests. 7vgae vga enable. when changing the state of this bit, both the dc and vga should be stopped, and not actively fetching and displaying data. no other dc features operate with the vga pass-through feature enabled, with the exception of the crc/signature fe ature, the filters, and the timing generator (when the fil- ters or vga fixed timings are enabled). all other features should be turned off to prevent interference with vga operation. 0: normal dc operation. 1: allow the hardware vga use of the display fifo and the memory request interface. the vga hsync, vsync, blank, and pixel outputs are routed through the back end of the dc pixel and sync pipeline and then to the i/o pads. 6dece decompression enable. 0: disable display refresh decompression. 1: enable display refresh decompression. 5cmpe compression enable. 0: disable display refresh compression. 1: enable display refresh compression. 4 filt_sig_sel filter signature select. when bit 23 is clear and this bit is set, the crc mechanism at the output of the scaler filter (before the flicker filter) is enabled. setting this bit when bit 23 is also set has no effect. when both this bit and bit 23 are cleared, the crc is taken at the output of the dc, including the border/ove rscan pixels. also note that the crc calcu- lation can be affected by the vbi crc enable bit, located in dc_vbi_even_ctl (dc memory offset 0a0h[31]. 3vide video enable. 0: disable video port/overlay. 1: enable video port/overlay. 2 clr_cur color cursor. 0: 2-bpp format. 1: 32-bpp color cursor. 1 cure cursor enable. 0: disable hardware cursor. 1: enable hardware cursor. 0dfle display-fifo load enable. 0: disable display fifo. 1: enable display fifo. setting this bit high initiates display refresh requests to the mem- ory controller at the trailing edge of vertical sync. dc_general_cfg bit desc riptions (continued) bit name description
amd geode? lx processors data book 317 display controller register descriptions 33234h 6.6.3.3 dc display config uration (dc_display_cfg) this register contains configuration bits for co ntrolling the various display functions of the dc. unless otherwise noted, settings written to this register do not take effect until the start of the following frame or interlac ed field. dc memory offset 008h ty p e r / w reset value 00000000h dc_display_cfg register map 313029282726252423222120191817161514131211109876543210 rsvd visl rsvd pa l b dcen rsvd vfhpel vfhpsl 16bpp_mode disp_mode rsvd trup rsvd vden gden rsvd tgen dc_display_cfg bit descriptions bit name description 31:28 rsvd reserved. 27 visl vertical interrupt select. effective immediately. 0: smi generated at start of vertical blank when vien is enabled (bit 5 = 1). 1: smi generated at end of vertical syn c when vien is enabled (bit 5 = 1). 26 rsvd reserved. 25 palb pal bypass. 0: graphics data is routed through palet te ram in 16, 24, and 32-bpp display modes. 1: graphics data bypasses palette ram in 16, 24, and 32-bpp display modes. while con- figured in this mode, 2-bpp cursor and bord er overlays are supported, but the palette entries for these items must be modified. see section 6.6.7.1 on page 335 for more information. 24 dcen display center. 0: normal active portion of scan line is qualified with dispen (ball ae4). 1: border and active portions of scan line are qualified with dispen. this enables cen- tering the display for flat panels. 23:20 rsvd reserved. 19:16 vfhpel video-fifo high priority end level. this field specifies the depth of the video fifo (in multiples of 64 bytes) at which a high priority request previously issued to the memory controller for video data will end. this field should always be non-zero and should be larger than the start level. note that th e settings in the dc_arb_cfg register (dc mem- ory offset 00ch) can also affect the priority of requests. this field should be set to 0 if video overlay is disabled. 15:12 vfhpsl video-fifo high priority start level. this field specifies the depth of the video fifo (in multiples of 64 bytes) at which a high priority request is sent to the memory controller to fill up the video fifo. this field should always be non-zero and should be less than the high-priority end level. note that the settin gs in the dc_arb_cfg register (dc memory offset 00ch) can also affect the priority of requests. 11:10 16bpp_mode per-pixel mode. based on the number of bits per pixel (disp_mode bits [9:8] must equal 01), this determines how those bits are allocated to color and alpha information: for 16-bpp display format: 00: 16-bpp (rgb 5:6:5) 01: 15-bpp (rgb 5:5:5) 10: xrgb (argb 4:4:4) 11: reserved
318 amd geode? lx processors data book display controller register descriptions 33234h 9:8 disp_mode display mode. bits per pixel. 00: 8-bpp (also used in vga emulation) 01: 16-bpp 10: 24-bpp (rgb 8:8:8) 11: 32-bpp 7 rsvd reserved. 6trup timing register update. effective immediately. 0: prevent update of working timing registers. this bit should be set low when a new tim- ing set is being programmed, but the display is still running with the previously pro- grammed timing set. 1: update working timing registers on next active edge of vertical sync. 5 rsvd reserved. 4vden video data enable. set this bit to 1 to allow transfer of video data to the vp. 3gden graphics data enable. set this bit to 1 to allow transfer of graphics data through the dis- play pipeline. 2:1 rsvd reserved. 0tgen timing generator enable. effective immediately. 0: disable timing generator. 1: enable timing generator. this bit must be set to 0 when using vga mode unless the filters or vga fixed timings are also enabled (dc_general_cfg register, bit 18, dc memory offset 004h[18]). dc_display_cfg bit descriptions (continued) bit name description
amd geode? lx processors data book 319 display controller register descriptions 33234h 6.6.3.4 dc arbitration co nfiguration (dc_arb_cfg) this register contains configuration bits for controlling the priority level of gliu requests by the dc. it allows high priorit y to be enabled under several conditions (see bits [8:1]). these c onditions are ored with other s ources of high-priority, includ- ing the fifo watermark mechanisms. settings written to this register ta ke effect immediately. the features in this register do not affect the dc?s internal prioritization of video vs. graphics data fetches -- just the priority that is presented on the geodelink request. the low priority at vsync mechanism (bits [15:9, 0]) takes precedence over all priority mechanisms except the high priority when line buffer fill in progress? mechanism bit [1]. dc memory offset 00ch ty p e r / w reset value 00000000h dc_arb_cfg register map 313029282726252423222120191817161514131211109876543210 rsvd lb_load_wm_en lb_load_wm lpen_end_count hpen_sb_inv hpen_fb_inv_halfsb hpen_fb_inv_sbrd hpen_fb_inv hpen_1lb_inv hpen_2lb_inv hpen_3lb_inv hpen_lb_fill lpen_vsync dc_arb_cfg bit descriptions bit name description 31:21 rsvd reserved. 20 lb_load_wm_ en line buffer load watermark enable. when set, allows line buffer loads from the dis- play fifo to begin when the display fifo ha s at least as much data as defined by the watermark in bits [19:16] (lb_load_wm). when this bit is cleared, line buffer loads are not permitted until the display fifo is full. 19:16 lb_load_wm line buffer load watermark. when enabled via bit 20 (lb_load_wm_en), this watermark determines how much data must be in the dfifo before a line buffer load is permitted. this level is set in 256-byte increments. 15:9 lpen_end_ count low priority end counter. when bit 0 (lpen_vsync) is se t, this field indicates the number of scan lines after vsync that the dc will force its requests to low priority. because the line buffers, flicker filter buffers, sync buffer, and data fifo are all cleared at vsync, this mechanism prevents the dc from sp ending an inordinate amount of time in high priority while filling all of these buffers. in most cases this value should be set three or four lines less than the distance between vsync start and v_total. this value may need to be lowered if vbi data is enabled. 8 hpen_sb_inv high priority enable when sync buffer invalid. this bit enables the dc to arbitrate in high priority whenever the synchronizer buffer does not contain valid data. 7 hpen_fb_inv_ halfsb high priority enable when flicker buffer invalid and sync buffer less than half full. this bit enables the dc to arbitrate in high priority whenever the synchronizer buffer is less than half full and the flicker filter buffer does not contain valid data. 6 hpen_fb_inv_ sbrd high priority enable when flicker bu ffer invalid and sync buffer being read. this bit enables the dc to arbitrate in high priority whenever the synchronizer buffer is being read and the flicker filter buffer does not contain valid data. 5 hpen_fb_inv high priority enable when flicker buffer invalid. this bit enables the dc to arbitrate at high priority whenever the flicker f ilter buffer does not contain valid data. 4 hpen_1lb_inv high priority enable when any one line buffer invalid. this bit enables the dc to arbitrate at high priority if any of the three line buffers is invalid. (when the scaler filter is disabled, only one logical line buffer is used , and the state of the others is ignored.)
320 amd geode? lx processors data book display controller register descriptions 33234h 3 hpen_2lb_inv high priority enable when any two line buffers invalid. this bit enables the dc to arbitrate at high priority if the scaler filter is enabled and any two of the three line buffers that feed this filter are invalid. (the state of this bit is igno red if the scaler filter is dis- abled.) 2 hpen_3lb_inv high priority enable when any three line buffers invalid. this bit enables the dc to arbitrate at high priority if the scaler filter is enabled and all of the three line buffers that feed this filter are invalid. (the state of this bit is ignored if the scaler filter is disabled.) 1 hpen_lb_fill high priority enable when line buffer fill in progress. this bit enables the dc to maintain high priority requests whenever it is in the process of filling a line buffer. the line buffer fill requires an entire scan line of data to be read from the data fifo without inter- ruption. because the fifo typically does not contain a full scan line of data, it is neces- sary to fetch additional data from memory during this process. 0 lpen_vsync low priority enable at vsync. when this bit is set, the dc is forced to arbitrate at low priority for a number of lines after the st art of vsync. (this number of lines is pro- grammed in bits [15:9] (lpen_end_count)) beca use the line buffers, flicker filter buff- ers, sync buffer, and data fifo are all cl eared at vsync, this mechanism prevents the dc from spending an inordinate amount of time in high priority while filling all of these buffers. in most cases this value should be set three or four lines less than the distance between vsync start and v_total this value may need to be lowered if vbi data is enabled. during this low priority period after vsync, this mechanism over rides the watermark mechanism for the data fifo and all of the ot her mechanisms in this register except the high priority enable when line buffer fill in progress mechanism enabled in bit 1 (hpen_lb_fill). outside of this period, this mechanism has no effect on the priority level of outgoing dc requests on the gliu. dc_arb_cfg bit descriptions (continued) bit name description
amd geode? lx processors data book 321 display controller register descriptions 33234h 6.6.4 memory organization registers the graphics memory region is up to 16 mb in size. the gr aphics memory is made up of the normal uncompressed frame buffer, compressed display buffer, cursor buffer, cursor color bu ffer (for 16-bit color cursor), and video buffer(s). each buff er begins at a programmable offset within the graphics memory region. the various memory buffers are arranged so as to effici ently pack the data within the graphics memory region. this requires flexibility in the way that the buffers are arranged wh en different display modes are in use. the cursor and cursor color buffers are linear blocks, so addre ssing is straightforward. the frame buffer and compressed display buffer are arranged based upon scan lines. each scan line has a maximum number of valid or active qwords and a pitch that, when added to the previous line offset, points to the next line. in th is way, the buffers may be stored as linear blocks or as recta n- gular blocks. the various buffers? addresses are all located within t he same 1 mb-aligned region. thus, a separate register, dc_gliu0_mem_offset (dc memory offset 084h), is used to set a 1 mb-aligned base address. gart address translation is not supported. 6.6.4.1 dc frame buffer star t address (dc_fb_st_offset) this register specifies the offset at which the frame buffer st arts. settings written to this register do not take effect until the start of the following frame or interlaced field. dc memory offset 010h ty p e r / w reset value xxxxxxxxh dc_fb_st_offset 313029282726252423222120191817161514131211109876543210 rsvd offset dc_fb_st_offset bit descriptions bit name description 31:28 rsvd reserved. 27:0 offset frame buffer start offset. this value represents the byte offset of the starting location of the displayed frame buffer. this value may be changed to achieve panning across a virtual desktop or to allow multiple buffering. when this register is programmed to a non-zero value, the compression logic should be disabled. the memory address defined by bits [2 7:3] takes effect at the start of the next frame scan. the pixel offset defined by bits [2 :0] is latched at the end of vertical sync and added to the pixel panning offset to determine the actual panning value.
322 amd geode? lx processors data book display controller register descriptions 33234h 6.6.4.2 dc compression buffer start address (dc_cb_st_offset) this register specifies the offset at which the compressed displa y buffer starts. settings written to this register do not take effect until the start of the foll owing frame or interlaced field. 6.6.4.3 dc cursor buffer star t address (dc_curs_st_offset) this register specifies the offset at whic h the cursor memory buffer starts. settings written to this register do not take effe ct until the start of the followi ng frame or interlaced field. dc memory offset 014h ty p e r / w reset value xxxxxxxxh dc_cb_st_offset register map 313029282726252423222120191817161514131211109876543210 rsvd offset 0h dc_cb_st_offset bi t descriptions bit name description 31:28 rsvd reserved. 27:0 offset compressed display buffer start offset . this value represents the byte offset of the starting location of the comp ressed display buffer. the lower five bits should always be programmed to zero so that the start offset is aligned to a 32-byte boundary. this value should change only when a new display mode is set due to a change in size of the frame buffer. dc memory offset 018h ty p e r / w reset value xxxxxxxxh dc_curs_st_offset register map 313029282726252423222120191817161514131211109876543210 rsvd offset 0h dc_curs_st_offset bit descriptions bit name description 31:28 rsvd reserved. 27:0 offset cursor start offset . this value represents the byte of fset of the starti ng location of the cursor display pattern. the lower five bits should always be programmed to zero so that the start offset is 32-byte aligne d. note that if there is a y of fset for the cursor pattern, the cursor start offset should be set to point to the first displayed line of the cursor pattern.
amd geode? lx processors data book 323 display controller register descriptions 33234h 6.6.4.4 dc video y buffer start addr ess offset (dc_ vid_y_st_offset) this register specifies th e offset at which the video y (yuv 4:2: 0) or yuv (yuv 4:2:2) buffer starts. the upper 4 bits of this register are for the field count mechanism. this mechanism, which did not exist on previous amd geode processors, allows the dc to fetch multiple fields or frames of vip data without requiring software intervention to move the offset. this mechanism has t he constraint that the buffers for multip le video frames must be contiguous in memory. (the vip hardware will meet this constraint.) settings written to this register do not take effect until the start of the following frame or interlaced field. 6.6.4.5 dc video u buffer start ad dress offset (dc_vid_u_st_offset) this register specifies the offset at which the video u (yuv 4:2:0) buffer starts. settings written to this register do not take effect until the start of the following frame or interlaced field. dc memory offset 020h ty p e r / w reset value xxxxxxxxh dc_vid_y_st_offset register map 313029282726252423222120191817161514131211109876543210 rsvd offset 0h dc_vid_y_st_offset bit descriptions bit name description 31:28 rsvd reserved. reserved for field count mechanism 27:0 offset video y buffer start offset. this value represents the starting location for video y buffer. the lower five bits should always be programmed as zero so that the start offset is aligned to a 32-byte boundary. if yuv 4:2:2 mode is selected (dc memory offset 004h[20] = 0), the video y buffer is used as a singular buffer holding interleaved y, u and v data. if yuv 4:2:0 is selected (dc memory o ffset 004h[20] = 1), the video y buffer is used to hold only y data while u and v data are stored in separate buffers whose start offsets are represented in dc_vid_u_st_o ffset (dc memory offset 024h[27:0]) and dc_vid_v_st_offset (dc memory offset 028h[27:0]). dc memory offset 024h ty p e r / w reset value xxxxxxxxh dc_vid_u_st_offset register map 313029282726252423222120191817161514131211109876543210 frame_count offset 0
324 amd geode? lx processors data book display controller register descriptions 33234h 6.6.4.6 dc video v buffer start addr ess offset (dc_ vid_v_st_offset) this register specifies the offset at which the video v buffer starts. settings written to this register do not take effect until the start of the following frame or interlaced field. 6.6.4.7 dc dirty/valid re gion top (dc_dv_top) this register specifies the top of the frame buffer memory region to be watched for frame-dirty mode. settings written to this register take effect immediately. dc_vid_u_st_offset bit descriptions bit name description 31:28 frame_count frame count. when reading this register, this fiel d indicates the current frame count, as determined by counting rising edges of vip vsync. this value is reset to 0 when vip_vsync occurs and frame_cnt >= frame_li mit. it can also be written to pro- vide a mechanism for software to synchronize activities between the vip and the dis- play controller. however, this can result in corrupted video data until the next reset of this counter. 27:0 offset video u buffer start offset . this value represents the starting location for the video u buffer. the lower three bits should always be programmed as zero so that the start off- set is aligned to a qword boundary. a buffer for u data is only used if yuv 4:2:0 dis- play mode is selected (dc memory offset 004h[20] = 1). dc memory offset 028h ty p e r / w reset value xxxxxxxxh dc_vid_v_st_offset register map 313029282726252423222120191817161514131211109876543210 rsvd offset 0 dc_vid_v_st_offset bit descriptions bit name description 31:28 rsvd reserved. 27:0 offset video v buffer start offset . this value represents the starting location for the video v buffer. the lower three bits should always be programmed as zero so that the start offset is aligned to a qword boundary. a buffer for v data is only used if yuv 4:2:0 display mode is selected (dc memory offset 004h[20] = 1). dc memory offset 02ch ty p e r / w reset value 00000000h dc_dv_top register map 313029282726252423222120191817161514131211109876543210 rsvd dv_top rsvd dv_top_en
amd geode? lx processors data book 325 display controller register descriptions 33234h 6.6.4.8 dc line si ze (dc_line_size) this register specifies the number of bytes to transfer for a line of frame buffer, compression buffer, and video buffer data. the compressed line buffer is invalidated if it exceeds the cb_line_size (bits [18:12]). settings written to this register do not take effect until the start of the following frame or interlaced field. dc_dv_top bit descriptions bit name description 31:24 rsvd reserved. these bits should be programmed to zero. 23:10 dv_top_addr dirty/valid region top address. when enabled via bit 0 (dv_top_en), this field indi- cates the size of the region to be watched for frame buffer accesses. when writes to this region occur and the compression logic is in frame-dirty mode, the frame is marked as dirty. (writes outside this region, regardless of the settings in the dv_ctl register (dc memory offset 088h), do not cause the frame to be marked as dirty in frame-dirty mode.) the bits in this field correspond to address bits [23:10]. 9:1 rsvd reserved. these bits should be programmed to zero. 0 dv_top_en dirty/valid region top enable. this bit enables the top-of-region check for frame-dirty mode. this bit should be cleared if the compression logic is not configured for frame- dirty mode. dc memory offset 030h ty p e r / w reset value xxxxxxxxh dc_line_size register map 313029282726252423222120191817161514131211109876543210 rsvd vid_line_size rsvd cb_line_size rsvd fb_line_size dc_line_size bit descriptions bit name description 31:30 rsvd reserved. these bits should be programmed to zero. 29:20 vid_line_size video line size. this value specifies the number of qwords (8-byte segments) to transfer for each source line from the video buffer in yuv 4:2:2 mode. in yuv 4:2:0 mode, it specifies the number of qwords to transfer for the u or v stream for a source line (2x this amount is transferred for the y st ream). in yuv 4:2:2 mode, this field must be set to a multiple of four qwords -- bits [21:20] must be 0. 19 rsvd reserved. this bit should be programmed to zero. 18:12 cb_line_size compressed display buffer line size. this value represents the number of qwords for a valid compressed line plus 1. it is us ed to detect an overflow of the compressed data fifo. when the compression data for a line reaches cb_line_size qwords, the line is deemed incompressible. note that dc actually writes cb_line_size + 4 qwords to memory, so if x qwords are allocated for each compression line, then x - 4 + 1 (or x - 3) should be programmed into this register. note also that the cb_line_size field should never be larger than 65 (041h) since the maximum size of the compressed data fifo is 64 qwords. 11:10 rsvd reserved. these bits should be programmed to zero. 9:0 fb_line_size frame buffer line size. this value specifies the number of qwords (8-byte seg- ments) to transfer for each display line from the frame buffer.
326 amd geode? lx processors data book display controller register descriptions 33234h 6.6.4.9 dc graphics pi tch (dc_gfx_pitch) this register stores the pitch for the graphics display buffers. 6.6.4.10 dc video yuv pi tch (dc_vid_yuv_pitch) this register stores the pitch for the video buffers. dc memory offset 034h ty p e r / w reset value xxxxxxxxh dc_gfx_pitch register map 313029282726252423222120191817161514131211109876543210 cb_pitch fb_pitch dc_gfx_pitch bit descriptions bit name description 31:16 cb_pitch compressed display buffer pitch. this value represents the number of qwords between consecutive scan lines of compressed buffer data in memory. this pitch must be set to a multiple of four qwords (i.e., bits [17:16] must be 00). 15:0 fb_pitch frame buffer pitch. this value represents the num ber of qwords between consecu- tive scan lines of frame buffer data in memory. dc memory offset 038h ty p e r / w reset value xxxxxxxxh dc_vid_yuv_pitch register map 313029282726252423222120191817161514131211109876543210 uv_pitch y_pitch dc_vid_yuv_pitch bit descriptions bit name description 31:16 uv_pitch video u and v buffer pitch. this value represents the number of qwords between consecutive scan lines of u or v buffer data in memory. (u and v video buffers are always the same pitch.) a pitch up to 512 kb is supported to allow for vertical decimation for downscaling. 15:0 y_pitch video y buffer pitch. this value represents the number of qwords between consecu- tive scan lines of y buffer data in memory. a pitch up to 512 kb is supported to allow for vertical decimation for downscaling.
amd geode? lx processors data book 327 display controller register descriptions 33234h 6.6.5 timing registers the dc timing registers control the generat ion of sync, blanking, and active displa y regions. these registers are generally programmed by the bios from an int 10h call or by the extended mode driver from a display timing file. example: to display a 1024x768 graphics (frame buffer) image on a 720x483/59.94 television. the dc crtc settings are as follows: note: the above timings are based on tables b.1 and b.2 in the ansi/smtpe 293m-1996 spec. they assume that the frame buffer image should be displayed over the entire 720x483 screen, with no additional border. the dc_gfx_scale (dc memory offset 090h) register would be set up to scale the 1024x768 image to a 720x483 frame: v_scale = (768/(483-1)) = 1.593360995... h_scale = (1024/(720 - 1)) = 1.424200278... dc_gfx_scale = 65f9_5b26h (v_scale = 1.593322754; h_scale = 1.424194336) in addition, the filt_ena and intl_en bits would be set (dc memory offset 94h[12,11] = 11) , and the filter coefficients would be programmed. this example also presumes that th e flick_en bit is set (dc memory offset 0d4h[24] = 1). because the output is to be interlaced, the flicker filter can be used. (use of the flicker fi lter is not required.) for inform ation on the configuration bits for the flicker filter, see "dc genlock control (dc_genlk_ctl)" on page 350. dc_h_active_timing (040h) = 0x035a_02d0 // h_total = 858; h_active = 720 dc_h_blank_timing (044h) = 0x35a_02d0 // h_bl ank_start = 720; h_blank_end=858 -- no overscan dc_h_sync_timing (048h) = 0x031f_02e0 // h_sync start = 736; h_sync_end = 799 dc_v_active_timing (050h) = 0x0106_00f1 // v_total = 262 (even) 263(odd); v_active = 241 (even & odd) dc_v_blank_timing (054h) = 0x0106_00f1 // v_blan k_start = 241; v_blank_end = 262 -- no overscan dc_v_sync_timing (058h) = 0x00f6_00f5 // v_sync_sta rt = 245; vsync_end = 246 dc_v_active_even_timing (0e4h) = 0x0105_00f0 // v_total = 261; v_active = 240 dc_v_blank_even_timing (0e8h) = 0x0105_00f0 // v_blank_start = 240; v_blank_end = 261 dc_v_sync_even_timing (0ech) = 0x00f6_00f5 // v_sync_start = 245; v_sync_end = 246 dc_b_active (05ch) = 03ff_02ffh // frame buffer size1024x768
328 amd geode? lx processors data book display controller register descriptions 33234h 6.6.5.1 dc horizontal and tota l timing (dc_h_active_timing) this register contains horizontal ac tive and total timing information. dc memory offset 040h ty p e r / w reset value xxxxxxxxh dc_h_active_timing register map 313029282726252423222120191817161514131211109876543210 rsvd h_total rsvd h_active dc_h_active_timing bit descriptions bit name description 31:28 rsvd reserved. these bits should be programmed to zero. 27:16 h_total horizontal total. this field represents the total number of pixel clocks for a given scan line minus 1. note that the value must repr esent a value greater than the h_active field (bits [11:0]) because it includes border pixels and blanked pixels. for flat panels, this value will never change. unlike previous versions of the dc, the horizontal total can be programmed to any pixel granularity; it is not limited to character (8-pixel) granularity. 15:12 rsvd reserved . these bits should be programmed to zero. 11:0 h_active horizontal active . this field represents the total number of pixel clocks for the displayed portion of a scan line minus 1. note that for fl at panels, if this value is less than the panel active horizontal resolution (h_panel), the parameters h_blk_start, h_blk_end (dc memory offset 044h[11: 0, 27:16]), h_sync_st, and h_sync_end (dc memory offset 048h[11:0, 27:16]) shoul d be reduced by the value of h_adjust (or the value of h_panel - h_active / 2) to achieve horizontal centering. unlike previous versions of the dc, this field can be programmed to any pixel granularity; it is not limited to character (8-pixel) granularity. if graphics scaling is enabled, this value re presents the width of the final (scaled) image to be displayed. the width of the frame buffer image may be different in this case; dc_fb_active (dc memory offset 05ch) is used to program the horizontal and verti- cal active values in the frame buffer when graphics scaling is enabled. h_active must be set to at least 64 pixels.
amd geode? lx processors data book 329 display controller register descriptions 33234h 6.6.5.2 dc crt horizo ntal blanking timi ng (dc_h_blank_timing) this register contains crt hori zontal blank timing information. note: a minimum of 32 pixel clocks is required for the horizontal blanking portion of a line in order for the timing generator to function correctly. 6.6.5.3 dc crt horizontal sync timing (dc_h_sync_timing) this register contains crt horizontal syn c timing information. note however, that this register should also be programmed appropriately for flat panel only display, since the horizo ntal sync transition determines when to advance the vertical counter. dc memory offset 044h ty p e r / w reset value xxxxxxxxh dc_h_blank_timing register map 313029282726252423222120191817161514131211109876543210 rsvd h_blk_end rsvd h_blk_start dc_h_blank_timing bit descriptions bit name description 31:28 rsvd reserved. these bits should be programmed to zero. 27:16 h_blk_end horizontal blank end. this field represents the pixel cl ock count at which the horizontal blanking signal becomes inactive minus 1. unlike previous versions of the dc, this field can be programmed to any pixel granularity; it is not limited to character (8-pixel) granularity. 15:12 rsvd reserved. these bits should be programmed to zero. 11:0 h_blk_start horizontal blank start. this field represents the pixel clock count at which the horizon- tal blanking signal becomes active minus 1. unlike previous versions of the dc, this field can be programmed to any pixel granularity; it is not limited to character (8-pixel) granularity. dc memory offset 048h ty p e r / w reset value xxxxxxxxh dc_h_sync_timing register map 313029282726252423222120191817161514131211109876543210 rsvd h_sync_end rsvd h_sync_st dc_h_sync_timing bit descriptions bit name description 31:28 rsvd reserved. these bits should be programmed to zero. 27:16 h_sync_end horizontal sync end. this field represents the pixel clock count at which the crt hori- zontal sync signal becomes inactive minus 1. unlike previous versions of the dc, this field can be programmed to any pixel granularity; it is not limited to character (8-pixel) granularity. the horizontal sync must be at least 8 pixels in width.
330 amd geode? lx processors data book display controller register descriptions 33234h 6.6.5.4 dc vertical and total timing (dc_v_active_timing) this register contains vertical active and total timing inform ation. the parameters pertain to both crt and flat panel display. all values are specified in lines. 15:12 rsvd reserved. these bits should be programmed to zero. 11:0 h_sync_st horizontal sync start. this field represents the pixel clock count at which the crt hori- zontal sync signal becomes active minus 1. unlike previous versions of the dc, this field can be programmed to any pixel granularity; it is not limited to character (8-pixel) granularity. the horizontal sync must be at least 8 pixels in width, and cannot begin until at least 8 pixels after h_blk_start (dc memory offset 044h[11:0]). dc memory offset 050h ty p e r / w reset value xxxxxxxxh dc_h_sync_timing bit descriptions bit name description dc_v_active_timing register map 313029282726252423222120191817161514131211109876543210 rsvd v_total rsvd v_active dc_v_active_timing bit descriptions bit name description 31:27 rsvd reserved. these bits should be programmed to zero. 26:16 v_total vertical total . this field represents the total number of lines for a given frame scan minus 1. note that the value is necessarily greater than the v_active field (bits [10:0]) because it includes border lines and blanked lines. if the display is interlaced, the total number of lines must be odd, so this value should be an even number. 15:11 rsvd reserved. these bits should be programmed to zero. 10:0 v_active vertical active. this field represents the total number of lines for the displayed portion of a frame scan minus 1. note that for flat panels, if this value is less than the panel active vertical resolution (v_panel), the par ameters v_blank_start, v_blank_end (dc memory offset 054h[10:0, 26:16]), v_sy nc_start, and v_sync_end (dc memory offset 058h[10:0, 26:16]) should be reduc ed by the following value (v_adjust) to achieve vertical centering: v_adjust = (v_panel - v_active) / 2 if the display is interlaced, the number of active lines should be even, so this value should be an odd number. if graphics scaling is enabled (and interleaved display is disabled), this value represents the height of the final (scaled) image to be di splayed. the height of the frame buffer image may be different in this case; dc_fb_active (dc memory offset 05ch) is used to program the horizontal and vertical active values in the frame buffer when graphics scaling is enabled. if interleaved mode is enabled, this value re presents half the height of the final (scaled and interleaved) displayed image.
amd geode? lx processors data book 331 display controller register descriptions 33234h 6.6.5.5 dc crt vertical blan k timing (dc_v_blank_timing) this register contains vertical blank timi ng information. all values are specified in lines. for interlaced display, no border is supported, so blank timing is implied by the total/active timing. 6.6.5.6 dc crt vertical sync timing (dc_v_sync_timing) this register contains crt vertical sync timing information. all values are specified in lines. dc memory offset 054h ty p e r / w reset value xxxxxxxxh dc_v_blank_timing register map 313029282726252423222120191817161514131211109876543210 rsvd v_blank_end rsvd v_blank_start dc_v_blank_timing bit descriptions bit name description 31:27 rsvd reserved. these bits should be programmed to zero. 26:16 v_blank_end vertical blank end. this field represents the line at which the vertical blanking signal becomes inactive minus 1. if the display is interlaced, no border is supported, so this value should be identical to v_total. 15:11 rsvd reserved. these bits should be programmed to zero. 10:0 v_blank_ start vertical blank start. this field represents the line at which the vertical blanking signal becomes active minus 1. if the display is interlaced, this value should be programmed to v_active plus 1. dc memory offset 058h ty p e r / w reset value xxxxxxxxh dc_v_sync_timing register map 313029282726252423222120191817161514131211109876543210 rsvd v_sync_end rsvd v_sync_start dc_v_sync_timing bit descriptions bit name description 31:27 rsvd reserved. these bits should be programmed to zero. 26:16 v_sync_end vertical sync end. this field represents the line at which the crt vertical sync signal becomes inactive minus 1. 15:11 rsvd reserved. these bits should be programmed to zero. 10:0 v_sync_ start vertical sync start. this field represents the line at which the crt vertical sync signal becomes active minus 1. for interlaced displa y, note that the vertical counter is incre- mented twice during each line and since there are an odd number of lines, the vertical sync pulse will trigger in the middle of a line for one field and at the end of a line for the subsequent field.
332 amd geode? lx processors data book display controller register descriptions 33234h 6.6.5.7 dc frame buffer active region register (dc_fb_active) 6.6.6 cursor position and line count/status registers the cursor registers contain pixel coordinate information for t he cursor. these values are not latched by the timing genera- tor until the start of the frame to avoid tearing artifacts when moving the cursor. the line count/status register holds status information for t he current display status, including the current scan line for the display. 6.6.6.1 dc cursor x po sition (dc_cursor_x) this register contains the x position information of the hardware cursor. settings written to this register do not take effect until the start of the following frame or interlaced field. dc memory offset 05ch ty p e r / w reset value xxxxxxxxh dc_fb_active register map 313029282726252423222120191817161514131211109876543210 fb_h_active fb_v_active dc_fb_active bit descriptions bit name description 31:16 fb_h_active horizontal frame bu ffer active end. this field is used only when graphics scaling is enabled. the lower three bits of this register are ignored and presumed to be 111. includ- ing these bits, the value in this field represents the total number of pixels in a line in the graphics frame buffer minus 1. this field is analogous to the h_active field in the dc_h_active_timing register (dc memory offset 040h[11:0]), except that th is field is used only for the fetching and rendering of pixel data, not the display timings. when graphics scaling is disabled, this field is not used. (the h_active field is used instead. 15:0 fb_v_active vertical frame buffer active. this field is used only when graphics scaling is enabled. it represents the total number of lines in the graphics frame buffer minus 1. this field is analogous to the v_active fiel d in the dc_v_active_timing register (dc memory offset 050h[10:0]), except that this field is used only for the fetching and render- ing of pixel data, not the display timings. when graphics scaling is disabled, this field is not used. (the v_active field is used instead.) dc memory offset 060h ty p e r / w reset value xxxxxxxxh dc_cursor_x register map 313029282726252423222120191817161514131211109876543210 rsvd x_offset cursor_x dc_cursor_x bit descriptions bit name description 31:17 rsvd reserved.
amd geode? lx processors data book 333 display controller register descriptions 33234h 6.6.6.2 dc cursor y po sition (dc_cursor_y) this register contains the y position information of the hardware cursor. settings written to this register will not take effect until the start of the followi ng frame or interlaced field. 6.6.6.3 dc line count/stat us (dc_line_cnt/status) this register contains status informat ion for the current display state, includi ng the current scan line for the display (v_line_cnt). this portion of t he register is read only and is used by software to time update the frame buffer to avoid tearing artifacts. this scan line value is driven directly off of the dot clock, and consequently it is not synchronized with t he cpu clock. software should read this register twice and compar e the result to ensure that the value is not transitioning. several additional read only display status bits are provided to allow software to properly time the programming of registers and to detect the source of display generated interrupts. 16:11 x_offset x offset. this field represents the x pixel offset within the 64x64 cursor pattern at which the displayed portion of the cursor is to begin. normally, this value is set to zero to dis- play the entire cursor pattern, but for cursors for which the ?hot spot? is not at the left edge of the pattern, it may be necessary to display the right-most pixels of the cursor only as the cursor moves close to the left edge of the display. 10:0 cursor_x cursor x. this field represents the x coordinate of the pixel at which the upper left cor- ner of the cursor is to be displayed. this value is referenced to the screen origin (0,0), which is the pixel in the upper left corner of the screen. dc memory offset 064h ty p e r / w reset value xxxxxxxxh dc_cursor_x bit descriptions bit name description dc_cursor_y register map 313029282726252423222120191817161514131211109876543210 rsvd y_offset cursor_y dc_cursor_y bit descriptions bit name description 31:17 rsvd reserved. 16:11 y_offset y offset. this field represents the y line offset within the 64x64 cursor pattern at which the displayed portion of the cursor is to begin. normally, this value is set to zero to dis- play the entire cursor pattern, but for cursors for which the ?hot spot? is not at the top edge of the pattern, it may be necessary to display the bottom-most lines of the cursor only as the cursor moves close to the top edge of the display. note that if this value is non-zero, the dc_curs_st_offset (dc memory offset 018h) must be set to point to the first cursor line to be displayed. 10:0 cursor_y cursor y. this field represents the y coordinate of the line at which the upper left corner of the cursor is to be displayed. this value is referenced to the screen origin (0,0), which is the pixel in the upper left corner of the screen. dc memory offset 06ch ty p e r o reset value xxxxxxxxh
334 amd geode? lx processors data book display controller register descriptions 33234h dc_line_cnt/status register map 313029282726252423222120191817161514131211109876543210 dna vna vsa rsvd flip v_line_cnt vflip sigc even_field rsvd dot_line_cnt dc_line_cnt/status bit descriptions bit name description 31 dna display not active. 0: display active. 1: display not active (i.e., blanking or border). 30 vna vertical not active. 0: vertical display active. 1: vertical display not active (i.e., vertical blanking or border). 29 vsa vertical sync active. 0: vertical sync not active. 1: vertical sync active. 28 rsvd reserved. 27 flip flip. 0: newly programmed dc_fb_st_offset ( dc memory offset 010h[27:0]) has not been latched by display address generation hardware yet. 1: previously programmed dc_fb_st_off set (dc memory offset 010h[27:0]) has been latched by display address generation hardware. 26:16 v_line_cnt dc line count. this value is the current scan line of the dc engine. the dc engine, which fetches the frame buffer data, performs compression and de-compression, and overlays cursor data, typically runs several scan lines ahead of the actual display. this allows for buffering and scaling/filtering of graphics data. 15 vflip video flip. 0: newly programmed dc_vid_y_st_offset ( dc memory offset 020h[27:0]) has not been latched by display address generation hardware yet. 1: previously programmed dc_vid_y_st_off set (dc memory offs et 020h[27:0]) has been latched by display address generation hardware. 14 sigc signature complete. a 1 in this bit indicates that the crc signature operation has com- pleted and the resulting signature value may be safely read by software. 13 even_field even field indicator. when interlacing is enabled, a 1 in this bit indicates that the cur- rent field is the even field. 12:11 rsvd reserved. 10:0 dot_line_ cnt dot line count. this value is the current scan line of the display. this field is not syn- chronized in hardware, so software should read this value twice to ensure that the result is correct.
amd geode? lx processors data book 335 display controller register descriptions 33234h 6.6.7 palette access fifo diagnostic registers the palette access registers are used for accessing the internal palette ram and extensions. in addition to the standard 256 entries for color translation, the palette has extensions for cursor colors and overscan (border) color. the diagnostics registers enable testability of the display fifo and compression fifo. 6.6.7.1 dc palette address (dc_pal_address) this register should be written with the address (index) locati on to be used for the next access to the (dc_pal_data regis- ter dc memory offset 074h). dc memory offset 070h ty p e r / w reset value xxxxxxxxh dc_pal_address register map 313029282726252423222120191817161514131211109876543210 rsvd pal_addr dc_pal_address bit descriptions bit name description 31:9 rsvd reserved. 8:0 pal_addr pal address. this 9-bit field specifies the address to be used for the next access to the dc_pal_data register (dc memory offset 074h) . each access to the data register auto- matically increments the palette address register. if non-sequential access is made to the palette, the address register must be loaded between each non-sequential data block. the address ranges are as follows: address color 0h - ffh standard palette colors 100h cursor color 0 101h cursor color 1 102h rsvd 103h rsvd 104h overscan color 105h - 1ffh not valid note that in general, 24-bit values are loaded for all color extensions. however, if a 16-bpp mode is active, only the appropriate most significant bits are used (5:5:5 or 5:6:5).
336 amd geode? lx processors data book display controller register descriptions 33234h 6.6.7.2 dc palette data (dc_pal_data) this register contains the dat a for a palette access cycle. when a read or write to the palette ram occurs, the previous out- put value is held for one additional dot clock period. this effect should go unnoticed and will provide for sparkle-free updates. prior to a read or write to this register, th e dc_pal_address register (dc memory offset 070h) should be loaded with the appropriate address. the address automatically increments after each access to this register, so for sequential access, the address register need only be loaded once. if the sgre bit in dc_general_cfg is set (dc memory offset 004h[25] = 1), this register reads back the state of the graphics output pixel stream signature. 6.6.7.3 dc display fifo di agnostic (dc_dfifo_diag) this register is provided to enable te stability of the display fifo ram. before it is accessed, th e diag bit in the dc_general_cfg register should be set high (dc memory offset 004h[28] = 1) and the dfle bit should be set low (dc memory offset 004h[0] = 0). in addition, the tgen bit shoul d be set low (dc memory offset 008h[0] = 0) and all clock gat- ing should be disabled (msr 80002004h = 0). since each fifo ent ry is 64 bits, an even number of write operations should be performed. each pair of write operations causes the fifo wr ite pointer to increment automatically. after all write opera- tions are performed, a pair of reads of don't care data should be performed to load 64 bits of data into the output latch. each subsequent read contains the appropriate data that was previo usly written. each pair of read operations causes the fifo read pointer to increment automatically. this register is also used for writing to the compressed line buff er. each pair of writes to this register stores a 64-bit data value that is used for the next write to the compressed line buffer. the write pulse to the compressed line buffer is gener- ated by writing dummy data to the dc_pal_data register (dc memory offset 074h[23:0]) while in diag mode. dc memory offset 074h ty p e r / w reset value xxxxxxxxh dc_pal_data register map 313029282726252423222120191817161514131211109876543210 r s v d pa l _ data dc_pal_data bit descriptions bit name description 31:24 rsvd reserved. 23:0 pal_data pal da ta . this 24-bit field contains the read or write data for a palette access. if dc_general_cfg[sgre] (dc memory offset 004h [25]) is set, a read to this register will read back the state of the graphi cs output pixel stream signature. dc memory offset 078h ty p e r / w reset value xxxxxxxxh dc_dfifo_diag register map 313029282726252423222120191817161514131211109876543210 dfifo_data dc_dfifo_diag bit descriptions bit name description 31:0 dfifo_data display fifo diagnostic read or write data.
amd geode? lx processors data book 337 display controller register descriptions 33234h 6.6.7.4 dc compression fifo diagnostic (dc_cfifo_diag) this register is provided to enable testability of the compress ed line buffer (fifo) ram. before it is accessed, the diag bit should be set high (dc memory offset 004h[28] = 1) and the dfle bit should be set low (dc memory offset 004h[0] = 0). also, the cfrw bit in dc_general_cfg (dc memory offset 004h[29]) should be set appropriately depending on whether a series of reads or writes is to be performed. afte r each write, the fifo write pointer automatic ally increments. after all write operations are performed, the cfrw bit should be set high to enable read addresses to the fifo and a pair of reads of don't care data should be performed to load 64 bits of data into the output latc h. each subsequent read contains the appropriate data that was previously written. after each pa ir of reads, the fifo read pointer automatically increments. dc memory offset 07ch ty p e r / w reset value xxxxxxxxh dc_cfifo_diag register map 313029282726252423222120191817161514131211109876543210 cfifo_data dc_cfifo_diag bit descriptions bit name description 31:0 cfifo_data compressed data fifo diagno stic read or write data.
338 amd geode? lx processors data book display controller register descriptions 33234h 6.6.8 video downscaling 6.6.8.1 dc video downscaling delta (dc_vid_ds_delta) this register is provided to allow downscaling of the vid eo overlay image by selective skipping of source lines. a dda engine is used to identify lines to be skipped according to the following algorithm: at vertical retrace: phase = 0; // clear phase initially skip_flag = 0; // never skip the first line linenum = 0; // point to first line for each line of video: send_video_line(linenum); // send line to df linenum++ // increment to next line {skip_flag, phase} = phase + delta; // skip_flag is carry from add if (skip_flag) linenum = linenum + 1 // skip an additional line if flag was set else linenum = linenum // otherwise, just skip n lines the value to program into dc_vid_ds_delta is calculated as follows: parms: dword original_lines = full size image line count dword scaled_lines = line count of scaled image equation: dword dc_vid_ds_delta = ((original_li nes << 14) / scaled_lines) << 18; note: the scaling algorithm is only intended to work for ratios from 1 down to 1/2. the equation above clips the value to the 14 bits of accuracy in the hardware. the equation could be modified to allow for higher bits in the future by changing the 14-bit and 18-bit shift values. the only r equirement is that the sum of the shift values be 32. dc memory offset 080h ty p e r / w reset value 00000000h dc_vid_ds_delta register map 313029282726252423222120191817161514131211109876543210 delta rsvd vsync_shift_en rsvd vsync_shift dc_vid_ds_delta bit descriptions bit name description 31:18 delta delta. a 0.14 fixed-point fraction used as the del ta value for the dda engine that calcu- lates which video lines to skip for video downscaling. this register is enabled when the vdse bit in dc_general_cfg is set (dc memory offset 004h[19] = 1). 17:16 rsvd reserved. 15 vsync_shift_ en vsync shift enable. when this bit is set, the vsync output is delayed during even fields in interlaced modes. the amount of de lay is defined in vsync _shift (bits [11:0]). 14:12 rsvd reserved. 11:0 vsync_shift vsync shift. when vsync_shift_en is set (bit 15 = 1), this field determines the number of dot clocks of delay that is inserted on vsync during even fields in interlaced modes.
amd geode? lx processors data book 339 display controller register descriptions 33234h 6.6.9 gliu control registers 6.6.9.1 dc gliu0 memory of fset (dc_gliu0_mem_offset) this register is used to set a base address for the graphics memo ry region. the value in this register is added to all outgo- ing memory addresses. because the base address must be aligned to a 16 mb region, only bits [31:24] of this register are used. 6.6.9.2 dc dirty/valid ra m control (dc_dv_ctl) dc memory offset 084h ty p e r / w reset value 00000000h dc_gliu0_mem_offset register map 313029282726252423222120191817161514131211109876543210 gliu0_mem_offset rsvd dv_ram_ad dc_gliu0_mem_offset bit descriptions bit name description 31:20 gliu0_ mem_offset gliu0 memory offset. base address (1 mb aligned) for the graphics memory region. this value is added to all outgoing memory addresses. 19:11 rsvd reserved. equal to 0. 10:0 dv_ram_ad dv ram address. this value is used to allow direct software access to the dirty/valid (dv) ram. the address must be written in this location before reading or writing the dv ram access register (dc memory offset 08ch). dc memory offset 088h ty p e r / w reset value 00000000h dc_dv_ctl register map 313029282726252423222120191817161514131211109876543210 dv address offset dv_line_size dv_range rsvd dv_mask clear_dv_ram dv_ctl bit descriptions bit name description 31:12 dv address offset dv address offset. when the dv ram observes memory transactions, the addresses correspond to memory controller device address space. however, the dv ram is organized based on the internal dc device address space. to account for this, the value indicated by this field is shifte d to correspond to address bits [31:12], and then subtracted from memory addresses before determining an offset into the dv ram. when programming the value in this fiel d, software must calculate the sum of the gliu0_mem_offset (dc memory offset 084h [31:24] and the appropriate physical- to-device descriptor(s) in gliu0.
340 amd geode? lx processors data book display controller register descriptions 33234h 6.6.9.3 dc dirty/valid ram access (dc_dv_access) 11:10 dv_line_size dv line size. this field determines how many bytes of frame buffer space correspond to an entry in the dv ram. the value select ed by this field must be greater than or equal to the fb_line_size, as programme d in the dc_line_size register (dc mem- ory offset 030h[9:0]). 00: 1024 (256 qwords) 01: 2048 (512 qwords) 10: 4096 (1024 qwords) 11: 8192 (2048 qwords) 9:8 dv_range dv range. the value selected by this field is an upper bound of the number of entries used in the dv ram. by setting this val ue to a number less than the maximum (2048), there is a potential savings in power, sinc e the dv ram will not be accessed for lines that may be just above the frame buffer space. 00: 2048 lines 01: 512 lines 10: 1024 lines 11: 1536 lines 7:2 rsvd reserved. set to 0. 1 dv_mask dv mask. while this bit is set, the dv ram controller does not monitor writes to mem- ory; no dirty bits will be set in response to memory activity. when this bit is cleared, the dv ram behaves normally. 0 clear_dv_ram clear dv ram. writing a 1 to this bit causes the contents of the dv ram to be cleared (i.e., every entry is set to dirty and invalid). this process requires approximately 2050 gliu0 clocks. this bit may be read to determine if this clear operation is underway (1) or completed (0). writing a 0 to this bit has no effect. dc memory offset 08ch ty p e r / w reset value 0000000xh dv_ctl bit descriptions (continued) bit name description dc_dv_access register map 313029282726252423222120191817161514131211109876543210 rsvd dv_valid dv_dirty dc_dv_access bit descriptions bit name description 31:2 rsvd reserved. set to 0. 1dv_valid dv valid. writes to this register place the value of this bit into the ?valid? entry of the dv ram. reads return the value of the ?valid? entry. the dv ram address is determined by the value in dv_ram_ad (dc memory offset 084h[10:0]). 0dv_dirty dv dirty. writes to this register will place the value of this bit into the ?dirty? entry of the dirty/valid ram. reads will return the value of the ?dirty? entry. the dv ram address is determined by the value in dv_ram_a d (dc memory offset 084h[10:0]).
amd geode? lx processors data book 341 display controller register descriptions 33234h 6.6.10 graphics scaling control registers 6.6.10.1 dc graphics filter scale (dc_gfx_scale) dc memory offset 090h ty p e r / w reset value 40004000h dc_gfx_scale register map 313029282726252423222120191817161514131211109876543210 v_scale h_scale dc_gfx_scale bit descriptions bit name description 31:16 v_scale vertical filter scale. the value in this field, represents the number of vertical lines of source data that are co nsumed for every line of filtered dat a produced by the scaler filter. this field is treated as a rational number , with the decimal point between bits 30 and 29. to determine the value to be programmed into this field, use the following formula: v_scale = (v_source / (v_dest-1)) << 14 where v_source is the height (in scan lines ) of the frame buffer and v_dest is the height (in scan lines) of the destination field. the default value of this field (4000h) repr esents 1:1 scaling. this value must be pro- grammed when the vertical filter is disabled. the value in this field must not exceed 8000h , which represents a 2:1 downscale ratio. if the width of the source image is more than 1024 pixels, scaling is not supported. 15:0 h_scale horizontal filter scale. the value in this field, represents the number of (horizontal) pix- els of source data that are consumed for ever y pixel of data produced by the scaler filter. this field is treated as a rational number , with the decimal point between bits 14 and 13. to determine the value to be programmed into this field, use the following formula: h_scale = (h_source/(h_dest-1)) << 14 where h_source is the width (in pixels) of the frame buffer and h_dest is the width (in pixels) of the destination image. the default value of this field (4000h) repr esents 1:1 scaling. this value must be pro- grammed when the horizontal filter is disabled. the value in this field must never exceed 800 0h, which represents a 2:1 horizontal down- scale. if the width of the source image is gr eater than 1024 pixels, scaling is not sup- ported.
342 amd geode? lx processors data book display controller register descriptions 33234h 6.6.10.2 dc irq/filter co ntrol (dc_irq_filt_ctl) dc memory offset 094h ty p e r / w reset value 00000000h dc_irq_filt_ctl register map 313029282726252423222120191817161514131211109876543210 rsvd linebuf_sel interlace_addressing rsvd line_count rsvd alpha_filt_ena rsvd filt_ena intl_en h_filt_sel rsvd filt_addr dc_irq_filt_ctl bit descriptions bit name description 31 rsvd reserved. 30:29 linebuf_sel line buffer select. when linebuf_reg_en[0] is set (bit 9 = 1), the coefficient ram address bits (filt_addr, bits [7:0) and the f ilter coefficient data registers (dc memory offset 098h and 09ch) can be used to read and write the line buffer or flicker filter rams. this field selects which of the three line buffer rams (or two flicker filter rams) is to be accessed. 28 interlace_ addressing interlace addressing. this bit indicates whether each field should be vertically deci- mated when interlacing. if this bit is set, each field of the interlaced frame will include every other line of the original (unscaled) fram e buffer image. the flicker filter and scaler filter should both be disabled if this bit is set. 27 rsvd reserved. 26:16 line_count interrupt line count. this value determines which scan line will trigger a line count interrupt. when the dc?s display engine reaches the line number determined by this value, it will assert an interr upt if irq_mask is cleared (dc memory offset 0c8h[0] = 0). 15 rsvd reserved. 14 alpha_filt_ ena alpha filter enable. settings written to this field will not take effect until the start of the following frame or interlaced field. setting this bit to 1 enables the scaler filter for the alpha channel. this filter is provided to support scaling and interlacing of graphics data. if the graphics filter is disabled or this bit is cleared, the alpha channel is not filter ed; a nearest-neighbor mechanism is used instead. this can provide cleaner transitions between regions with significantly different alpha values. 13 rsvd reserved. 12 filt_ena graphics filter enable. settings written to this field will not take effect until the start of the following frame or interlaced field. setting this bit to 1 enables the graphics scaler filter; this filter is provided to support scaling and interlacing of graphics data.
amd geode? lx processors data book 343 display controller register descriptions 33234h 6.6.10.3 dc filter coefficient da ta register 1 (dc_filt_coeff1) any read or write of this register causes a read or write of the horizontal or filter coefficient ram. if this occurs while the dis- play is active, improper filtering of an output pixel can occur, which may cause temporary visual artifacts (speckling). to avoid this, either disable the display or avoid accessing this register unless during vertical blank. 11 intl_en interlace enable. settings written to this field will not take effect until the start of the fol- lowing frame or interlaced field. setting this bit to 1 configures the output to interlaced mode. in this mode, the vertical timings are based on the even timing registers fo r every other field. this bit must be set if the flicker filter or address interlacing is enabled. when using the vga and interlacing, the scaler must also be used (i.e., bit 12 of this reg- ister must be set). 10 h_filt_sel horizontal filter select. setting this bit to 1 allows access to the horizontal filter coeffi- cients via this register and the filter data registers (dc memory offset 098h and 09ch). when this bit is cleared, the vertical filter coefficients are accessed instead. 9:8 rsvd reserved. 7:0 filt_addr filter coefficient address. this indicates which filter location is accessed through reads and writes of the dc filt er coefficient data register 1 (dc memory offset 098h). dc memory offset 098h ty p e r / w reset value xxxxxxxxh dc_irq_filt_ctl bit descriptions (continued) bit name description dc_filt_coeff1 register map 313029282726252423222120191817161514131211109876543210 rsvd tap3 tap2 tap1 dc_ filt_coeff1 bit descriptions bit name description 31:30 rsvd reserved. set to 0. 29:20 tap3 tap 3 coefficient. this coefficient is used for the thir d tap in the filter (the lower tap of the vertical filter or the center tap of the horizontal filter). each of the four components of the pixel color (red, green, blue, and alpha, if available) is expanded to 8 bits and then multiplied by this value before being summed wit h the weighted results of the other filter taps. 19:10 tap2 tap 2 coefficient. this coefficient is used for the second tap in the filter (the center tap of the vertical filter or the second tap from the left in the horizontal filter). 9:0 tap1 tap 1 coefficient. this coefficient is used for the first tap in the filter (t he upper tap of the vertical filter or the leftmost tap of the horizontal filter).
344 amd geode? lx processors data book display controller register descriptions 33234h 6.6.10.4 dc filter coefficient da ta register 2 (dc_filt_coeff2) any read or write of this register causes a read or write of the horizontal or filter coefficient ram. if this occurs while the dis- play is active, improper filtering of an output pixel can occur, which may cause temporary visual artifacts (speckling). to avoid this, either disable the display or avoid accessing this register unless during vertical blank. 6.6.11 vbi control registers 6.6.11.1 dc vbi even control (dc_vbi_even_ctl) settings written to this register do not take effect until the start of the following frame or interlaced field. dc memory offset 09ch ty p e r / w reset value xxxxxxxxh dc_filt_coeff2 register map 313029282726252423222120191817161514131211109876543210 rsvd tap5 tap4 dc_filt_coeff2 bit descriptions bit name description 31:20 rsvd reserved. set to 0. this field is used only when reading or writing the line buffer regis- ter. 19:10 tap5 tap 5 coefficient. this coefficient is used for the fifth tap (rightmost) in the horizontal fil- ter. 9:0 tap4 tap 4 coefficient. this coefficient is used for the fourth tap (second from the right) in the horizontal filter. dc memory offset 0a0h ty p e r / w reset value xxxxxxxxh dc_vbi_even_ctl register map 313029282726252423222120191817161514131211109876543210 vbi_sig_en vbi_16 vbi_up vbi_ena vbi_even_offset 0 dc_vbi_even_ctl bit descriptions bit name description 31 vbi_sig_en vbi signature enable. this bit allows the crc engine at the output of the dc to be used to check vbi data instead of graphics dat a. when this bit is set, the crc is gener- ated based only on vbi data; when cleared, only graphics data is used for the crc cal- culation. 30 vbi_16 vbi 16-bit enable. when set, vbi data is sent 16 bits per dot clock. when clear, vbi data is sent 8 bits per dot clock. 29 vbi_up vbi upscale. when set, the vbi data is upscaled by 2. this is accomplished by repeat- ing data twice.
amd geode? lx processors data book 345 display controller register descriptions 33234h 6.6.11.2 dc vbi odd cont rol (dc_vbi_odd_ctl) settings written to this register do not take effect until the start of the following frame or interlaced field. 6.6.11.3 dc vbi horizontal control (dc_vbi_hor) settings written to this register do not take effect until the start of the following frame or interlaced field. 28 vbi_ena vbi enable. setting this bit to 1 enables vbi (vertical blank interrupt) data. this is a data stream that is placed in the off-screen region at the start of each fiel d. this data is passed through the graphics output path, but is not filtered or modified in any way. 27:0 vbi_even_ offset vbi even address offset. indicates the starting offset fo r vbi data for even fields. this address must be qword aligned; the low three bits are always 0. if interlacing is dis- abled, this offset is used for vbi data. dc memory offset 0a4h ty p e r / w reset value xxxxxxxxh dc_vbi_even_ctl bit d escriptions (continued) bit name description dc_vbi_odd_ctl register map 313029282726252423222120191817161514131211109876543210 rsvd vbi_odd_offset 0 dc_vbi_odd_ctl bit descriptions bit name description 31:28 rsvd reserved. set to 0. 27:0 vbi_odd_ offset vbi odd address offset. indicates the starting offset for vbi data for odd fields. this address must be qword aligned; the low three bits are always 0. if interlacing is dis- abled, the even offset is used for vbi data. dc memory offset 0a8h ty p e r / w reset value xxxxxxxxh dc_vbi_hor register map 313029282726252423222120191817161514131211109876543210 rsvd vbi_h_end rsvd vbi_h_start dc_vbi_hor bit descriptions bit name description 31:28 rsvd reserved. set to 0. 27:16 vbi_h_end vbi horizontal end. specifies the horizontal end position for vbi data minus 1 pixel. 15:12 rsvd reserved. set to 0. 11:0 vbi_h_start vbi horizontal start. specifies the horizontal start po sition for vbi data minus 1 pixel.
346 amd geode? lx processors data book display controller register descriptions 33234h 6.6.11.4 dc vbi odd line enable (dc_vbi_ln_odd) settings written to this register do not take effect until the start of the following frame or interlaced field. 6.6.11.5 dc vbi even line enable (dc_vbi_ln_even) settings written to this register do not take effect until the start of the following frame or interlaced field. dc memory offset 0ach ty p e r / w reset value xxxxxxxxh dc_vbi_ln_odd register map 313029282726252423222120191817161514131211109876543210 ln_offset_odd ln_en_odd rsvd dc_vbi_ln_odd bit descriptions bit name description 31:25 ln_offset_ odd odd line offset. specifies the offset (in lines) of th e start of vbi data from the initial edge of vsync. this field is not used if interlacing is disabled . this field must be set to a value of 126 or less. 24:2 ln_en_odd odd line enable. each of the bits in this field corre sponds to a line (24-2) of vbi data. setting a bit in this field to 1 enables the corresponding line of vbi data in the odd field. this field is not used if interlacing is disabled. 1:0 rsvd reserved. set to 0. dc memory offset 0b0h ty p e r / w reset value xxxxxxxxh dc_vbi_ln_even register map 313029282726252423222120191817161514131211109876543210 ln_offset_even ln_en_even rsvd dc_vbi_ln_even bit descriptions bit name description 31:25 ln_offset_ even even line offset. specifies the offset (in lines) of th e start of vbi data from the initial edge of vsync. this field is used for all frames if interlacing is disabl ed. this field must be set to a value of 126 or less. 24:2 ln_en_even even line enable. each of the bits in this field corresponds to a line (24-2) of vbi data. setting a bit in this field to 1 enables the corresponding line of vbi data in the even field. this field is used for all frames if interlacing is disabled. 1:0 rsvd reserved. set to 0.
amd geode? lx processors data book 347 display controller register descriptions 33234h 6.6.11.6 dc vbi pitch and size (dc_vbi_pitch) 6.6.12 color key control registers 6.6.12.1 dc color key (dc_clr_key) dc memory offset 0b4h ty p e r / w reset value xxxxxxxxh dc_vbi_pitch register map 313029282726252423222120191817161514131211109876543210 rsvd vbi_size vbi_pitch dc_vbi_pitch bit descriptions bit name description 31:26 rsvd reserved. set to 0. 25:16 vbi_size vbi data size. indicates how many qwords of data to fetch from memory for each line of vbi 15:0 vbi_pitch vbi data pitch. indicates how many qwords of memory space to increment when moving from the start of one active vbi line to the start of the next. dc memory offset 0b8h ty p e r / w reset value 00000000h dc_ clr_key register map 313029282726252423222120191817161514131211109876543210 rsvd clr_key_en clr_key dc_clr_key bit descriptions bit name description 31:25 rsvd reserved. set to 0. 24 clr_key_en color key enable. this bit enables color key detection in the dc. when this bit is set, the dc adjusts the alpha value of pixels wh ose 24-bit rgb values match the value in clr_key (bits [23:0]). a mask is also pr ovided in clr_key_mask (dc memory offset 0bch[23:0]) to indicate which bits can be ig nored when performing this match. color key detection is performed after the data ha s been decompressed and the cursor has been overlayed, but before scaling and filtering take place. 23:0 clr_key color key. this field represents the rgb value th at will be compared to dc pixels when performing color key detection.
348 amd geode? lx processors data book display controller register descriptions 33234h 6.6.12.2 dc color key mask (dc_clr_key_mask) 6.6.12.3 dc color key horizont al position (dc_clr_key_x) settings written to this register do not take effect until the start of the following frame or interlaced field. 6.6.12.4 dc color key vertical position (dc_clr_key_y) settings written to this register do not take effect until the start of the following frame or interlaced field. dc memory offset 0bch ty p e r / w reset value 00xxxxxxh dc_clr_key_mask register map 313029282726252423222120191817161514131211109876543210 rsvd clr_key_mask dc_clr_key_mask bit descriptions bit name description 31:24 rsvd reserved. set to 0. 23:0 clr_key_ mask color key mask. this field is anded with both the pixel and the color key value (in dc_clr_key, dc memory offset 0b8h[23:0]) before comparing the values. this allows the value of some bits to be ignored when performing the match. dc memory offset 0c0h ty p e r / w reset value 00000000h dc_clr_key_x register map 313029282726252423222120191817161514131211109876543210 rsvd clr_key_x_end rsvd clr_key_x_start dc_clr_key_x bit descriptions bit name description 31:27 rsvd reserved. set to 0. 26:16 clr_key_x_ end color key hori zontal end. this field indicates the horizontal end position of the color key region minus 1.this represents the firs t pixel past the end of the color key region. this field is 0-based; the upper left pixe l of the screen is represented by (0,0). 15:11 rsvd reserved. set to 0. 10:0 clr_key_x_ start color key horizontal start. this field represents the horiz ontal start position of the color key region minus 1. this represents th e first pixel within the color key region. dc memory offset 0c4h ty p e r / w reset value 00000000h dc_clr_key_y register map 313029282726252423222120191817161514131211109876543210 rsvd clr_key_y_end rsvd clr_key_y_start
amd geode? lx processors data book 349 display controller register descriptions 33234h 6.6.12.5 dc interrupt (dc_irq) dc_clr_key_y bit descriptions bit name description 31:27 rsvd reserved. set to 0. 26:16 clr_key_y_ end color key vertical end. this field represents the vertical end position of the color key region minus 1. this represents the first line past the end of the color key region. 15:11 rsvd reserved. set to 0. 10:0 clr_key_y_ start color key vertical start. this field represents the vertical start position of the color key region minus 1. this represents the first line within the color key region. dc memory offset 0c8h ty p e r / w reset value 00000003h dc_irq register map 313029282726252423222120191817161514131211109876543210 rsvd vip_vsync_loss_irq irq rsvd vip_vsync_loss_irq_mask irq_mask dc_irq bit descriptions bit name description 31:18 rsvd reserved. set to 0. 17 vip_vsync_ loss_irq vip vsync loss irq. if set to 1, this field indicates that while genlock was enabled, genlock timeout was enabled, and the dc reached the end of a frame and detected vip_video_ok (dc memory offset d4h[23]) inac tive. as a result of this condition, the dc began display of a field/frame based on its own timings. 16 irq irq status. if set to 1, this field indicates that the vertical counter has reached the value set in the irq/filter control register. the state of the irq_mask, bit 0, will not prevent this bit from being set. to clear th e interrupt, write a 1 to this bit. 15:2 rsvd reserved. set to 0. 1 vip_vsync_ loss_irq_ mask vip vsync loss irq mask. masks generation of an interrupt in the event that the dc reaches the end of a frame with genlock enabled and genlock timeout enabled and determines that the vip_vide o_ok (dc memory offset d4h[23]) input is inactive. 0 irq_mask irq mask. setting this bit to 1 prevents the display controller from generating an inter- rupt signal when the vertical counter reaches the value programmed in dc_irq_filt_ctl (dc memory offset 094h). clearing this bit disables interrupt gener- ation, but will not prevent irq, bit 16, from being set.
350 amd geode? lx processors data book display controller register descriptions 33234h 6.6.13 interrupt and genlock registers 6.6.13.1 dc genlock co ntrol (dc_genlk_ctl) settings written to this register do not take effect until the start of the frame or interlaced field after the timing register update bit (dc memory offset 008h[6]) is set. dc memory offset 0d4h ty p e r / w reset value xxxxxxxxh dc_genlk_ctl register map 313029282726252423222120191817161514131211109876543210 flick_sel rsvd alpha_flick_en flick_en vip_video_ok genlock_active skew_wait vip_vsync_wait genlk_to_en genlk_en genlk_skw dc_genlk_ctl bit descriptions bit name description 31:28 flick_sel flicker filter select. when the flicker filter is enabled (flick_en, bit 24 = 1), this field selects the weighting of the three taps in this vertical filter: 0000: 0, 1, 0 (top, middle, bottom) 0001: 1/16, 7/8, 1/16 0010: 1/8, 3/4, 1/8 0100: 1/4, 1/2, 1/4 0101: 5/16, 3/8, 5/16 all other combinations in this field are reserved. 27:26 rsvd reserved. set to 0. 25 alpha_flick_ en alpha flicker filter enable. if set, this bit enables flicker filtering of the alpha value when the flicker filter is enabled (flick_en, bit 24 = 1). if the flicker filter is enabled and this bit is cleared, the alpha value of the c enter pixel is passed through the flicker filter unchanged. 24 flick_en flicker filter enable. enables the 3-tap vertical flicker filter (primarily used for interlaced modes). when set, the graphics output is filter ed vertically using the coefficients as indi- cated in bits [22:21]. when clear, no flicker filtering is performed. 23 vip_video_ok (ro) vip video ok (read only). this bit indicates the state of the internal vip video_ok input. this signal is driven by the vip to i ndicate that the vip is detecting a valid input stream. 22 genlock_ active (ro) genlock active (read only). this bit indicates that the current (or most recent) field/ frame was initiated as the result of an active vip vsync. the state of this bit will change coincident with the activation of the vsy nc output. if the vsync output occurs as the result of a timeout condition, this bit w ill be cleared. if genlock is not enabled (genlk_en, bit 18 = 0), this bit will be cleared. 21 skew_wait (ro) skew wait (read only). this status bit indicates that the dc has received a vsync from the vip and that the skew counter is running. this bit is set when the vip_vsync input is set and cleared when the skew counter expires.
amd geode? lx processors data book 351 display controller register descriptions 33234h 6.6.14 even field video address registers 6.6.14.1 dc even field video y start ad dress offset (dc_vid_even_y_st_offset) settings written to this register do not take effe ct until the start of the next even interlaced field. 20 vip_vsync_ wait (ro) vip vsync wait (read only). if set to 1 this status bit indicates that the dc has com- pleted a field or frame and is waiting for the vip?s vsync to go active before beginning another frame. typically, this will occur only if the vip_video_ok (bit 23) input is active or the genlock_to _en (bit 19) is inactive. 19 genlk_to_en genlock time out enable. setting this bit allows the dc to revert to its own internal timer if a loss of sync is detected by the vip. this allows for seamless operation of the dc in genlock mode when the vip input becomes unstable. clearing this bit forces the dc to wait for a vsync signal from the vip even if the vip indicates a loss of sync. 18 genlk_en genlock enable. when set to 1, the dc resets to the start of the frame/field upon receipt of a rising edge on the vip_vsync signal. 17:0 genlk_skw genlock skew. this value indicates how many dot clocks to delay the internal recogni- tion of the vip vsync by the dc when genlock is enabled. if genlock timeout is also enabled (genlk_to_en, bit 19 = 1), internal recognition of vsync occurs immediately upon timeout (without allowing this skew time to elapse after the timeout is detected.) this allows seamless transition from a vip- supplied vsync to an internally-determined vsync, while still allowing for a delay in time out detection. dc memory offset 0d8h ty p e r / w reset value xxxxxxxxh dc_genlk_ctl bit descriptions (continued) bit name description dc_vid_even_y_st_offset register map 313029282726252423222120191817161514131211109876543210 rsvd offset dc_vid_even_y_st_offset bit descriptions bit name description 31:28 rsvd reserved. set to 0. 27:0 offset video y even buffer start offset. this value represents the starting location for video y buffer for even fields when interlacing is enabled. this field is not used when interlac- ing is disabled (dc memory offset 094h[11] = 0). this value represents the starting location for video y buffer for even fields when inter- lacing is enabled (dc memory offset 094h[11] = 1). the lower five bits should always be programmed as zero so that the start offset is aligned to a 32-byte boundary. if yuv 4:2:2 mode is selected (dc memory offset 00 4h[20] = 0), the video y buffer is used as a singular buffer holding interleaved y, u and v data. if yuv 4:2:0 is selected (dc memory offset 004h[20] = 1), the video y buffer is used to hold only y data while u and v data are stored in separate buffers.
352 amd geode? lx processors data book display controller register descriptions 33234h 6.6.14.2 dc even field vide o u start address offset (dc_vid_even_u _st_offset) settings written to this register do not take effe ct until the start of the next even interlaced field. 6.6.14.3 dc even field video v start ad dress offset (dc_vid_even_v_st_offset) settings written to this register do not take effe ct until the start of the next even interlaced field. dc memory offset 0dch ty p e r / w reset value xxxxxxxxh dc_vid_even_u_st_offset register map 313029282726252423222120191817161514131211109876543210 rsvd offset dc_vid_even_u_st_offset bit descriptions bit name description 31:28 rsvd reserved. set to 0. 27:0 offset video u even buffe r start offset. this value represents the starting location for video u buffer for even fields when interlacing is enabled (dc memory offset 094h[11] = 1) and yuv 4:2:0 mode is selected (dc memory offset 004h[20] = 1). the lower five bits should always be programmed as zero so that the start offset is aligned to a 32-byte boundary. dc memory offset 0e0h ty p e r / w reset value xxxxxxxxh dc_vid_even_v_st_offset register map 313029282726252423222120191817161514131211109876543210 rsvd offset dc_vid_even_v_st_offset bit descriptions bit name description 31:28 rsvd reserved. set to 0. 27:0 offset video v even buffer start offset. this value represents the starting location for video v buffer for even fields when interlacing is enabled (dc memory offset 094h[11] = 1) and yuv 4:2:0 is selected (dc memory offset 004h[20] = 1). the lower five bits should always be programmed as zero so that the start offset is aligned to a 32-byte boundary.
amd geode? lx processors data book 353 display controller register descriptions 33234h 6.6.15 even field vertical timing registers 6.6.15.1 dc vertical and to tal timing for even fiel ds (dc_v_active_even_timing) this register contains vertical active and total timing inform ation. these parameters pertain only to even fields in inter- laced display modes (the dc_v_active_timing register (dc memory offset 050h) will take effect for odd fields in inter- laced display modes.) settings written to this register will not ta ke effect until the start of t he frame or interlaced field a fter the timing register update bit is se t (dc memory offset 008h[6] = 1). dc memory offset 0e4h ty p e r / w reset value xxxxxxxxh dc_v_active_even_tim ing register map 313029282726252423222120191817161514131211109876543210 rsvd v_total rsvd v_active dc_v_active_even_timin g bit descriptions bit name description 31:27 rsvd reserved. these bits should be programmed to zero. 26:16 v_total vertical total . this field represents the total number of lines for a given frame scan minus 1. note that the value is necessarily greater than the v_active field (bits 10:0]) because it includes border lines and blanked lines. 15:11 rsvd reserved. these bits should be programmed to zero. 10:0 v_active vertical active. this field represents the total number of lines for the displayed portion of a frame scan minus 1. note that for flat panels, if this value is less than the panel active vertical resolution (v_panel), the par ameters v_blank_start, v_blank_end, v_sync_start, and v_sync_end should be reduced by the following value (v_adjust) to achieve vertical centering: v_adjust = (v_panel - v_active) / 2 if graphics scaling is enabled (and interleaved display is enabled), this value represents the height of the final (scaled) field to be di splayed. the height of the frame buffer image may be different in this case; fb_active ( dc memory offset 5ch) is used to program the horizontal and vertical active values in the frame buffer when graphics scaling is enabled.
354 amd geode? lx processors data book display controller register descriptions 33234h 6.6.15.2 dc crt vertical blank timing for even fields (dc_v_blank_even_timing) this register contains vertical blank timing information. all va lues are specified in lines. this register is used only for eve n fields in interlaced display modes. settings written to this register do not take effect until the start of the frame or interl aced field after the timing register update bit is set (dc memory offset 008h[6] = 1). 6.6.15.3 dc crt vertical sync timing fo r even fields (dc_ v_sync_even_timing) this register contains crt vertical sync ti ming information. all values are specified in lines. this register is used only for even fields in interlaced modes. settings written to this regist er do not take effect until the start of the frame or interlace d field after the timing register update bit is set (dc memory offset 008h[6] = 1). dc memory offset 0e8h ty p e r / w reset value xxxxxxxxh dc_v_blank_even_timing register map 313029282726252423222120191817161514131211109876543210 rsvd v_blank_end rsvd v_blank_start dc_v_blank_even_timing bit descriptions bit name description 31:27 rsvd reserved. these bits should be programmed to zero. 26:16 v_blank_end vertical blank end. this field represents the line at which the vertical blanking signal becomes inactive minus 1. if the display is interlaced, no border is supported, so this value should be identical to v_total (dc memory offset 0e4h[26:16]). 15:11 rsvd reserved. these bits should be programmed to zero. 10:0 v_blank_ start vertical blank start. this field represents the line at which the vertical blanking signal becomes active minus 1. if the display is interlaced, this value should be programmed to v_active (dc memory offset 0e4h[10:0]) plus 1. dc memory offset 0ech ty p e r / w reset value xxxxxxxxh dc_v_sync_even_timing register map 313029282726252423222120191817161514131211109876543210 rsvd v_sync_end rsvd v_sync_start dc_v_sync_even_timing bit descriptions bit name description 31:27 rsvd reserved. these bits should be programmed to zero. 26:16 v_sync_end vertical sync end. this field represents the line at which the crt vertical sync signal becomes inactive minus 1. 15:11 rsvd reserved. these bits should be programmed to zero. 10:0 v_sync_ start vertical sync start. this field represents the line at which the crt vertical sync signal becomes active minus 1. for interlaced displa y, note that the vertical counter is incre- mented twice during each line and since there are an odd number of lines, the vertical sync pulse will trigger in the middle of a line for one field and at the end of a line for the subsequent field.
amd geode? lx processors data book 355 display controller register descriptions 33234h 6.6.16 vga block configuration registers 6.6.16.1 vga configuration (vga_config) this register controls palette write operations. 6.6.16.2 vga status (vga_status) this register provides status information for the individual smi events e nabled in the vga_config register (dc memory offset 100h), as well as certain other status bits. reading this register clears all active events. dc memory offset 100h ty p e r / w reset value 00000000h vga_config register map 313029282726252423222120191817161514131211109876543210 rsvd wppal vga_config bit descriptions bit name description 31:1 rsvd reserved. set to 0. 0 wppal write protect palette. if set to 1, vga palette write operations are not written to the palette rams. palette writes behave norm ally, except that the data is discarded. dc memory offset 104h ty p e r o reset value 00000000h vga_status register map 313029282726252423222120191817161514131211109876543210 rsvd blink_cnt rsvd v_cnt rsvd vsync dispen crtcio_smi vblank_smi isr0_smi misc_smi vga_status bit descriptions bit name description 31:30 rsvd reserved. 29:24 blink_cnt blink counter value. unsynchronized, used as a simulation aid. 23:22 rsvd reserved. 21:12 v_cnt vertical counter value. unsynchronized, used as a simulation aid. 11:6 rsvd reserved. 5 vsync vsync. 1 if vsync is active (copy of bit 3 of isr1). 4dispen display enable. 0 if both horizontal and vertical display enable are active (copy of bit 0 of isr1). 3 crtcio_smi crtc register smi. if = 1, an smi was generated due to an i/o read or write to an non- implemented crtc register.
356 amd geode? lx processors data book display controller register descriptions 33234h 6.6.17 vga block standard registers 6.6.17.1 vga miscellaneous output 2 vblank_smi vblank smi. if = 1, an smi was generated due to leading edge vertical blank. 1 isr0_smi input status register 0 smi. if = 1, an smi was generated fr om an i/o in to input status register 0. 0misc_smi miscellaneous outp ut register smi. if = 1, an smi was generated from an i/o out to the miscellaneous output register. read address 3cch write address 3c2h ty p e r / w reset value 02h vga_status bit descriptions (continued) bit name description vga miscellaneous output register bit descriptions bit name description 7 vsync_pol vertical sync polarity. selects a positive-going vsync pulse (bit = 0) or a negative- going vsync pulse (bit = 1). 6 hsync_pol horizontal sync polarity. selects a positive-going hsync pulse (bit = 0) or a negative- going hsync pulse (bit = 1). 5page page bit. this bit is used to replace memory address bit a0 as the lsb when bit 1 of the miscellaneous register (index 06h[1]) in the vga graphics controller is set to 1. 4 rsvd reserved. 3:2 clk_sel clock select. selects the vga pixel clock source. writes to this register will directly affect the frequency generated by the dot cloc k plls. the value of this register is sam- pled when it is written; the dot clock freq uency can be overridden by subsequent writes to the dot clock pll controls. if the vga is disabled or in fixed timing mode, the dot clock frequency is not affected by writes to this register. 00: selects clock for 640/320 pixels per line (25.175 mhz dot clock). 01: selects clock for 720/360 pixels per line (28.325 mhz dot clock). 10: reserved. 11: reserved. 1ram_en ram enable. enables the video frame buffer address decode when set to 1. 0 id_addr_sel i/o address select. determines the i/o address of the crtc index and data registers (index 3?4h and 3?5h), feature control register (index 3?ah), and input status register 1 (index 3?ah) as follows: ? = b when bit set to 0 (mda i/o address emulation), ? = d when bit set to 1 (cga address emulation).
amd geode? lx processors data book 357 display controller register descriptions 33234h 6.6.17.2 vga input status register 0 6.6.17.3 vga input status register 1 6.6.17.4 vga feature control read address 3c2h write address -- ty p e r / w reset value 00h vga input status register 0 bit descriptions bit name description 7 rsvd not implemented. (crtc interrupt pending) 6:5 rsvd reserved. 4 rsvd not implemented. (display sense) 3:0 rsvd reserved. read address 3bah or 3dah write address -- ty p e r / w reset value 01h vga input status register 1 bit descriptions bit name description 7:4 rsvd reserved. 3 vsync vertical sync. when a 1, indicates that the vsync signal is active. 2:1 rsvd reserved. 0disp_en display enable. reads as a 0 when both horizontal and vertical display enable are active. reads as a 1 when either display enable signal is inactive. read address 3cah write address 3bah or 3dah ty p e r / w reset value xxh vga feature control register bit descriptions bit name description 7:0 rsvd reserved.
358 amd geode? lx processors data book display controller register descriptions 33234h 6.6.18 vga sequencer registers the sequencer registers are accessed by writing an index va lue to the sequencer index register (3c4h) and reading or writing the register using the sequencer data register (3c5h). 6.6.18.1 vga sequencer index 6.6.18.2 vga sequencer data 6.6.18.3 vga reset table 6-51. vga sequencer registers summary index type register reset value reference -- r/w vga sequencer index 0xh page 358 -- r/w vga sequencer data xxh page 358 00h r/w vga reset 00h page 358 01h r/w vga clocking mode 02h page 359 02h r/w vga map mask 00h page 359 03h r/w vga character map select xxh page 360 04h r/w vga memory mode 02h page 360 index address 3c4h ty p e r / w reset value 0xh vga sequencer index register bit descriptions bit name description 7:3 rsvd reserved. 2:0 index index . data address 3c5h ty p e r / w reset value xxh vga sequencer data register bit descriptions bit name description 7:0 data data. index 00h ty p e r / w reset value 00h vga reset register bit descriptions bit name description 7:2 rsvd reserved. 1:0 dis_en enable display. both these bits should be set to 1 (value = 11) to enable display of the vga screen image. if either of these bits ar e 0, the display is blanked. the vga contin- ues to respond to i/o and memory accesses.
amd geode? lx processors data book 359 display controller register descriptions 33234h 6.6.18.4 vga clocking mode 6.6.18.5 vga map mask these bits enable (bit = 1) writing to their corresponding by tes in each dword of the frame buffer (i.e., em3 enables byte 3, em2 enables byte 2, etc.). the four maps or planes correspond to the fo ur bytes in each dword of the frame buffer. reads to all maps are always enabled, and are unaffected by these bits. index 01h ty p e r / w reset value 02h vga clocking mode register bit descriptions bit name description 7:6 rsvd reserved. 5 screen_off screen off. setting this bit to a 1 blanks the screen while maintaining the hsync and vsync signals. this is intended to allow the cpu full access to the memory bandwidth. this bit must be 0 for the display image to be visible. 4 rsvd not supported. (shift4) 3 dclk_div2 dot clock divide by 2. when set to 1, the incoming pixel clock is divided by two to form the actual dot clock. when 0, the incoming pixel clock is used unchanged. 2 rsvd not supported. (shift load) 1 rsvd reserved. always 1. 0 char_width 8-dot character width. when set to a 1, the character cells in text mode are eight pixels wide. when set to 0, the character cells are nine pixels wide. the 9th pixel is equal to the 8th pixel for character codes c0h-dfh (the line graphics character codes), and is 0 (background) for all other codes. index 02h ty p e r / w reset value 00h vga map mask register bit descriptions bit name description 7:4 rsvd reserved. 3em3 enable map 3. 2em2 enable map 2. 1em1 enable map 1. 0em0 enable map 0.
360 amd geode? lx processors data book display controller register descriptions 33234h 6.6.18.6 vga character map select character map a (bits [5,3 :2]) and character map b (bits [4,1:0]) determi ne which font tables are used when displaying a character in text mode. when bit 3 of t he character's attribute = 1, character map a is used; when bit 3 of the character's attribute = 0, character map b is used. the font tables are stor ed in the 64 kb in map 2. there are eight font tables. the character map codes select the font tables as shown in table 6-52. 6.6.18.7 vga memory mode index 03h ty p e r / w reset value xxh vga character map select register bit descriptions bit name description 7:6 rsvd reserved. write as read. 5 char_az character map a bit 2. 4 char_bz character map b bit 2. 3:2 char_a character map a bits 1:0. 1:0 char_b character map b bits 1:0. table 6-52. font table code font table location in map 2 code font table location in map 2 0 8 kb block 0 4 8 kb block 1 1 8 kb block 2 5 8 kb block 3 2 8 kb block 4 6 8 kb block 5 3 8 kb block 6 7 8 kb block 7 index 04h ty p e r / w reset value 02h vga memory mode register bit descriptions bit name description 7:4 rsvd reserved. 3 chain4 chain4. when set to a 1, cpu address bits 1 and 0 are used to select the map or plane in the frame buffer dword. for example, if cpu a1:a0 = 3, then map 3 is selected. if cpu a1:a0 = 1, then map 1 is selected. if chain4 is 0, then the frame buffer addressing is controlled by the chain2 (bit 2). 2 chain2 chain2. when set to a 0, cpu address bit 0 sele cts between frame buffer maps 0 and 1, or maps 2 and 3, depending on the value in t he graphics controller read map select field (index 04h[1:0]). for example, if cpu a0 is 0, then map 0 (or 2) is selected. 1 ext_mem extended memory. this bit should always be set to a 1. it is a throwback to ega where the standard frame buffer size was 64 kb and was upgradeable to 256 kb. vga always has (at least) 256 kb. 0 rsvd reserved.
amd geode? lx processors data book 361 display controller register descriptions 33234h 6.6.19 vga crt controller registers the crtc registers are accessed by writing an index value to the crtc index register (3b4h or 3d4h) and reading or writ- ing the register using the crtc data register (3b5h or 3d5h). see the description of the i/o address select bit in the mis- cellaneous output register (section 6.6.17.1 on page 356) for more information on the i/o address of the crtc registers. the crt timings are controlled by the crt controller register s when the vga is active. various third-party vga adapters implement these registers differently, a nd so different cards can produce different timings with the same settings. the set- tings shown in table 6-53 are recommended for various vga modes when programming the crtc registers. note: the extended vga registers are accessed through the crtc interface. this section only discusses the base vga registers, however. see section 6.6.23 "vga block ext ended registers" on page 384 for more information on the extended registers. table 6-53. crtc register settings vga mode index 00010203040506070d0e0f10111213 0 2d2d5f5f2d2d5f5f2d5f5f5f5f5f5f 1 27274f4f27274f4f274f4f4f4f4f4f 2 282850502828505028505050505050 3 909082829090828290828282828282 4 292951512929515129515151515151 5 8e8e9e9e8e8e9e9e8e9e9e9e9e9e9e 6 bfbfbfbfbfbfbfbfbfbfbfbf0b0bbf 7 1f1f1f1f1f1f1f1f1f1f1f1f3e3e1f 8 000000000000000000000000000000 9 4f4f4f4fc1c1c14fc0c04040404041 a 0d0d0d0d0000000d00000000000000 b 0e0e0e0e0000000e00000000000000 c 000000000000000000000000000000 d 000000000000000000000000000000 e 000000000000000000000000000000 f 000000000000000000000000000000 10 9b 9b 9b 9b 9b 9b 9b 9b 9b 9b 83 83 e9 e9 9b 11 8d 8d 8d 8d 8d 8d 8d 8d 8d 8d 85 85 8b 8b 8d 12 8f 8f 8f 8f 8f 8f 8f 8f 8f 8f 5d 5d df df 8f 13 14 14 28 28 14 14 28 28 14 28 28 28 28 28 28 14 1f 1f 1f 1f 00 00 00 0f 00 00 0f 0f 00 00 40 15 97 97 97 97 97 97 97 97 97 97 65 65 e7 e7 98 16 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 04 04 b9 17 a3 a3 a3 a3 a2 a2 c2 a3 e3 e3 e3 e3 c3 e3 a3 18 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
362 amd geode? lx processors data book display controller register descriptions 33234h 6.6.19.1 crtc index table 6-54. crtc registers summary index type register reset value reference -- r/w crtc index 00h page 362 -- r/w crtc data 00h page 363 00h r/w horizontal total 00h page 363 01h r/w horizontal display enable end 00h page 363 02h r/w horizontal blank start 00h page 363 03h r/w horizontal blank end 00h page 364 04h r/w horizontal sync start 00h page 364 05h r/w horizontal sync end 00h page 364 06h r/w vertical total 00h page 365 07h r/w overflow xxh page 365 08h r/w preset row scan 00h page 365 09h r/w maximum scan line 00h page 366 0ah r/w cursor start 00h page 366 0bh r/w cursor end 00h page 367 0ch r/w start address high 00h page 367 0dh r/w start address low 00h page 367 0eh r/w cursor location high 00h page 367 0fh r/w cursor location low 00h page 368 10h r/w vertical sync start 00h page 368 11h r/w vertical sync end 00h page 368 12h r/w vertical display enable end 00h page 369 13h r/w offset 00h page 369 14h r/w underline location 00h page 369 15h r/w vertical blank start 00h page 370 16h r/w vertical blank end 00h page 370 17h r/w crtc mode control 00h page 370 18h r/w line compare 00h page 372 22h r/w cpu data latch state 00h page 372 24h r/w attribute index/data ff state 00h page 372 26h r/w attribute index state xxh page 373 index address 3b4h or 3d4h ty p e r / w reset value 00h crtc index register bit descriptions bit name description 7 rsvd reserved. 6:0 index index.
amd geode? lx processors data book 363 display controller register descriptions 33234h 6.6.19.2 crtc data 6.6.19.3 horizontal total 6.6.19.4 horizontal display enable end 6.6.19.5 horizontal blank start data address 3b5h or 3d5h ty p e r / w reset value 00h crtc data register bit descriptions bit name description 7 rsvd reserved. 6:0 data data. index 00h ty p e r / w reset value 00h horizontal total regi ster bit descriptions bit name description 7:0 h_total horizontal total. this value specifies the number of character clocks per horizontal scan line minus 5. it determines the horizontal line rate/period. index 01h ty p e r / w reset value 00h horizontal display enable end register bit descriptions bit name description 7:0 h_disp_end horizontal display enable end. this value specifies the number of displayed charac- ters minus 1. it determines the width of the horizontal display enable signal. index 02h ty p e r / w reset value 00h horizontal blank start re gister bit descriptions bit name description 7:0 h_blank_st horizontal blank start. this value specifies the character position on the line where the horizontal blanking signal goes active.
364 amd geode? lx processors data book display controller register descriptions 33234h 6.6.19.6 horizon tal blank end 6.6.19.7 horizontal sync start 6.6.19.8 horizontal sync end index 03h ty p e r / w reset value 00h horizontal blank end register bit descriptions bit name description 7 rsvd reserved. set to 1. 6:5 dispen_skew display enable skew control. this value is a binary encoded value that specifies how many character clocks to skew the horizontal display enable signal by (0 character clocks - 3 character clocks) before it is sent to t he attribute controller. this field is used to accommodate differences in the length of the video pipeline (frame buffer to pixel output) in various text and graphics modes. 4:0 h_blank_end [4:0] horizontal blank end register bits [4:0]. this 6-bit value is a compare target for the character count where the horizontal blank signal ends. bit 5 of this value is in the hori- zontal sync end register (index 05h[7]). note that not all horizontal counter bits are com- pared, which can create aliased compares dependi ng upon the binary values involved in the count range and compare values. index 04h ty p e r / w reset value 00h horizontal sync start re gister bit descriptions bit name description 7:0 h_sync_st horizontal sync start. this value specifies the character position where the horizontal sync pulse starts. index 05h ty p e r / w reset value 00h horizontal sync end register bit descriptions bit name description 7 h_blank_end5 horizontal blank end bit 5. see h_blank_end[4:0] bit description (index 03h[4:0]). 6:5 rsvd not implemented. (hsync delay). 4:0 h_sync_end horizontal sync end. these bits represent the low five bits of the character position where the horizontal sync signal ends.
amd geode? lx processors data book 365 display controller register descriptions 33234h 6.6.19.9 vertical total 6.6.19.10 overflow these are the high-order bits for several of the vertical prog ramming values. see the descriptions of the respective vertical registers for descriptions of these fields. 6.6.19.11 preset row scan index 06h ty p e r / w reset value 00h vertical total register bit descriptions bit name description 7:0 v_total[7:0] vertical total register bits [7:0]. this is the low eight bits of a value that specifies the total number of scan lines on the screen minus 2. this value includes the blanking area and determines the vertical refresh rate. the high two bits of this value are in the over- flow register (index 07h[5,1]). index 07h ty p e r / w reset value xxh overflow register bit descriptions bit name description 7 v_sync_st9 vertical sync start bit 9. see v_sync_st[7:0] bit description (index 10h[7:0]). v_sync_st8 is located at bit 2 6 v_disp_en_end9 vertical display enable end bit 9. see v_disp_end[7:0] bit description (index 12h[7:0]). v_disp_end8 is located at bit 1 5v_total9 vertical total bit 9. see v_total[7:0] bit description (index 06h[7:0]). v_total8 is located at bit 0. 4line_comp8 line compare bit 8. see line_comp[7:0] bit descr iption (index 18h[7:0]). line_comp9 is located at index 09h[6]. 3 v_blank_st8 vertical blank start bit 8. see v_blank_st[7:0 ] bit description (index 15h[7:0]). v_blank_st9 is located at index 09h[5]. 2 v_sync_st8 vertical sync start bit 8. see v_sync_st[7:0] bit description (index 10h[7:0]). v_sync_st9 is located at bit 7. 1 v_disp_en_end8 vertical display enable end bit 8. see v_disp_end[7:0] bit description (index 12h[7:0]). v_disp_end9 is located at bit 6. 0v_total8 vertical total bit 8. see vtotal[7:0] bit description (index 06h[7:0]). v_total9 is located at bit 5. index 08h ty p e r / w reset value 00h preset row scan register bit descriptions bit name description 7 rsvd reserved.
366 amd geode? lx processors data book display controller register descriptions 33234h 6.6.19.12 maximum scan line 6.6.19.13 cursor start 6:5 bype_pan byte panning. this value causes the pixel data stream to be fetched zero, one, two, or three character positions early for use with pel panning in the attribute controller. this field is used when the video serializers are chained together (by two or by four). 4:0 row_scan starting row scan. this specifies the value loaded into the row scan counter on the first text line of the screen. changing this value in text modes allows the screen to be scrolled on a scan line basis rather than a text line basis. the starting row scan count for all sub- sequent scan lines is 0. index 09h ty p e r / w reset value 00h preset row scan register bit descriptions bit name description maximum scan line register bit descriptions bit name description 7 dbl_scan double scan. when this bit is set to a 1, the row scan counter increments every other scan line. when this bit is cleared to 0, t he row scan counter increments on every scan line. this bit is used to make 200 line text modes occupy 400 physical scan lines on the screen. 6 ln_cmp9 line compare register bit 9. see line_comp[7:0] bit de scription (index 18h[7:0]). line_comp8 is located at index 07h[4]. 5 v_blank_st9 vertical blank start register bit 9. see v_blank_st[7:0] bit description (index 15h[7:0]). v_blank_st8 is located at index 09h[3]). 4:0 max_line maximum scan line. this field specifies the number of scan lines per character row minus 1. the row scan counter will count up to this value then go to 0 for the next charac- ter row. index 0ah ty p e r / w reset value 00h cursor start register bit descriptions bit name description 7:6 rsvd reserved. 5 curs_off cursor off. when set to 1, the cursor is turned off and will not appear on the screen. when this bit is 0, the cursor is displayed. this bit is only applicable in text modes. 4:0 curs_st cursor start. this field specifies the first scan line in the character box where the cursor is displayed. if this value is greater than the cursor end value (curs_end, index 0bh[4:0]), then no cursor is displayed. if this value is equal to the curs_end value, then the cursor occupies a single scan line.
amd geode? lx processors data book 367 display controller register descriptions 33234h 6.6.19.14 cursor end 6.6.19.15 start address high 6.6.19.16 start address low 6.6.19.17 cursor location high index 0bh ty p e r / w reset value 00h cursor end register bit descriptions bit name description 7 rsvd reserved. 6:5 curs_skew cursor skew. this field allows the cursor to be sk ewed by zero, one, two, or three char- acter positions to the right. 4:0 curs_end cursor end. this field specifies the last scan line in the character box where the cursor is displayed. see curs_st bit descriptions (index 0ah[4:0]) for more information. index 0ch ty p e r / w reset value 00h start address high register bit descriptions bit name description 7:0 st_addr_hi start address register bits [15:8]. together with the register (st_addr_low, index 0dh[7:0]), this value specifie s the frame buffer address used at the beginning of a screen refresh. it represents the uppe r left corner of the screen. index 0dh ty p e r / w reset value 00h start address low register bit descriptions bit name description 7:0 st_addr_low start address register bits [7:0]. together with the regist er (st_addr_hi, index 0ch[7:0]), this value specifies the frame buff er address used at the beginning of a screen refresh. it represents the upper left corner of the screen. index 0eh ty p e r / w reset value 00h cursor location high register bit descriptions bit name description 7:0 curs_hi cursor location register bits [15:8]. together with the regi ster (curs_low, index 0fh[7:0]), this value specifie s the frame buffer address where the cursor is displayed in text mode. the cursor will appear at the character whose memory address corresponds to this value.
368 amd geode? lx processors data book display controller register descriptions 33234h 6.6.19.18 cursor location low 6.6.19.19 vertical sync start 6.6.19.20 vertical sync end index 0fh ty p e r / w reset value 00h cursor location low register bit descriptions bit name description 7:0 curs_low cursor location register bits [7:0]. together with the register (curs_hi, index 0eh[7:0]), this value specifies the frame buff er address where the cursor is displayed in text mode. the cursor will appear at the character whose memory address corresponds to this value. index 10h ty p e r / w reset value 00h vertical sync start register bit descriptions bit name description 7:0 vert_sync_st vertical sync start register bits [7:0]. this value specifies the scan line number where the vertical sync signal will go active. this is a 10-bit value. bits 9 and 8 are in the overflow register (index 07h[7,2]). index 11h ty p e r / w reset value 00h vertical sync end register bit descriptions bit name description 7wr_prot write-protect registers. this bit is used to prevent old ega programs from writing invalid values to the vga horizontal timing registers. the line_comp8 (index 07h[4]) is not protected by this bit. 6 rsvd not implemented. (refresh cycle select) 5 rsvd not implemented. (enable vertical interrupt) 4 rsvd not implemented. (clear vertical interrupt) 3:0 v_sync_end vertical sync end register bits [3:0]. this field represents the low four bits of a com- pare value that specifies which scan line that the vertical sync signal goes inactive.
amd geode? lx processors data book 369 display controller register descriptions 33234h 6.6.19.21 vertical di splay enable end 6.6.19.22 offset 6.6.19.23 underline location index 12h ty p e r / w reset value 00h vertical display enable end register bit descriptions bit name description 7:0 v_disp_en_ end vertical display enable end register bits [7:0]. this is a 10-bit value that specifies the scan line where the vertical display enable signal goes inactive. it represents the number of active scan lines minus 1. bits 9 and 8 of this value are in the overflow regis- ter (index 07h[6,1]). index 13h ty p e r / w reset value 00h offset register bit descriptions bits name description 7:0 ofst offset. this field specifies the logical line width of the screen. this value (multiplied by two or four depending on the crtc clocking mode) is added to the starting address of the current scan line to get the star ting address of the next scan line. index 14h ty p e r / w reset value 00h underline location register bit descriptions bit name description 7 rsvd reserved. 6dw doubleword mode. when this bit is a 1, crtc memory addresses are dword addresses, and the crtc refresh counter effectively increments by 4. when this bit is a 0, the address increment is determined by th e byte mode bit in the crtc mode control register (index 17h[6]). 5 rsvd not implemented. (count by 4) 4:0 ul underline location. this field specifies the row scan value where the underline appears in the character box in text modes.
370 amd geode? lx processors data book display controller register descriptions 33234h 6.6.19.24 vertical blank start 6.6.19.25 vertic al blank end 6.6.19.26 crtc mode control index 15h ty p e r / w reset value 00h vertical blank start register bit descriptions bit name description 7:0 v_bl_st vertical blank start register bits [7:0]. this is the low eight bits of a value that speci- fies the starting scan line of the vertical blank signal. this is a 10-bit value. bit 8 is in the overflow register (index 07h[3]) and bit 9 is in the maximum scan line register (index 09h[5]). index 16h ty p e r / w reset value 00h vertical blank end register bit descriptions bit name description 7:0 v_bl_end vertical blank end. this value specifies the low eight bits of a compare value that repre- sents the scan line where the vertical blank signal goes inactive. index 17h ty p e r / w reset value 00h crtc mode control register bit descriptions bit name description 7 ensync enable syncs. when set to 1, this bit enables the horizontal and vertical sync signals. when 0, this bit holds both sync flip-flops reset. 6btmd byte mode. if the dword mode bit (dw, index 14h[6]) is 0, then this bit configures the crtc addresses for byte addresses when set to 1, or word addresses when set to 0. if dw is set to 1, then this bit is ignored. see table 6-55 on page 371 for information on the various crtc addressing modes. 5aw address wrap. when the crtc is addressing the frame buffer in word mode (byte mode = 0, dword mode = 0) then this bi t determines which address bit occupies the ma0 bit position of the address sent to the frame buffer memory. if address wrap = 0, crtc address counter bit 13 occupies the ma0 position. if address wrap = 1, then crtc address counter bit 15 is in the ma0 position. see table 6-55 on page 371 for information on the various crtc addressing modes. 4 rsvd reserved. 3 rsvd not implemented. (count by 2) 2 vckl_sl vclk select. this bit determines the clocking for the vertical portion of the crtc. if this bit is 0, the horizontal sync signal clocks the vert ical section. if this bit is 1, the horizontal sync divided by two clocks the vertical section.
amd geode? lx processors data book 371 display controller register descriptions 33234h table 6-55 illustrates the various frame buffer addressing sch emes. in the table, max represents the frame buffer memory address signals, ax represents the crtc address counter si gnals, rsx represents row sc an counter output bits. the binary value in the column headings is a concatenation of the dword mode and byte mode bits. (i.e., {dword mode, bytemode} in verilog.) 1 sl_rscbt select row scan bit. this bit determines which crtc signal appears on the ma14 address bit sent to the frame buffer memory. if this bit is a 0, bit 1 of the row scan counter appears on ma14. if this bit is a 1, then crtc address counter bit 14, 13, or 12 appears on ma14. see table 6-55 on page 371 for more information. 0 sl_a13 select a13. this bit determines which crtc signal appears on the ma13 address bit sent to the frame buffer memory. if this bit is a 0, bit 0 of the row scan counter appears on ma13. if this bit is a 1, then crtc addr ess counter bit 13, 12, or 11 appears on ma13. see table 6-55 on page 371 for more information. table 6-55. crtc memory addressing modes frame buffer memory address bit byte mode (01) word mode (00) dword mode (1x) ma0 a0 a15 or a13 a12 ma1 a1 a0 a13 ma2 a2 a1 a0 ma3 a3 a2 a1 ma4 a4 a3 a2 ma5 a5 a4 a3 ma6 a6 a5 a4 ma7 a7 a6 a5 ma8 a8 a7 a6 ma9 a9 a8 a7 ma10 a10 a9 a8 ma11 a11 a10 a9 ma12 a12 a11 a10 ma13 a13 or rs0 a12 or rs0 a11 or rs0 ma14 a14 or rs1 a13 or rs1 a12 or rs1 ma15 a15 a14 a13 crtc mode control register bit descriptions (continued) bit name description
372 amd geode? lx processors data book display controller register descriptions 33234h 6.6.19.27 line compare 6.6.19.28 cpu data latch state 6.6.19.29 attribute index/data ff state index 18h ty p e r / w reset value 00h line compare register bit descriptions bit name description 7:0 line_comp[7:0] line compare register bits [7:0]. this value specifies the low eight bits of a compare value that represents the scan line where t he crtc frame buffer address counter is reset to 0. this can be used to create a split screen by using the start address registers to specify a non-zero location at which to begin the screen image. the lower portion of the screen (starting at frame buffer address 0) is immune to screen scrolling (and pel panning as specified in the attribute mode co ntrol register (index 10h). line compare is a 10-bit value. bit 8 is located in the overfl ow register (index 07h[4]) and bit 9 is in the maximum scan line register (index 09h[6]). index 22h ty p e r o reset value 00h cpu data latch state re gister bit descriptions bit name description 7:0 dlv data latch value. this read only field returns a byte of the cpu data latches and can be used in vga save/restore operations. the gr aphics controller?s read map select field (index 04h[1:0]) specifies which byte/map (0-3) is returned. index 24h ty p e r o reset value 00h attribute index/data ff state register bit descriptions bit name description 7ffst ff state. this read only bit indicates the state of the attribute contro ller index/data flip- flop. when this bit is 0, the next write to index 3c0h will write an index value; when this bit is 1, the next write to index 3c0h will write a data register value. 6:0 rsvd reserved.
amd geode? lx processors data book 373 display controller register descriptions 33234h 6.6.19.30 attribute index state 6.6.20 vga graphics controller registers the graphics controller registers are accessed by writing an index value to the graphics controller index register (index address 3ceh) and reading or writing the register using th e graphics controller data register (data address 3cfh). 6.6.20.1 vga graphics controller index index 26h ty p e r o reset value xxh attribute index state register bit descriptions bit name description 7:6 rsvd reserved. 5:0 att_in_va attribute index value. this read only value indicates the value of attribute index regis- ter bits [5:0] (index 3c0h). table 6-56. graphics controller registers summary index type register reset value reference -- r/w vga graphics controller index xxh page 373 -- r/w vga graphics controller data xxh page 374 00h r/w vga set/reset xxh page 374 01h r/w vga enable set/reset xxh page 374 02h r/w vga color compare xxh page 375 03h r/w vga data rotate xxh page 375 04h r/w vga read map select xxh page 376 05h r/w vga graphics mode xxh page 376 06h r/w vga miscellaneous xxh page 377 07h r/w vga color don?t care xxh page 378 08h r/w vga bit mask xxh page 378 index address 3ceh ty p e r / w reset value xxh vga graphics controller inde x register bit descriptions bit name description 7:4 rsvd reserved. 3:0 index index.
374 amd geode? lx processors data book display controller register descriptions 33234h 6.6.20.2 vga graphics controller data 6.6.20.3 vga set/reset bits [3:0] allow bits in their respective maps to be set or reset through write modes 0 or 3. see section 6.5.5.3 "write modes" on page 290 for more information. 6.6.20.4 vga enable set/reset bits [3:0] enable the set/reset function for their respective maps in write mode 0. see section 6.5.5.3 "write modes" on page 290 for more information. data address 3cfh ty p e r / w reset value xxh vga graphics controller data register bit descriptions bit name description 7:4 rsvd reserved. 3:0 data data. index 00h ty p e r / w reset value xxh vga set/reset register bits bit descriptions bit name description 7:4 rsvd reserved. 3sr_mp3 set/reset map 3. 2sr_mp2 set/reset map 2. 1sr_mp1 set/reset map 1. 0sr_mp0 set/reset map 0 index 01h ty p e r / w reset value xxh vga enable set/reset re gister bit descriptions bit name description 7:4 rsvd reserved. 3 en_sr_mp3 enable set/reset map 3. 2 en_sr_mp2 enable set/reset map 2. 1 en_sr_mp1 enable set/reset map 1. 0 en_sr_mp0 enable set/reset map 0.
amd geode? lx processors data book 375 display controller register descriptions 33234h 6.6.20.5 vga color compare bits [3:0] specify a compare value that allows the cpu to co mpare pixels in planar modes. read mode 1 performs a com- parison based on these bits combined with the color don?t care bits. data returned will contain a 1 in each one of the eight pixel positions where a color match is found. see the descrip tion of read modes (section 6.5.5.4 on page 291) for more information. 6.6.20.6 vga data rotate index 02h ty p e r / w reset value xxh vga color compare register bit descriptions bit name description 7:4 rsvd reserved. 3co_cm_mp3 color compare map 3. 2co_cm_mp2 color compare map 2. 1co_cm_mp1 color compare map 1. 0co_cm_mp0 color compare map 0. index 03h ty p e r / w reset value xxh vga data rotate bit desc riptions bit descriptions bit name description 7:5 rsvd reserved. 4:3 wrop write operation. data written to the frame buffer by the cpu can be logically combined with data already in the cpu data latches. 00: copy (cpu data written unmodified). 01: cpu data anded with latched data. 10: cpu data ored with latched data. 11: cpu data xored with latched data. see the description of write modes (section 6.5.5.3 on page 290) for more information. 2:0 rotcnt rotate count . this value is used to rotate the cpu data before it is used in write modes 0 and 3. the cpu data byte written is rotated right, with low bits wrapping to the high bit positions. see the description of write m odes (section 6.5.5.3 on page 290) for more information.
376 amd geode? lx processors data book display controller register descriptions 33234h 6.6.20.7 vga read map select 6.6.20.8 vga graphics mode index 04h ty p e r / w reset value xxh vga read map select register bit descriptions bit name description 7:2 rsvd reserved. 1:0 r_mp_sl read map select. this field specifies which map cpu read data is taken from in read mode 0. in odd/even modes (specified by the odd/even bit in the graphics mode regis- ter, index 05h[4]) bit 1 of this field sp ecifies which pair of maps returns data. when bit 1 is 0, data is returned from maps 0 a nd 1. when bit 1 is 1, data is returned from maps 2 and 3. the cpu read address bit a0 determines which byte is returned (low or high) in odd/even modes. in non-odd/even modes , these bits (both bits [1:0]) specify the map to read (0, 1, 2, or 3) and the cp u accesses data sequentially within the speci- fied map. index 05h ty p e r / w reset value xxh vga graphics mode register bit descriptions bit name description 7 rsvd reserved. 6 256_cm 256 color mode. when set to a 1, this bit configures the video serializers in the graphics controller for the 256 color mode (bios mode 13h). when this bit is 0, the shift register mode bit (bit 5) controls the serializer configuration. 5 sh_r_md shift register mode. when set to a 1, this bit configures the video serializers for bios modes 4 and 5. when this bit is 0, the serializers are taken in parallel (i.e., configured for 4-bit planar mode operation). note that the serializers are also wired toget her serially so that map 3 bit 7 feeds map 2 bit 0, map 2 bit 7 feeds map 1 bit 0, and map 1 bit 7 feeds map 0 bit 0. this allows for a 32-pixel 1 bit-per-pixel serializer to be used. fo r this configuration, color planes 1, 2, and 3 should be masked off using the color plane enable register (attribute controller, index 12h, on page 381.) 4 odd_even odd/even. when this bit is set to 1, cpu address bit a0 will select between maps 0 and 1 or maps 2 and 3 depending on the state of the read map select field (index 04h[1:0]). when this bit is 0, the cpu accesses data sequentially within a map. this bit is equiva- lent to the odd/even bit in the vga miscellaneous register (index 06h[2]), but is inverted in polarity from that bit. 3 rd_md read mode. this bit determines what is returned to the cpu when it reads the frame buffer. when this bit is 1, the result of a color compare operation is returned. the eight bits in the cpu read data contain a 1 in each pixel position where the color compare operation was true, and a 0 where the operation was false. when this bit is 0, frame buffer map data is returned. 2 rsvd reserved.
amd geode? lx processors data book 377 display controller register descriptions 33234h 6.6.20.9 vga miscellaneous 1:0 wr_md write mode. this field specifies how cpu data is written to the frame buffer. note that the write operation field in the vga data rota te register (index 03h[4:3]) specifies how cpu data is combined with data in the dat a latches for write modes 0, 2, and 3. 00: write mode 0: cpu data is rotated by th e count in the vga data rotate register. each map enabled by the vga map mask register (index 02h) is written by the rotated cpu data combined with the latch data (if set/reset is not enabled for that map) or by the map?s corresp onding set/reset bit replicat ed across the 8- bit byte (if set/reset is enabled for that map). the vga bit mask register (index 08h) is used to protect individual bits in each map from being updated. 01: write mode 1: each map enabled by the vga map mask register is written with its corresponding byte in the data latches. 10: write mode 2: cpu data is replicat ed for each map and combined with the data latches and written to memory. the vga bit mask register (index 08h) is used to protect individual bits in each map from being updated. 11: write mode 3: each map is written wit h its corresponding set/reset bit replicated through a byte (enable set/reset is ignor ed). the cpu data is rotated and anded with the vga bit mask register (index 08h). the resulting mask is used to protect individual bits in each map. index 06h ty p e r / w reset value xxh vga miscellaneous register bit descriptions bit name description 7:4 rsvd reserved. 3:2 mem_map memory map . this field controls the address mapping of the frame buffer in the cpu memory space. 00: memory map 0: a0000 to bffff (128 kb) 01: memory map 1: a0000 to affff (64 kb) 10: memory map 2: b0000 to b7fff (32 kb) 11: memory map 3: b8000 to bffff (32 kb) 1 odd_even odd/even . when set to 1, this bit replaces the cpu a0 address bit with a higher order bit when addressing the frame buffer. odd maps are then selected when cpu a0 = 1, and even maps selected when cpu a0 = 0. 0gph_md graphics mode . 0: text mode operation. 1: graphics mode operation. vga graphics mode register bit descriptions bit name description
378 amd geode? lx processors data book display controller register descriptions 33234h 6.6.20.10 vga color don?t care 6.6.20.11 vga bit mask 6.6.21 attribute controller registers the attribute controller registers are accessed by writing an inde x value to the attribute controller index register (3c0h) and reading or writing the register using the attribute controller data register (3c0h for writes, 3c1h for reads). index 07h ty p e r / w reset value xxh vga color don?t care register bit descriptions bit name description 7:4 rsvd reserved. 3cm_pr3 compare map 3. this bit enables (bit = 1) or excludes (bit = 0) map 3 from participating in a color compare operation. 2cm_pr2 compare map 2. this bit enables (bit = 1) or excludes (bit = 0) map 2 from participating in a color compare operation. 1cm_pr1 compare map 1. this bit enables (bit = 1) or excludes (bit = 0) map 1 from participating in a color compare operation. 0cm_pr0 compare map 0. this bit enables (bit = 1) or excludes (bit = 0) map 0 from participating in a color compare operation. index 08h ty p e r / w reset value xxh vga bit mask register bit descriptions bit name description 7:0 bt_msk bit mask . the bit mask is used to enable or disable writing to individual bits in each map. a 1 in the bit mask allows a bit to be updated, while a 0 in the bit mask writes the contents of the data latches back to memory, effectivel y protecting that bit from update. the data latches must be set by doing a frame buffer read in order for the masking operation to work properly. the bit mask is used in write modes 0, 2, and 3. table 6-57. attribute controller registers summary index type register reset value reference -- r/w attribute controller index/data/data xxh page 379 00h-0fh r/w ega palette xxh page 379 10h r/w attribute mode control xxh page 380 11h r/w overscan color xxh page 380 12h r/w color plane enable xxh page 381 13h r/w horizontal pel panning xxh page 381 14h r/w color select xxh page 382
amd geode? lx processors data book 379 display controller register descriptions 33234h 6.6.21.1 attribute controller index/data the attribute controller registers do not have a separate addr ess for writing index and data information. instead, an internal flip-flop alternates between index and data registers. reading in put status register 1 (3bah or 3dah) clears the flip-flop to the index state. the first write to 3c0h following a read from input status register 1 will u pdate the index register. the next write will update the selected data register. the next write specifies a new index, etc. 6.6.21.2 ega palette index address 3c0h data address 3c1h (r) 3c0h (w) ty p e r / w reset value xxh attribute controller index register bit descriptions bit name description 7:6 rsvd reserved. 5 int_pal_ad internal palette address. this bit determines whether the ega palette is addressed by the video pixel stream (bit = 1) or by the attribute controller index register (bit = 0). this bit should be set to 1 for normal vga operati on. cpu i/o accesses to the palette are dis- abled unless this bit is a 0. 4:0 data_rg_inx data register index. this field addresses the indivi dual palette and data registers. index 00h-0fh ty p e r / w reset value xxh ega palette register bit descriptions bit name description 7:6 rsvd reserved. 5:0 col_val color value. each of these 16 registers is used to expand the pixel value from the frame buffer (one, two, or four bits wide) into a 6- bit color value that is sent the video dac. the ega palette is ?programmed out of the way? in 256 color mode. these registers can only be read or written when the internal palette a ddress bit in the index register (3c0h) is 0.
380 amd geode? lx processors data book display controller register descriptions 33234h 6.6.21.3 attribute mode control 6.6.21.4 overscan color index 10h ty p e r / w reset value xxh attribute mode control register bit descriptions bit name description 7 p5:4_sel p5:4 select. when this bit is a 1, bits [5:4] of the 8-bit vga pixel value are taken from bits [1:0] of the color select register (index 14h). when a 0, bits [5:4] of the pixel are taken from bits [5:4] of the ega palette output. 6 pel_w pel width. this bit is used in 256 color mode to shift four pixels through the attribute controller for each character clock. clearing this bit shifts eight pixels for each charac- ter clock. 5 pel_pan_comp pel panning compatibility. when this bit is a 1, the scan lines following a line com- pare are immune to the effects of the pel panning. when this bit is a 0, the entire screen is affected by pel panning, regar dless of the line compare operation. 4 rsvd reserved. 3en_blink enable blink. when this bit is a 1, attribute bit 7 is used to cause a character to blink (bit 7 = 1) or not (bit 7 = 0). when this bit is 0, attribute bit 7 is used as a background intensity bit. 2 en_lgc enable line graphics codes. when this bit is 0, the 9th dot in 9-wide character modes is always set to the background color. wh en this bit is 1, the 9th dot is equal to the foreground color for character codes c0h-dfh, which are the line graphics charac- ter codes. 1mon_emu monochrome emulation. when this bit is a 1, the underline in 9-dot mode extends for all nine dots and an underlined phrase will ha ve a continuous line under it. when this bit is 0, the underline is only active for eight dots, and an underlined phrase will have a broken line under it. 0gr_mode graphics mode. when this bit is 1, graphics mode is selected and pixel data from the frame buffer is used to produce the pixel stream. when this bit is 0, text mode is selected, and text attribute and font pattern information is used to produce the pixel stream. index 11h ty p e r / w reset value xxh overscan color register bit descriptions bit name description 7:0 over_color overscan color . this value is output as the pixel value to the video dac when the dis- play enable signal from the crtc is inactive.
amd geode? lx processors data book 381 display controller register descriptions 33234h 6.6.21.5 color plane enable 6.6.21.6 horizontal pel panning index 12h ty p e r / w reset value xxh color plane enable register bit descriptions bit name description 7:4 rsvd reserved. 3 en_co_pn3 enable color plane 3. this bit enables color plane 3. it is anded with it corresponding pixel bit and the resulting 4-bit value is used as the address into the ega palette. 2 en_co_pn2 enable color plane 2. this bit enables color plane 2. it is anded with it corresponding pixel bit and the resulting 4-bit value is used as the address into the ega palette. 1 en_co_pn1 enable color plane 1. this bit enables color plane 1. it is anded with it corresponding pixel bit and the resulting 4-bit value is used as the address into the ega palette. 0 en_co_pn0 enable color plane 0. this bit enables color plane 0. it is anded with it corresponding pixel bit and the resulting 4-bit value is used as the address into the ega palette. index 13h ty p e r / w reset value xxh horizontal pel panning register bit descriptions bit name description 7:4 rsvd reserved. 3:0 hpp horizontal pel panning : this field specifies how many pixels the screen image should be shifted to the left by. bits [3:0] mode 13h panning 9-wide text mode panning panning for all other modes 0000 0 1 0 0001 -- 2 1 0010 1 3 2 0011 -- 4 3 0100 2 5 4 0101 -- 6 5 0110 3 7 6 0111 -- 8 7 1000 -- 0 - 1001 -- -- -- 1010 -- -- -- 1011 -- -- -- 1100 -- -- -- 1101 -- -- -- 1110 -- -- -- 1111 -- -- --
382 amd geode? lx processors data book display controller register descriptions 33234h 6.6.21.7 color select 6.6.22 video dac registers video dac palette registers are accessed by writing the palette address register at the read or write address, then perform- ing three reads or writes, one for each of the red, green, and blue color values. the video dac provides an address incre- ment feature that allows multiple sets of color triplets to be read or written witho ut writing the palette address register aga in. to invoke this feature, simply follow the first triplet read/write with the next triplet read/write. the original ibm video dac behavior for read operations is: 1) cpu initiates a palette read by writing index to i/o address 3c7h. 2) video dac loads a temporary register with the value stored at palette[index]. 3) video dac increments index (index = index + 1). 4) cpu reads red, green, blue color values from temporary register at i/o address 3c9h. 5) loop to step 2. the original ibm video dac behavior for write operations is: 1) cpu initiates a palette write by writing index to i/o address 3c8h. 2) cpu writes red, green, blue color values to temporary dac registers at i/o address 3c9h. 3) video dac stores the temporary register contents in palette[index]. 4) video dac increments index (index = index + 1). 5) loop to step 2. index 14h ty p e r / w reset value xxh color select regist er bit descriptions bit name description 7:4 rsvd reserved. 3:2 p[7:6] p7 and p6. these bits are used to provide the upper two bits of the 8-bit pixel value sent to the video dac in all modes except the 256 color mode (mode 13h). 1:0 p[5:4] p5 and p4. these bits are used to provide bits 5 and 4 of the 8-bit pixel value sent to the video dac when the p5:4 select bit is set in the attribute mode control register (index 10h[7]). in this case, they replace bi ts [5:4] coming from the ega palette. table 6-58. video dac registers summary i/o address type register reset value reference 3c8h ro palette address (write mode) 00h page 383 3c7h ro palette address (read mode) 00h page 383 3c7h ro dac state 00h page 383 3c9h r/w palette data 00h page 380 3c6h r/w pel mask 00h page 380
amd geode? lx processors data book 383 display controller register descriptions 33234h 6.6.22.1 video dac palette address 6.6.22.2 video dac state 6.6.22.3 video dac palette data read address 3c8h write address 3c7h (palette read mode) 3c8h (palette write mode) ty p e r o reset value 00h video dac palette address register bit descriptions bit name description 7:0 addr palette address. read address 3c7h write address -- ty p e r o reset value 00h video dac state register bit descriptions bit name description 7:2 rsvd reserved. 1:0 dac_st dac state. this register returns th e dac state for save/restore operations. if the last palette address write was to 3c7h (read mode), both bits are 1 (value = 11). if the last palette address write was to 3c8h (write mode), both bits are 0 (value = 00). read address 3c9h write address 3c9h ty p e r / w reset value 00h video dac palette data register bit descriptions bit name description 7:6 rsvd reserved. 5:0 co_cpn_val color component value. this is a 6-bit color component value that drives the video dac for the appropriate color component when the current palette write address is used to address the video dac in the pixel stream.
384 amd geode? lx processors data book display controller register descriptions 33234h 6.6.22.4 video dac palette mask 6.6.23 vga block extended registers the extended registers are accessed by writing an index value to the crtc index register (3b4h or 3d4h) and reading or writing the register using the crtc data register (3b5h or 3d 5h). see the description of the i/o address select bit in the section 6.6.17.1 "vga miscellaneous output" on page 356 for more information on the i/o address of the crtc registers. read address 3c6h write address 3c6h ty p e r / w reset value 00h video dac palette mask register bit descriptions bit name description 7:0 pal_msk palette mask. these bits enable their respective color bits between the final vga 8-bit pixel output and the dac palette. the bits are anded with the incoming vga pixel value and the result used to address the palette ram. table 6-59. extended registers summary index type register reset value reference 0030h r/w extendedregisterlock ffh page 385 043h r/w (note 1) note 1. r/w when unlocked, ro otherwise (see sect ion 6.6.23.1 "extendedregisterlock" for details). extendedmodecontrol 00h page 385 044h r/w (note 1) extendedstartaddress 00h page 385 047h r/w (note 1) writememoryaperture 00h page 386 048h r/w (note 1) readmemoryaperture 00h page 386 060h r/w (note 1) blinkcounterctl (for sim/test) 00h page 386 061h r/w (note 1) blinkcounter (for sim/test) 00h page 387 070h r/w (note 1) vgalatchsavres 00h page 387 071h r/w (note 1) dacifsavres 00h page 387
amd geode? lx processors data book 385 display controller register descriptions 33234h 6.6.23.1 extende dregisterlock 6.6.23.2 extende dmodecontrol 6.6.23.3 extendedstartaddress crtc index 030h ty p e r / w reset value ffh extendedregisterlock register bit descriptions bit name description 7:0 lock lock. a value of 4ch unlocks the extended registers. any other value locks the extended registers so they are read only. if the extended registers are currently locked, a read to this register will return ffh. if th ey are unlocked, a read will return 0. crtc index 043h ty p e r / w reset value 00h extendedmodecontrol register bit descriptions bit name description 7:3 rsvd reserved. 2:1 vg_rg_map dc register mapping. these bits determine the dc register visibility within the standard vga memory space (a0000h-bffffh). note th at the vga address space control bits override this feature. if the miscellaneous output register ram enable bit is 0, all vga memory space is disabled. or, if the memory map bits of the graphics miscellaneous register are set the same as these bits, then the vga frame buffer memory will appear in this space instead of the gui registers. 00: disabled 01: a0000h 10: b0000h 11: b8000h 0 pack_ch4 packed chain4 : when this bit is set, the chain4 memory mapping will not skip dwords as in true vga. host reads and writes to frame buffer dwords are contiguous. when this bit is 0, host accesses behave normally and access 1 dword out of every 4. note that this bit has no effect on the vga display refresh activity. this bit is only intended to provide a front end for packed svga modes being displayed by dc. crtc index 044h ty p e r / w reset value 00h extendedstartaddress register bit descriptions bit name description 7:6 rsvd reserved. 5:0 st_ad_rg [21:16] start address register bits [21:16]. start address register bits [23:18]: these bits extend the vga start address to 24 bits. bits [17:10] are in start address hi (index 0ch), and bits [9:2] are in start address lo (index 0ch).
386 amd geode? lx processors data book display controller register descriptions 33234h 6.6.23.4 writememoryaperture 6.6.23.5 readmemoryaperture 6.6.23.6 blinkcounterctl this register is for simulation and test only. crtc index 047h ty p e r / w reset value 00h writememoryaperture register bit descriptions bit name description 7:0 wr_base writebase. offset added to the graphics memory base to specify where vga write oper- ations start. this value provides dword address bits [21:14] when mapping host vga writes to graphics memory. this allows the vga base address to start on any 64 kb boundary within the 8 mb of graphics memory. crtc index 048h ty p e r / w reset value 00h readmemoryaperture register bit descriptions bit name description 7:0 rd_base readbase. offset added to the graphics memory base to specify where vga read oper- ations start. this value provides dword address bits [21:14] when mapping host vga reads to graphics memory. this allows the vga base address to start on any 64 kb boundary within the 8 mb of graphics memory. crtc index 060h ty p e r / w reset value 00h blinkcounterctl register bit descriptions bit name description 7 hld_cnt hold count. when set, prevents the blink counter from incrementing with each leading edge vsync. 6:5 rsvd reserved. 4:0 blnk_cnt blink count. the blink counter is loaded with this value while the sequencer reset reg- ister is in the reset state.
amd geode? lx processors data book 387 display controller register descriptions 33234h 6.6.23.7 blinkcounter this register is for simulation and test only. 6.6.23.8 vgalatchsavres 6.6.23.9 dacifsavres crtc index 061h ty p e r o reset value 00h blinkcounter register bit descriptions bit name description 7:5 rsvd reserved. 4:0 blnk_cnt blink count. these bits provide a real-time blink c ounter value. this register is not syn- chronized to the system clock domain. crtc index 070h ty p e r / w reset value 00h vgalatchsavres register bit descriptions bit name description 7:0 vga_lsr vgalatchsavres. this register is used to save/r estore the 32-bit vga data latch. when the crtc index register is written, an internal byte counter is cleared to 0. four successive reads or writes to the crtc data register at this index will return or write bytes 0 (bits [7:0]), 1 (bits [15:8]), 2 (bit s [23:16]), then 3 (bit s [31:24]) in sequence. crtc index 071h ty p e r / w reset value 00h dacifsavres register bit descriptions bit name description 7:0 dacifsr dacifsavres. this register is used to save/restore the vga palette interface logic state. when the crtc index register is written, an internal byte counter is cleared to 0. four successive reads or writes to the crtc data register at this index will return or write bytes 0 (bits [7:0]), 1 (bits [15:8]), 2 (bit s [23:16]), then 3 (bit s [31:24]) in sequence.
388 amd geode? lx processors data book video processor 33234h 6.7 video processor the video processor (vp) module provides a high-perfor- mance, low-power crt/tft disp lay or video output inter- face. there are three main functions contained within the vp: the video processor, the tft controller, and the video output port (vop). the scaling, filtering, and color space conversion algorithms implemented in the vp are of much higher quality than those used in software-only video play- back systems. the vp is capable of delivering high-resolu- tion and true-color graphics. it can also overlay or blend a scaled true-color video image on the graphic background. for video input, integrated scaling, and x and y interpola- tion, enable real-time motion video output. the video path of the vp also contains horizontal and vertical scaling hard- ware, and an optional yuv-to-rgb color space converter. this motion video acceleration circuitry is integrated into the video processor to improve video playback. by off- loading these arithmetic-int ensive tasks from the proces- sor, 30 frame-per-second playback can be easily achieved, while keeping processor utilization to acceptable perfor- mance levels. the graphics and video path is illustrated in figure 6-23 on page 389. general features ? hardware video acceleration ? graphics/video overlay and blending ? progressive video from the display controller module ? dot clocks up to 350 mhz hardware video acceleration ? arbitrary x and y interpolation using three line-buffers ? yuv-to-rgb color space conversion ? horizontal filtering and downscaling ? supports 4:2:2 and 4:2:0 yuv formats and rgb 5:6:5 format graphics-video over lay and blending ? overlay of true-color video up to 24-bpp ? supports chroma key and color key for both graphics and video streams ? supports alpha-blending with up to three alpha windows that can overlap one another ? 8-bit alpha values with autom atic increment or decre- ment on each frame ? optional gamma correction for video or graphics compatibility ? supports microsoft?s direct draw/direct video and dci (display controller interface) v2.0 for full motion video playback acceleration ? compatible with vesa, vga, and dpms standards for enhanced display control and power management 6.7.1 architecture overview the video processor module contains the following func- tional blocks. (figure 6-23 on page 389 shows the relation- ships between these blocks): ? video data interface ? video formatter ?downscaler ? 5 line buffers ? vertical upscaler (programmable up to x8) ? horizontal upscaler (programmable up to x8) ? control registers ? mixer/blender ? color space converter (csc) ?gamma ram ? color keys ? alpha blender ? crt dacs ? tft interface ? video output port
amd geode? lx processors data book 389 video processor 33234h figure 6-23. video processor block diagram video data interface (yuv) control registers interface graphics data interface (rgb) video formatter x and y scaler mixer/blender (overly with alpha blending, csc and gamma ram) delay video output port output format (mux) output devices vip tv encoder crt dac (3x8 bit) tft panel amd geode? companion video processor panel interface dither engine tft timing generator flat panel display controller display controller video data controller video data graphics data dot clock flat panel data + cntl vp rgb + cntl vp yuv + cntl fmt_sel 24 3 27 3 27 16 31 3 24 3 2 16 pixel data pixel cntl video processor module companion device bypass device
390 amd geode? lx processors data book video processor 33234h 6.7.2 functional description the vp receives the input video stream in either yuv (4:2:2 or 4:2:0) or rgb (5:6:5) format. the vp has an inte- grated color space converter to convert yuv data to rgb data. the video clock must always be active (regardless of the source of video input). either graphics, or graphics and video mixed (via color- keying or alpha-blending) can be displayed. mixing can be performed in either the rgb or yuv domain. for video input, integrated scaling and x and y interpola- tion enable real-time motion video output. the video path of the vp also contains horizontal and vertical scaling hard- ware, and an optional yuv-to-rgb color space converter. this motion video acceleration circuitry is integrated into the vp to improve video playback. by off-loading these arithmetic-inten sive tasks from the cpu, 30 frame-per-sec- ond playback can be easily achieved, while keeping cpu utilization to acceptable performance levels. figure 6-24. video processor block diagram 8 dac rgb downscaler formatter 24 (5x480x64 bit) dac dac 8 8 to crt graphic m m + 1 1 m + 1 or (4:2:2 or 4:2:0) 4:4:4 96 yuv444 or rgb888 line buffer 0 rgb video formatter mixer/blender (overlay with alpha-blending, color space converter, and gamma ram) 24 video data i/f (yuv) data i/f (rgb) line buffer 1 line buffer 2 line buffer 3 line buffer 4 96 32 96 96 80 80 80 ver tical scale 4 parallel 4-tap filters horizontal scale 4-tap filter or yuv
amd geode? lx processors data book 391 video processor 33234h 6.7.2.1 video formatter the video processor module accepts video data at a rate asynchronous to the gliu clock rate. the byte order of video input data can be configured using the vid_fmt bits in the video configuration register (vp memory offset 000h[3:2]). video input data can be in yu v 4:2:2, yuv 4:2:0, or rgb 5:6:5 format. the video input data is packed into a 32-bit word and written to one of three on-chip line buffers to significantly reduce video bandwidth. each line buffer is 480x64 bits, and supports up to a maximum of 1920 hori- zontal source video pixels. yuv video formats two different input data formats can be used by the video formatter for overlay of video or graphics data: 1) 4:2:2 video format four different types of 4:2:2 formats may be used. see the vid_fmt bits in the video configuration register (vp memory offset 000h[3:2]) for details about these formats. ensure that the selected format is appropriate for the data source. 2) 4:2:0 video format this format contains all y data for each line followed by all u data and all v data. for example, for a line with 720 pixels, 720 bytes of y data is followed by 360 bytes of u data and 360 bytes of v data for that line. this format is usually used for input from the proces- sor video buffer (i.e., generated by application soft- ware). this format is selected when the en_420 bit (vp memory offset 000h[28]) is set to 1. the following possible subformat types (described for four bytes of data) can be selected via the vid_fmt bits (vp mem- ory offset 000h[3:2]): 00: y0 y1 y2 y3 01: y3 y2 y1 y0 10: y1 y0 y3 y2 11: y1 y2 y3 y0 note: the above formats describe y data. u and v data have the same format (where ?u? and ?v? replace the ?y? in this sample). rgb video format in this format, each pixel is described by 16 bits: bits [15:11]: red bits [10:5]: green bits [4:0]: blue this format can be used for a second graphics plane if video mixing is not used. four subformats can be selected via the vid_fmt bits (vp memory offset 000h[3:2]): 00: p1l p1m p2l p2m 01: p2m p2l p1m p1l 10: p1m p1l p2m p2l 11: p1m p2l p2m p1l notes: 1) p1m is the most significant byte (msb) of pixel 1. 2) p1l is the least significant byte (lsb) of pixel 1. 3) p2m is the msb of pixel 2. 4) p2l is the lsb of pixel 2. 5) within each pixel (2 bytes) rgb ordering is constant. 6) this mode does not work if en_420 is high (vp mem- ory offset 000h[28] = 1). 6.7.2.2 4x4 filter/scaler ? accepts all sd and hd television resolutions as well as non-standard video window sizes. ? horizontal arbitrary scaling: ? up to 1:8 upscale. ? down to 8:1 downscale. ? vertical arbitrary scaling: ? up to 1:8 upscale. ? down to 2:1 downscale. ? 16-pixel filtering: ? one horizontal 4-tap filter. ? four parallel vertical 4-tap filters. ? 128 or 256 phase in both horizontal and vertical directions. ? programmable 16-bit signed horizontal and vertical coefficients. ? five video line buffers: ? four active line buffers. ? one extra line buffer for buffer elasticity and down- scale. ? line buffer interface operates at gliu clock up to 400 mhz. ? horizontal and vertical filter/scaler operates at dot clock up to 350 mhz the vp 4x4 filter/scaler contains multiple 4-tap filters that are used in conjunction wit h an upscale/downscale pro- cessing section. there are five video line buffers that store yuv pixels for upcoming display lines.
392 amd geode? lx processors data book video processor 33234h 6.7.2.3 horizontal downscaling the video processor module supports horizontal down- scaling (see figure 6-25). the downscaler can be imple- mented in the video processor module to shrink the video window by a factor of up to 8:1, in one-pixel increments. the downscaler factor select (m) is programmed in the video downscaler control register (vp memory offset 078h[4:1]). if bit 0 (dcf) of th is register is set to 0, the downscaler logic is bypassed. note: horizontal downscaling is supported in 4:2:2 yuv video format only, not 4:2:0 yuv or 5:6:5 rgb. the downscaler supports up to 29 downscaler factors. there are two types of factors: ? type a is (1/m+1). one pixel is retained, and m pixels are dropped. this enables down scaling factors of 1/8, 1/ 7, 1/6, 1/5, 1/4, 1/3, and 1/2. ? type b is (m/m+1). m pixels are retained, and one pixel is dropped. this enables downscaling factors of 2/3, 3/4, 4/5, 5/6, 6/7, 7/8. bit 6 of the video downscaler control register (vp memory offset 078h) selects the type of downscaling factor to be used. note: there is no vertical downscaling in the video pro- cessor module. figure 6-25. downscaler block diagram bypass 4-tap horizontal 4x8 downscale filtering coefficients downscaler factors to line buffers video input
amd geode? lx processors data book 393 video processor 33234h 6.7.3 x and y upscaler after the video data has been buffered, the upscaling algo- rithm is applied. the video processor module employs a digital differential analyzer-style (dda) algorithm for both horizontal and vertical upscaling. the scaling parameters are programmed via the video scale register (vp memory offset 020h). the scalers support up to 8x scale factors both horizontally and vertically. the scaled video pixel stream is then passed through bi-linear interpolating filters (2-tap, 8-phase) to smooth the output video, significantly enhancing the quality of the displayed image. the x and y upscaler uses the dda and linear interpolat- ing filter to calculate (via inte rpolation) the values of the pix- els to be generated. the interpolation formula uses a i,j , a i,j+1 , a i+1,j , and a i+1,j+1 values to calculate the value of intermediate points. the actual location of calculated points is determined by the dda algorithm. the location of each intermediate point is one of eight phases between the original pixels (see figure 6-26). 6.7.4 color space converter after scaling and filtering have been performed, yuv video data is passed through the color space converter to obtain 24-bit rgb video data. color space conversion equations are based on the bt.601-1 recommendation: standard definition color space conversion equations are based on microsoft?s recommendations as follows: r = 1.164383(y-16) + 1.596027(v-128) g = 1.164383(y-16) - 0.812968(v-128) - 0.391762 (u-128) b = 1.164383(y-16) + 2.017232(u-128) for high definition video, the color space conversion equa- tions are based on rec. itu-r bt.709 as follows: r = 1.164383(y-16) + 1.792742(v-128) g = 1.164383(y-16) - 0.532909(v-128) - 0.213249 (u-128) b = 1.164383(y-16) + 2.112402(u-128) the color space converter clamps inputs to prevent them from exceeding acceptable limits. the color space converter can be bypassed for overlaying 16-bpp graphics data. figure 6-26. linear interpolation calculation b 1 b 2 x z y a i,j+1 a i+1,j+1 a i+1,j a i,j notes: x and y are 0 - 7 b 1 a ij , () 8 y ? 8 ----------- - a i 1 j , + () y 8 -- - + = b 2 a ij ,1 + () 8 y ? 8 ----------- - a i 1 j 1 + , + () y 8 -- - + = zb 1 () 8 x ? 8 ----------- - b 2 () x 8 -- - + =
394 amd geode? lx processors data book video processor 33234h 6.7.5 video overlay video data is mixed with graphics data according to the video window position. the video window position is pro- grammable via the video x position (vp memory offset 010h) and video y position (vp memory offset 018h) reg- isters. a color-keying and alpha-blending mechanism is employed to compare either the source (video) or destina- tion (graphics) color to the color key programmed via the video color key register (vp memory offset 028h), and to select the appropriate bits in the video color mask register (vp memory offset 030h). this mechanism greatly reduces the software overhead for computing visible pix- els, and ensures that the video display window can be par- tially hidden by overlapping graphics data. see figure 6-27 on page 395. the video processor module accepts graphics data at the graphics dot clock rate. the video processor module can display graphics resolutions up to 1920x1440 on crt, at color depths up to 24-bpp while simultaneously overlaying a video window. 6.7.5.1 alpha-blending alpha-blending can be performed using rgb blending or yuv blending: ? for rgb blending, graphic data in rgb format and video data in rgb format (yuv to rgb conversion) are blended. ? yuv blending eliminates video de-interlacing and yuv to rgb conversion of video data. for yuv blending, the graphic data is converted to yuv and blended with video in yuv format. up to three alpha windows can be defined in the video win- dow. alpha values for blending are defined for each pixel in the upper 8 bits of video data. if alpha windows overlap, the alpha window with the highest priority (programmable) is used (for the overlapped area). alpha-blending is performed using the following formula: alpha * g + (1 - alpha) * v where g is the graphic value and v is the video value of the current pixel. color keys a color key mechanism is used with alpha-blending. color key values are defined for a cursor color key and for a nor- mal color key. the cursor colo r key is compared to each 24- bit value of graphic input data. if a match is found, the selected cursor color is disp layed. two possible cursor col- ors can be defined. the color_reg_offset field (in the cursor color key register, vp memory offset 0a0h[28:24]) is used to select the bit in the input graphic stream that determines the cursor color to use. each cur- sor color is stored in a separate cursor color register. fig- ure 6-28 on page 396 illustrates the logic used to determine how to implement the color key and alpha-blend- ing logic.
amd geode? lx processors data book 395 video processor 33234h figure 6-27. mixer block diagram csc_video video yuv graphics gv_pal_bp rgb/yuv vsync current pixel color key and blending logic palette alpha color registers and cursor color values cursor_color_key vid_clr_key location ram cur_color_mask compare compare vid_clr_mask 1 0 0 1 0 1 yuv to rgb csc hsv to rgb csc rgb to hsv saturation control sat_scale_en sat_scale 8 rgb rgb yuv 31:24 1 0 0 1 csc_gfx rgb to yuv csc to vo p 0 1 bypass_stream palette_stream 1 0 vg_ck hd/sd yuv to yuv csc video hd/sd yuv_csc_en csc_vop
396 amd geode? lx processors data book video processor 33234h figure 6-28. color key and alpha-blending logic no ye s ye s no ye s no no ye s no ye s notes: 1) vg_ck: video/graphics color key select (vp memory offset 008h[20]). selects whether graphic data is used for color keying or video data is used for chroma keying. 2) gfx_ins_video: graphics inside video (vp memory offset 098h[8]). graphics inside video enable. 3) graphics [31:24] = 00h: graphics color key match if vg_ck = 1, graphics(31:24) is pixel alpha value. no ye s ye s no no no yes ye s no start cursor color key matches graphics value? pixel inside the video window? use selected cursor color for pixel. use graphics value for this pixel. pixel inside alpha window? video pixel blend graphic values and video values using the alpha value for this window replace the pixel with the color register value value for this pixel use video value for this pixel color register video pixel matches vg_ck = 1? vg_ck = 1? matches chroma color register enabled for this window? ye s use video value for this pixel no ye s ye s chroma key? vg_ck = 1? ye s key? graphics [31:24] = enabled for this window? use graphics value for this pixel use graphics per-pixel alpha blending enabled? no no blend graphic values and video values using the alpha value for this pixel ye s gfx_inx_video = 1? 00h? no graphics[31:24] = 00h?
amd geode? lx processors data book 397 video processor 33234h table 6-60 represents the same logic that is displayed in figure 6-28 on page 396. 6.7.5.2 gamma ram either the graphics or video stream can be routed through an integrated palette ram for gamma-correction of the data stream or (for video data) contrast/brightness adjust- ments. a bypass path is provided for either the graphics or video stream (depending on which is sent through the gamma ram). 6.7.5.3 video proce ssor module display interface the video processor module connects directly to either the internal crt dacs, or provides a standard digital tft interface. 6.7.5.4 video interface the vp uses a two-wire protocol to control the sequence of data on the video port. this protocol consists of vid_val and vid_rdy. vid_val indicates the dc has placed valid data on the 32-bit vid_data bus. vid_rdy indicates the vp is ready to accept video data for the next video source line. the vp typically starts fetching video data five scan lines before the data is required for display. table 6-60. truth table for alpha-blending vg_ck (note 1 ) note 1. vg_ck is bit 20 in the display conf iguration register (vp memory offset 0008h). windows configuration (note 2 ) note 2. gfx_ins_video is bit 8 in the video de-interla cing and alpha control register (vp memory offset 0098h). alphax_color_reg_en are bit 24 in the alpha window colo r registers (vp memory of fsets 0d0h, 0f0h, and 110h). graphics data match cursor color key graphics [31:24] = 00h per-pixel alpha blending enabled video data match normal color key mixer output x (note 3) note 3. x = don?t care. xx yesxxxcursor color x not in video window x no x x x graphic data graphics color key (vg_ck = 0) not in alpha window gfx_ins_video = 0 no yes x x video data no no x x graphic data gfx_ins_video = 1 no x x x video data inside alpha window x alphax_color_reg_en = 1 no yes x x color from color register alphax_color_reg_en = 0 no yes x x video data x no no no x window alpha- blended data x no no yes x per-pixel alpha- blended data video chroma key (vg_ck = 1) not in alpha window gfx_ins_video = 0 no x x yes graphic data no x x no video data gfx_ins_video = 1 no x x x graphic data inside alpha window x alphax_color_reg_en = 1 no x x yes color from color register alphax_color_reg_en = 0 no x x yes graphic data x no x yes no per-pixel alpha- blended data x no x no no window alpha- blended data
398 amd geode? lx processors data book video processor 33234h 6.7.6 video output port 6.7.6.1 functio nal overview the video output port (vop) receives yuv 4:4:4 encoded data from the vp and formats t he data into a video-stream that is bt.656) or bt.601 co mpliant. output from the vop goes to either a vip or a tv encoder. the vop must be bt.656/bt.601 compliant since its output may go directly (or indirectly) to a display. 6.7.6.2 supported features ? vip 2.0 (level i and ii) with vip 1.1 compatibility mode, bt.656 mode supported ? support for vip 2.0 non_int bit (repeat and ext_flag not supported) ? bt.601 mode supported ? vbi data supported (no support for ancillary data) figure 6-29. vop internal block diagram vop registers slave interface 4:4:4 to 4:2:2 converter data from blender vop data formatter crc generator vop data out
amd geode? lx processors data book 399 video processor 33234h 6.7.6.3 hblank and vblank signals hblank and vblank signals are different from hsync and vsync. the hsync and vsync signals are only active for a portion of the blanking time, while the hblank and vblank signals are active through the entire time. hblank is a function of hori zontal pixel position, while vblank is a function of the vertical line number and the horizontal pixel position. figures 6-30 to 6-34 show the for- mation of these signals using a 525-line ntsc video win- dow. figure 6-30. 525-line ntsc video window figure 6-31. hblank and vblank for lines 20-262, 283-524 pixel position line number frame 1 858 525 1 1 v = 1 v = 0 v = 1 v = 0 20 264 283 frame 0 (continued) frame 0 pixel position line number hblank vblank 720 721 858 001 l# l# + 1
400 amd geode? lx processors data book video processor 33234h figure 6-32. hblank and vblank for lines 263, 525 figure 6-33. hblank and vblank for lines 1- 18, 264-281 figure 6-34. hblank and vblank for lines 19, 282 pixel position line number hblank vblank 720 721 858 001 244 245 pixel position line number hblank vblank 720 721 858 001 l# l# + 1 pixel position line number hblank vblank 720 721 858 001 294 001
amd geode? lx processors data book 401 video processor 33234h 6.7.6.4 interface to video processor the output from the video processor is connected via a 24-bit bus. bytes on this bus are aligned as shown below: [23:16] y [15:8] cr (v) [7:0] cb (u) the vop takes this 24-bit 4:4:4 data bus and converts it to a 16-bit 4:2:2 data bus (the y component on the high byte, the u/v components alternating on the low byte). the vop provides three different methods for translating from 4:4:4 to 4:2:2 data depending on the value of the mode select bits from the vop configuration register (vp memory offset 800h[5:4]) as shown in table 6-61. mode 0: 4:2:2 co-sited in this mode, the u/v samples are dropped on alternating sample sets, resulting in the below representation. sampling algorithm: y, u, v : 4:4:4 input data y?, u?, v? : 4:2:2 sampled data y1? = y1, u1? = u1, v1? = v1 y2? = y2 y3? = y3, u3? = u3, v3? = v3 etc. mode 1: 4:2:2 interspersed in this mode, adjacent pairs of u/v sample data are aver- aged, with the u/v samples coming from the same adja- cent sample sets. sampling algorithm: y, u, v : 4:4:4 input data y?, u?, v? : 4:2:2 sampled data y1? = y1, u1? = (u1+u2)/2, v1? = (v1+v2)/2 y2? = y2 y3? = y3, u3? = (u3+u4)/2, v3? = (v3+v4)/2 etc. mode 2: 4:2:2 interspersed (free-running) this mode is the same as mode 1 with the exception that the u sample is averaged between the first two samples, and the v sample is averaged between the second and third samples. sampling algorithm: y, u, v : 4:4:4 input data y?, u?, v? : 4:2:2 sampled data y1? = y1, u1? = (u1+u2)/2 y2? = y2, v2? = (v2+v3)/2 y3? = y3, u3? = (u3+u4)/2 y4? = y4, v3? = (v4+v5)/2 etc. table 6-61. vop mode mode bits description 000 4:2:2 co-sited (recommended) 101 4:2:2 interspersed 210 4:2:2 interspers ed, free-running luminance (y) samples chromance (u,v) samples luminance (y) samples chromance (u,v) samples luminance (y) samples chromance (u) samples chromance (v) samples
402 amd geode? lx processors data book video processor 33234h 6.7.6.5 operating modes bt.656 mode bt.656 is the basic standard that specifies the encoding of the control lines into the data bus. in this mode the sepa- rate control lines are encoded into the data bus as speci- fied by recommendation itu-r bt.656. each line begins with a start of active video (sav) header, and ends with an end of active video (eav) header. each of these are four-byte sequences beginning with ff, 00, 00. the fourth byte of the header provides important infor- mation about this line. the bit format of the sav and eav headers is shown in table 6-62. the t bit is specified in bt.656 as a constant logic 1. the f bit indicates field - 1 for even (also called field 2), 0 for odd (field 1). the v bit indicates vertical blanking. the h bit indicates horizontal blanking. bits p3 through p0 are protection bits used to detect and correct single-bit errors. the bits are defined as follows: p3 = (v + h) + ~t p2 = (f + h) + ~t p1 = (f + v) + ~t p0 = (f + v) + h using the above formulas, the bit values are listed in table 6-63. vip 1.1 compatible mode vip 1.1 compatible mode builds on cbt.656 mode with the following changes/additions: ? video flags t, f, and v can only be changed in the eav code. during vertical blanking there must be a minimum of one sav/eav scan line in order to convey the updated t, f, and v bits. ? task bit is used to indicate vbi data within the video stream (t = 0 for vbi data, t = 1 for active video). ? p3-p0 are ignored. table 6-62. sav/eav sequence parameter d7d6d5d4d3d2d1d0 preamble 11111111 00000000 00000000 status word t f v h p3 p2 p1 p0 table 6-63. protection bit values t f v h p3 p2 p1 p0 hex 000 011 10 0e 000 100 11 13 0 0 1 0 0 1 0 1 25 001 110 00 38 010 010 01 49 010 101 00 54 0 1 1 0 0 0 1 0 62 011 111 11 7f 100 000 00 80 100 111 01 9d 1 0 1 0 1 0 1 1 ab 101 101 10 b6 110 001 11 c7 110 110 10da 1 1 1 0 1 1 0 0 ec 111 100 01 f1
amd geode? lx processors data book 403 video processor 33234h vip 2.0 modes (8 or 16 bits) vip 2.0 mode builds on vip 1.1 with the following changes/ additions: ? video flags t, f, and v are valid in the eav and sav code, valid values must appear no later then the sav of the first scan line of the next active region (see figure 6-35). ? task bit differentiates between two video streams. these streams can be interleaved at a line or field rate. ? new video flags - the p nibble is redefined as [non_int,repeat,rese rved,ext_flag]. ? non_int - 1 = non-interlaced source, 0 = inter- laced source. ? repeat - 1 = repeat field in 3:2 pull-down, 0 = not a repeat field (tied to 0). ? ext_flag - 1 = extra flag byte follows this eav, 0 = no extra flag byte (this flag is always 0). figure 6-35. bt.656 8/16 bit line data f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b c r yyc b c r y eav code sav code 4 horizontal blanking 4 active video start of digital line 4:2:2 sampled video data f f 0 0 0 0 x y eav code f f 0 0 0 0 x y 1 0 1 0 1 0 1 0 1 0 1 0 f f 0 0 0 0 x y yy yyyy y f f 0 0 0 0 x y 8 0 8 0 8 0 8 0 8 0 8 0 c b c b c b c b 8-bit vip data (vip 1.1 and vip 2.0 level i) 16-bit vip data (vip 2.0 level ii) 4 horizontal blanking 4 active video c r c r c r 4 eav code sav code 4:2:2 sampled video data eav code vip_data[7:0] vip_data[7:0] vip_data[15:8]
404 amd geode? lx processors data book video processor 33234h 6.7.6.6 new vip 2.0 video flags four bits are defined (shown in table 6-64) by the vip specification that allow the vip slave to communicate field/ frame-specific information to the graphics chip during the video stream output. these flags are embedded in the lower nibble of the sav or eav header. these video flags allow the graphics chip to handle bob and weave, as well as 3:2 pull-down in hardware. only bit 3 is implemented in the amd geode lx processor. 6.7.6.7 bt.601 support when vop is configured for bt.601 mode, the hsyncs and vsyncs are used to determine the timing of each data line sent out. the sav/eav codes are not used. 6.7.6.8 vip 2.0 level system for even field detection, some devices require a shift in vsync with respect to hsync. this shift is programmed at dc memory offset 080h. also for correct odd/even field shift, vp memory offset 800h[6] = 1. 6.7.6.9 vbi data vertical blanking interval (vbi ) data is not part of the active video (i.e., not directly displayed). this data is sent between fields of active video data during vertical blanking. vbi data has many uses: closed captioning, timecodes, teletext, etc. although there are some specified standards with respect to closed captioning which are generally decoded at the tv, basically, as long as the data is sent and received correctly, there are no restrictions. indication of vbi data is configurable for the different modes. in bt.656 mode, typically the task bit in the eav/sav header is fixed at 1. in this case, there is no indication of vbi data. if the vbi bit in the vop configuration register is set to 1 (vp memory offset 800h[11] = 1), then vbi data will be indicated by a task bi t value of 0 (active video has the value of 1). in vip 1.1 mode, by definition the task bit in the eav/sav header is 0 for vbi data, and 1 for active video. the vbi bit in the vop configuration register has no effect in this mode. in vip 2.0 mode, the task bit value in the eav/sav header is configurable by selecting a value for the task bit in the vop configuration register. if it is desired to have the task bit in the eav/sav header indicate vbi data, then setting the vbi bit will use the inverse value of the task bit in the vop configuration register to indicate vbi data (i.e., if task = 1, then vbi data is indicated by a task bit value of 0 in the eav/sav, if task = 0, then vbi data is indicated by a task bi t value of 1 in the eav/sav). table 6-64. sav vip flags bit flag description 3 non_int 1 indicates that the video is from a non-interlaced source. 0 indi- cates that the video is from an interlaced source. 2 repeat 1 indicates that the current field is a repeat field. this occurs during 3:2 pull-down. this flag enables a vip master to drop the repeat field in the weave mode. this bit is not supported in the amd geode? lx proces- sor (tied to 0). 1 rsvd reserved. 0 ext_flag 0 indicates no extended flags. this bit is not supported in the amd geode lx processor (tied to 0). table 6-65. vop clock rate level video port max. pixclk i 8-bit 75 mhz ii 16-bit 75 mhz
amd geode? lx processors data book 405 video processor 33234h 6.7.7 flat panel display controller 6.7.7.1 fp functional overview the flat panel (fp) display controller converts the digital rgb output of the video mixer block to digital output suit- able for driving a tft flat panel lcd. features include: ? 24-bit color support for digital pixel input. ? 170 mhz pixel clock operation supports up to 1600x1200 tft panels. ? supports most svga tft panels and the vesa fpdi (flat panel display interface) revision 1.0 specification. ? tft panel support provided by use of one connector allows a pass-through mode for the digital pixel input. ? 9-, 12-, 18-, and 24-bit 1 pixel per clock tft support. ? 9+9 or 12+12-bit, and 24-bit 2 pixels per clock tft panel support. ? programmable dither, up to 64 levels. 6.7.7.2 fp architecture overview the fp display controller contains the following functional blocks, as shown in figure 6-36: ? dither engine ? control registers ? tft timing generator ? panel interface ? crc (cyclical redundancy check) engine figure 6-36. flat panel display controller block diagram dither pixel pixel panel panel control registers control data control data engine tft timing generator panel interface crc engine 24 24 24 3 24 7
406 amd geode? lx processors data book video processor 33234h 6.7.7.3 fp functional description the fp connects to the rgb port of the video mixer. lcd interface the fp interfaces directly to industry standard 18-bit or 24- bit active matrix thin-film-tran sistor (tft). the digital rgb or video data that is supplied by the video logic is con- verted into a suitable format to drive a wide variety range of panels with variable bits. the lcd interface includes dith- ering logic to increase the apparent number of colors dis- played for use on panels with less than 6 bits per color. the lcd interface also supports automatic power sequence of panel power supplies. mode selection the fp can be configured for operation with most standard tft panels: ? supports tft panels with up to 24-bit interface with 640x480, 800x600, 1024x768, 1280x1024, and 1600x1200 pixel resolutions. either one or two pixels per clock is supported for all resolutions. other resolutions below 640x480 are also supported. table 6-66 shows the mapping of the data in the supported modes. for tft panel support, the output from the dither block is directly fed on to the panel data pins (drgbx). the data that is being sent on to the panel data pins is in sync with the tft timing signals such as hsync, vsync, and lde. one pixel (or two pixels in 2 pix/clk mode) is shifted on every positive edge of the clock as long as disp_ena is active. table 6-66. panel output signal mapping pin name tft 9-bit tft 18-bit tft 24-bit tft 9+9-bit tft 12+12-bit drgb0 b0 bb0 drgb1 b1 bb0 bb1 drgb2 b0 b2 bb1 bb2 drgb3 b1 b3 bb2 bb3 drgb4 b2 b4 gb0 drgb5 b0 b3 b5 gb0 gb1 drgb6 b1 b4 b6 gb1 gb2 drgb7 b2 b5 b7 gb2 gb3 drgb8 g0 rb0 drgb9 g1 rb0 rb1 drgb10 g0 g2 rb1 rb2 drgb11 g1 g3 rb2 rb3 drgb12 g2 g4 ba0 drgb13 g0 g3 g5 ba0 ba1 drgb14 g1 g4 g6 ba1 ba2 drgb15 g2 g5 g7 ba2 ba3 drgb16 r0 ga0 drgb17 r1 ga0 ga1 drgb18 r0 r2 ga1 ga2 drgb19 r1 r3 ga2 ga3 drgb20 r2 r4 ra0 drgb21 r0 r3 r5 ra0 ra1 drgb22 r1 r4 r6 ra1 ra2 drgb23 r2 r5 r7 ra2 ra3
amd geode? lx processors data book 407 video processor 33234h maximum frequency the fp will operate at a dotclk frequency of up to 170 mhz. there is no minimum frequency; however, many flat panels have signal timings that require minimum frequen- cies. refer to the flat panel display manufacturer?s specifi- cations as appropriate. crc signature the fp contains hardware/logic that performs cyclical redundancy checks (crcs) on the digital video/graphics pipeline. this feature is used for error detection and makes it possible to capture a unique 24-or 32-bit signature for any given mode setup. an error in the video/graphics mem- ory interface, control logic, or pixel pipeline will produce a different signature when compared to a known good signa- ture value. this allows the programmer to quickly and accurately test a video screen without having to visually inspect the screen for errors. by default, a 24-bit signature generator is used. for more accuracy, a 32-bit signature generator my be selected. dithering after the video mixer gamma ram logic, the graphic data or the video data goes through the dithering logic. some panels have limitations of supporting maximum num- ber of bits to display all colo r shades that the crt monitor can support. for example, if the selected mode is 24-bpp and the panel can support only 18-bpp, the remaining two bits for each color is used for dithering to get the desired number of shades as compared to the crt. the idea behind dithering is to achieve intermediate color intensities by allowing the human eye to blend or average the intensities of adjacent pi xels on a screen. intensity res- olution is gained by sacrificing spatial resolution. for example, consider just the red color component of a 2x2 square of pixels. if the only two options for the red color component were to be turned on or off, then there would only be two colors, black and the brightest red. however, if two of the pixels? red color components in the 2x2 square were turned on and two were turned off, the human eye would blend these adjacent pixels and the 2x2 pixel square would appear to be half as bri ght as the brightest red. the drawback is that fine details and boundaries between regions of differing color intensities become slightly blurred. the fp supports dithering patt erns over an 8x8 pixel area. an 8x8 pixel area supports 64 different dithering patterns. this means that the 8-bit input intensity for a given pixel pri- mary color component can be reduced down to its two most significant bits by using the six least significant bits to select a 8x8 pixel pattern whose average intensity is equal to the original 8-bit input intensity value. as an example, consider a display screen that is capable of producing six different intensities of the red color compo- nent for each pixel. given an 8-bit red intensity value, 01010110, the problem is to come up with a 8x8 pixel pat- tern, using only the six availa ble red pixel intensities, that when averaged together, yield the value of the original 8-bit intensity. the values of the six available intensities, padded out to eight bits, are 00000000, 01000000, 01010000, 10000000, 11000000, and 11010000. the given intensity, 010110, lies between 01000000 and 10000000, so these two intensities are used in the 8x8 pixel pattern, as shown in figure 6-37 on page 408. the average intensity of this 8x8 pattern is 01010110. the actual dithering pattern is an 8x8 pattern of 1s and 0s. a 0 in a given position of the pattern indicates that the trun- cated value of the input color component intensity be used. a 1 means use the next higher truncated value. in the pre- vious example, the intensity value was 01010110, the trun- cated value is 01000000 (least significant six bits set to 0), and the next higher truncated value is 10000000. the 8x8 dithering pattern for an input intensity value whose least significant six bits are al ready zero is made up of all 0s. this means that the next higher truncated intensity value is never used because the input intensity value is the same as its truncated value. as the value of the least signif- icant six bits of the input intensity value increases, the input intensity value gets closer to the next higher truncated intensity value, and more 1s are added to the pattern. for example, when the value of the least significant six bits of the input intensity value is 16, there will be sixteen 1s in the dithering pattern and the next higher truncated intensity value will be used sixteen times within the 8x8 pattern. dotclk clk clk clk clk clk hsync hsync hsync hsync hsync hsync vsync vsync vsync vsync vsync vsync ldemod lde lde lde lde lde vdden enlvdd enlvdd enlvdd enlvdd enlvdd table 6-66. panel output signal mapping (continued) pin name tft 9-bit tft 18-bit tft 24-bit tft 9+9-bit tft 12+12-bit
408 amd geode? lx processors data book video processor 33234h figure 6-37. dithered 8x8 pixel pattern all discussions to this point have referred to a 6-bit dither- ing scheme. a 6-bit dithering scheme is one in which the least significant six bits of the input intensity value for each pixel color component are truncated and these least signifi- cant six bits are used to select an 8x8 dithering pattern. the fp also supports 4-, 3-, 2-, and 1-bit dithering schemes. in the 4-bit dithering scheme, only the least sig- nificant four bits of the input intensity value for each color component are truncated. as th e value of the least signifi- cant four bits increases from 0 to 15, the order in which 1s are added to the dithering is much the same as in a 6-bit scheme except that two 1s are added to the pattern for each increment of the 4-bit value. the 3-bit dithering scheme selects a dithering pattern based on the least significant th ree bits of the input inten- sity value for each color component. the order in which 1s are added to the dithering pattern as the value of these two bits increases from 0 to 7 is the same as the order for the 6-bit scheme except that two 1s are added to the pattern for each increment of the 3-bit value. the 2-bit dithering scheme selects a dithering pattern based on the least significant tw o bits of the input intensity value for each color component. the order in which 1s are added to the dithering pattern as the value of these two bits increases from 0 to 3 is the same as the order for the 6-bit scheme except that four 1s are added to the pattern for each increment of the 2-bit value. the 1-bit dithering scheme uses the least significant bit of the input intensity value to se lect one of two dithering pat- terns. the order that 1s are added to the dithering pattern is the same as the 6-bit schem e except that eight 1s are added to the pattern when the least significant bit is a 1. when the least significant bit is 0, the pattern is all 0s. when the least significant bit is 1, the pattern is alternating 0s and 1s. figure 6-38 on page 409 shows the suggested order for adding 1s to the dithering patterns for the 4-, 3-, 2-, and 1- bit dithering schemes. x-count[3:0] y-count[3:0] 10000000 10000000 01000000 01000000 01000000 01000000 10000000 01000000 01000000 01000000 01000000 01000000 10000000 10000000 01000000 01000000 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 10000000 10000000 01000000 01000000 01000000 01000000 01000000 01000000 01000000 01000000 01000000 01000000 10000000 10000000 01000000 01000000 01000000 10000000 01000000 01000000 01000000 01000000 01000000 01000000 01000000 10000000 10000000 10000000 01000000 01000000 10000000 10000000 01000000 01000000 01000000 01000000 01000000 01000000 01000000 01000000 10000000 10000000 01000000 01000000 01000000 01000000 01000000 01000000
amd geode? lx processors data book 409 video processor 33234h figure 6-38. n-bit dithering pattern schemes 15 13 14 12 000 001 010 011 100 111 101 110 000 001 010 011 100 111 101 110 75 3111 9 46 8210 15 13 14 12 75 3111 9 46 8210 15 13 14 12 75 46 8210 15 13 14 12 75 46 8210 3111931119 x-count[3:0] y-count [3:0] 12 1 2 000 001 010 011 100 111 101 110 000 001 010 011 100 111 101 110 56 73 4 65 473 12 1 2 56 73 4 65 473 12 1 2 56 65 473 12 1 2 56 65 473 73 473 4 x-count[3:0] y-count [3:0] 33 3 3 000 001 010 011 100 111 101 110 000 001 010 011 100 111 101 110 11 22 11 22 33 3 3 11 22 11 22 33 3 3 11 11 22 33 3 3 11 11 22 2222 x-count[3:0] y-count [3:0] 11 1 1 000 001 010 011 100 111 101 110 000 001 010 011 100 111 101 110 11 11 11 1 1 11 11 11 1 1 11 11 1 1 11 1114 x-count[3:0] y-count [3:0] 4-bit scheme 3-bit scheme 2-bit scheme 1-bit scheme
410 amd geode? lx processors data book video processor 33234h crc signature the fp contains hardware/logic that performs cyclical redundancy checks (crcs) on the panel data digital pipe- line. this feature is used for error detection and makes it possible to capture a unique 24- or 32-bit signature for any given mode setup. an error in the dither pixel pipeline pro- duces a different signature when compared to a known good signature value. the dither data path can be config- ured in two basic modes: dither enable and dither disable by programming the denb bit (fp memory offset 418h[0]). this allows the programmer to quickly and accurately test a video screen without having to visually inspect the screen for errors. table 6-67 shows the bit settings that provide this feature. panel selection is done through fp memory offset 408h[18:16]. the selection of thes e bits results in two func- tions. 1) generates the desired pa nel clk from the pixel clock based on the panel type selected. 2) steers the internal pixel bus on to the panel interface data pins. all the unused pins are driven with 0s. this panel data is sent to the crc signature generator. the crc number varies for each panel configuration for a fixed on-screen image. addressing the dithering memories the least significant four bits of each color component intensity value are used to select a 4x4 dithering pattern. in other words, there are 16 diff erent 16-bit dithering patterns for each color component (red, green, and blue). this requires one 256x1-bit memory for each color component. the address to one of these dithering pattern memories is then eight bits in length. the bit address for dithering memory is defined as the con- catenation of: 1) the least significant two bits of the display screen hori- zontal position pixel count 2) the least significant two bits of the display screen vertical position pixel count 3) the least significant four bits of the input intensity value this concatenation is as shown below: the fp gliu interface programs the red, green, and blue dither memories individually, or all at once. writing to all three dither memories at the same time means that the dithering patterns are the same for each of the three color components. table 6-67. register settings for dither enable/ disable feature dither enable for tft bypass dither for tft bypass fp fp memory offset 418h[6:0] 000,001,1 001,010,1 010,011,1 011,100,1 100,101,1 101,xxx,x fp memory offset 418h[6:0] 101,xxx,x fp memory offset 408h[30] is set to 1 dithering memory bit address[7:0] = {x-count[1:0], y-count[1:0], intensity[3:0]}
amd geode? lx processors data book 411 video processor 33234h 6.7.8 vp resolution table supported crt and flat panel resolutions of the vp are provided in table 6-32 on page 281. all resolutions can be up to 8 bits per color, or 24 bits per pixel. in general, all dis- play resolutions contained in vesa monitor timing specifi- cations version 1.0 v0.8 are supported for crt. flat panels up to 1600x1200x60 are supported. for those resolutions not listed in the vesa specification, the maximum dot clock frequency is 340 mhz for crt and 170 mhz for tft. all sdtv and hdtv resolutions are also supported 6.7.9 display rgb modes mode overview: 1) crt: normal functional, crt display. 2) tft online: normal functional, tft display. 3) crt legacy rgb: use companion device as off-chip display controller, graphics only for crt. 4) tft legacy rgb: use the amd geode companion device as off-chip display controller, graphics only for crt. 5) crt debug: normal functional, access to debug sig- nals. the dbg signals are driven on the specified pins outside the vp module, listed here for information only. 6) tft legacy rgb debug: use companion device as off-chip display controller, reduced graphics only for crt, access to debug signals. the dbg signals are driven on the specified pins outside the vp module, listed here for information only. 7) vop: normal function table 6-68. display rgb modes pin crt 1 tft online 2 crt legacy rgb 3 tft legacy rgb 4 crt debug 5 tft legacy rgb debug 6 vop 7 drgb23 0 tft23 r7 r7 dbg15 dbg15 0 drgb22 0 tft22 r6 r6 dbg14 dbg14 0 drgb21 0 tft21 r5 r5 dbg13 dbg13 0 drgb20 0 tft20 r4 r4 dbg12 dbg12 0 drgb19 0 tft19 r3 r3 dbg11 dbg11 0 drgb18 0 tft18 0 r2 0 r7 0 drgb17 0 tft17 0 r1 0 r6 0 drgb16 0 tft16 0 r0 0 r5 0 drgb15 0 tft15 g7 g7 dbg10 dbg10 vop8 drgb14 0 tft14 g6 g6 dbg09 dbg09 vop9 drgb13 0 tft13 g5 g5 dbg08 dbg08 vop10 drgb12 0 tft12 g4 g4 dbg07 dbg07 vop11 drgb11 0 tft11 g3 g3 dbg06 dbg06 vop12 drgb10 0 tft10 g2 g2 dbg05 dbg05 vop13 drgb9 0 tft9 0 g1 0 g7 vop14 drgb8 0 tft8 0 g0 0 g6 vop15 drgb7 0 tft7 b7 b7 dbg04 dbg04 vop0 drgb6 0 tft6 b6 b6 dbg03 dbg03 vop1 drgb5 0 tft5 b5 b5 dbg02 dbg02 vop2 drgb4 0 tft4 b4 b4 dbg01 dbg01 vop3 drgb3 0 tft3 b3 b3 dbg00 dbg00 vop4 drgb2 0 tft2 0 b2 0 g5 vop5 drgb1 0 tft1 0 b1 0 b7 vop6 drgb0 0 tft0 0 b0 0 b6 vop7 dotclk 0 fp_shfclk df_dot_clk df_dot_clk dbg_clk df_dot_clk vopclk hsync vp_hsync fp_hsync vg_hsyn c vg_hsync vp_hsync vg_hsync 0 vsync vp_vsync fp_vsync vg_vsync vg_vsync vp_vsync vg_vsync 0 dispen 0 bklen 0 vg_disp_en 0 vg_disp_en 0 vdden 0 fp_vdden 0 0 0 0 0 ldemod 0 fp_lde 0 0 0 0 0
412 amd geode? lx processors data book video processor register descriptions 33234h 6.8 video processor re gister descriptions this section provides information on the registers associ- ated with the video processor: standard geodelink device (gld) and video processor specific msrs (accessed via the rdmsr and wrmsr instructions), and two blocks of functional memory mapped registers (video processor and flat panel). table 6-75 through table 6-78 are register summary tables that include reset values and page references where the bit descriptions are provided. note: the msr address is derived from the perspective of the cpu core. see section 4.1 "msr set" on page 45 for more details on msr addressing. for memory offset mapping details, see section 4.1.3 "memory and i/o m apping" on page 47. table 6-69. standard geodelink? device msrs summary msr address type register name reset value reference 48002000h ro gld capabilities msr (gld_msr_cap) 00000000_0013f0xxh page 415 48002001h r/w gld master configuration msr (gld_msr_config) 00000000_00040e00h page 415 48002002h r/w gld smi msr (gld_msr_smi) 00000000_00000000h page 417 48002003h r/w gld error msr (gld_msr_error) 00000000_00000000h page 417 48002004h r/w gld power management msr (gld_msr_pm) 00000000_00000555h page 418 48002005h r/w gld diagnostic msr (gld_msr_diag) 00000002_00000000h page 418 table 6-70. video processor module specific msrs summary msr address type register name reset value reference 48002010h r/w vp diagnostic msr (msr_diag_vp) 00000000_00000000h page 419 48002011h r/w pad select msr (msr_padsel) 00000000_00000000h page 420 table 6-71. video processor module configuration control registers summary vp memory offset type register name reset value reference video processor 000h r/w video configuration (vcfg) 00000000_00000000h page 421 008h r/w display configuration (dcfg) 00000000_00000000h page 422 010h r/w video x position (vx) 00000000_00000000h page 424 018h r/w video y position (vy) 00000000_00000000h page 425 020h r/w video scale (scl) 00000000_00000000h page 425 028h r/w video color key register (vck) 00000000_00000000h page 426 030h r/w video color mask (vcm) 00000000_00000000h page 427 038h r/w palette address (par) 00000000_000000xxh page 428 040h r/w palette data (pdr) 00000000_00xxxxxxh page 428 048h r/w saturation scale (slr) 00000000_00000000h page 429
amd geode? lx processors data book 413 video processor register descriptions 33234h 050h r/w miscellaneous (misc) 00000000_00000c00h page 430 058h r/w crt clock select (ccs) 00000000_00000000h page 431 060h r/w video y scale (vys) 00000000_00000000h page 431 068h r/w video x scale (vxs) 00000000_00000000h page 431 070h -- reserved (rsvd) -- -- 078h r/w video downscaler control (vdc) 00000000_00000000h page 432 080h -- reserved -- -- 088h r/w crc signature (crc) 00000000_00000000h page 433 090h ro 32-bit crc signature (crc32) 00000000_00000001h page 434 098h r/w video de-interlacing and alpha control (vde) 00000000_00000400h page 434 0a0h r/w cursor color key (cck) 00000000_00000000h page 436 0a8h r/w cursor color mask (ccm) 00000000_00000000h page 437 0b0h r/w cursor color 1 (cc1) 00000000_00000000h page 437 0b8h r/w cursor color 2 (cc2) 00000000_00000000h page 438 0c0h r/w alpha window 1 x position (a1x) 00000000_00000000h page 438 0c8h r/w alpha window 1 y position (a1y) 00000000_00000000h page 439 0d0h r/w alpha window 1 color (a1c) 00000000_00000000h page 439 0d8h r/w alpha window 1 control (a1t) 00000000_00000000h page 440 0e0h r/w alpha window 2 x position (a2x) 00000000_00000000h page 441 0e8h r/w alpha window 2 y position (a2y) 00000000_00000000h page 442 0f0h r/w alpha window 2 color (ac2) 00000000_00000000h page 442 0f8h r/w alpha window 2 control (a2t) 00000000_00000000h page 443 100h r/w alpha window 3 x position (a3x) 00000000_00000000h page 444 108h r/w alpha window 3 y position (a3y) 00000000_00000000h page 445 110h r/w alpha window 3 color (a3c) 00000000_00000000h page 445 118h r/w alpha window 3 control (a3t) 00000000_00000000h page 446 120h r/w video request (vrr) 00000000_001b0017h page 447 128h ro alpha watch (awt) 00000000_00000000h page 448 130h r/w video processor test mode (vtm) 00000000_00000000h page 448 138h r/w even video y position (vye) 00000000_00000000h page 449 140h r/w even alpha window 1 y position (a1ye) 00000000_00000000h page 449 148h r/w even alpha window 2 y position (a2ye) 00000000_00000000h page 450 150h r/w even alpha window 3 y position (a3ye) 00000000_00000000h page 450 158h-3ffh -- reserved -- -- table 6-71. video processor module configuration control registers summary (continued) vp memory offset type register name reset value reference
414 amd geode? lx processors data book video processor register descriptions 33234h flat panel 400h r/w panel timing register 1 (pt1) 00000000_00000000h page 451 408h r/w panel timing register 2 (pt2) 00000000_00000000h page 453 410h r/w power management (pm) 00000000_00000002h page 454 418h r/w dither and frame rate control (dfc) 00000000_00000000h page 456 420h -- reserved -- -- 428h -- reserved -- -- 430h -- reserved -- -- 438h -- reserved -- -- 440h -- reserved -- -- 448h r/w dither ram control and address (dca) 00000000_00000000h page 457 450h r/w dither memory data (dmd) 00000000_00000000h page 458 458h r/w panel crc signature (crc) 00000000_00000000h page 458 460h -- reserved -- -- 468h ro 32-bit panel crc (crc32) 00000000_00000001h page 459 video output port (vop) 800h r/w video output port configuration (vop_config) 00000000_00000000h page 459 808h ro video output port signature (vop_sig) 00000000_00000000h page 461 810h-8ffh -- reserved -- -- 1000h- 1fffh r/w video coefficient ram (vcr) xxxxxxxx_xxxxxxxxh page 451 table 6-71. video processor module configuration control registers summary (continued) vp memory offset type register name reset value reference
amd geode? lx processors data book 415 video processor register descriptions 33234h 6.8.1 standard geodelink? device msrs 6.8.1.1 gld capabilities msr (gld_msr_cap) 6.8.1.2 gld master configur ation msr (gld_msr_config) msr address 48002000h ty p e r o reset value 00000000_0013f0xxh gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. reads back as 0. 23:8 dev_id device id. identifies device (13f0h). 7:0 rev_id revision id. identifies device revision. see amd geode? lx processors specification update document for value. msr address 48002001h ty p e r / w reset value 00000000_00040e00h gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 sp vidpri mskcs gpri fpc iuv div fmtbo fmt pid gld_msr_config bit descriptions bit name description 63:32 rsvd (ro) reserved (read only). reads back as 0. 31:21 sp spares. bits are read/write, but have no function. 20 vidpri video priority. sets the video priority level to the video generator. if this bit is set the video stream will be put in high priority mode. 19 mskcs mask palette chip select fix. if this bit is set, the fix for the chip select bug in the pal- ette ram is inactivated and the chip select remains active if the bypass both is not set. if this bit is clear, then the chip select is throttled on individual accesses to the ram. 18:16 gpri gliu master priority. 000 in this field sets the video processor module at the lowest gliu priority and 111 sets the video processor module at the highest gliu priority.
416 amd geode? lx processors data book video processor register descriptions 33234h 15 fpc simultaneous flat panel (or vop) and crt. primary display is flat panel. setting this bit activates the crt dac interface to allow simultaneous display of both panel and crt. leaving this bit reset forces the crt dac signals to zero. this bit is ignored if bits [5:3] of this register are set to 0 or 4. 14 iuv interchange uv. interchange byte order of the u and v bytes (see bits [7:6]). this applies only to drgb mode (see bits [5:3]). 13:8 div clock divider. gliu clock divider to produce 14.3 mhz reference clock. result must be equal to or less than 14.3 mhz. gliu clock speed/div = reference clock. 7:6 fmtbo format byte order. the lower 24 bits of the drgb output bus byte order can be modi- fied for any required interface. these bits, along with bit 14, are used to output the follow- ing combinations of byte order. this applies only to drgb mode. 000 = rgb / yuv (yc b c r ) 001 = bgr / vuy (c r c b y) 010 = bgr / vyu (c r yc b ) 011 = brg / vuy (c r c b y) 100 = rgb / yvu (yc r c b ) 101 = bgr / vyu (c r yc b ) 110 = bgr / vuy (c r c b y) 111 = brg / vyu (c r yc b ) 5:3 fmt vp output format select. video processor module display outputs formatted for crt or flat panel. resets to crt; software mu st change if a different mode is required. 000: crt. 001: flat panel. 010: reserved. 011: reserved. 100: crt debug mode. 101: reserved. 110: vop. 111: drgb. 2:0 pid vp priority domain. video processor module assigned priority domain identifier. gld_msr_config bit descriptions (continued) bit name description
amd geode? lx processors data book 417 video processor register descriptions 33234h 6.8.1.3 gld smi msr (gld_msr_smi) the video processor does not produce smi interrupts, therefore this register is not used. always write 0. 6.8.1.4 gld error msr (gld_msr_error) msr address 48002002h ty p e r / w reset value 00000000_00000000h msr address 48002003h ty p e r / w reset value 00000000_00000000h gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd e 313029282726252423222120191817161514131211109876543210 rsvd em gld_msr_error bit descriptions bit name description 63:33 rsvd (ro) reserved (read only). reads back as 0. 32 e vp error status. any gliu request made of an unsupported function type causes this bit to be set by the hardware. writing a 1 to this bit clears the status. bit 0 must be 0 for the error to be generated. 0: error not pending. 1: error pending. 31:1 rsvd (ro) reserved (read only). 0em df error mask. 0: unmask the error (i.e., error generation is enabled). 1: mask the error (i.e., error generation is disabled).
418 amd geode? lx processors data book video processor register descriptions 33234h 6.8.1.5 gld power management msr (gld_msr_pm) 6.8.1.6 gld diagnostic msr (gld_msr_diag) this register is reserved for internal use by amd and should not be written to. msr address 48002004h ty p e r / w reset value 00000000_00000555h gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd sp rsvd pmd5 rsvd pmd4 rsvd pmd3 rsvd pmd2 rsvd pmd1 rsvd pmd0 gld_msr_pm bit descriptions bit name description 63:28 rsvd reserved. 27:24 sp spare. read/write, no function. 23:11 rsvd reserved. 10 pmd5 vop 2x dot clock power mode. 0: disable clock gating. clocks are always on. 1: enable active hardware clock gating. 9 rsvd reserved. 8pmd4 vp video dot clock power mode. 0: disable clock gating. clocks are always on. 1: enable active hardware clock gating. 7 rsvd reserved. 6pmd3 fp dot clock power mode. 0: disable clock gating. clocks are always on. 1: enable active hardware clock gating. 5 rsvd reserved. 4pmd2 fp gliu clock power mode. 0: disable clock gating. clocks are always on. 1: enable active hardware clock gating. 3 rsvd reserved. 2pmd1 vp graphics dot clock power mode. 0: disable clock gating. clocks are always on. 1: enable active hardware clock gating. 1 rsvd reserved. 0pmd0 vp gliu clock power mode. 0: disable clock gating. clocks are always on. 1: enable active hardware clock gating. msr address 48002005h ty p e r / w reset value 00000002_00000000h
amd geode? lx processors data book 419 video processor register descriptions 33234h 6.8.2 video processor module specific msrs 6.8.2.1 vp diagnostic msr (msr_diag_vp) msr address 48002010h ty p e r / w reset value 00000000_00000000h msr_diag_vp register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 cm ndm sm dval d tsel sp msr_diag_vp bit descriptions bit name description 63:32 rsvd reserved. 31 cm 32-bit crc mode. selects 32-bit crc generation. 0: disable. 1: enable. 30 ndm new dither mode. selects either the legacy dither mode, or new dither mode. the legacy dither mode has an errata with the first pixel. the new dither mode fixes this errata. this bit provided for backward compatibility. 0: legacy dither mode. 1: new dither mode. 29:28 sm sim mode. this field is used to put the vp in modes to aid verification. 00: normal operation. 01: graphics input bypasses vp and goes directly to fp. 10: reserved. 11: reserved. 27:20 dval dac test value. 8-bit data value to drive to crt dac when selected by bit 19. dupli- cate copies of dac test value are driven on dac rgb. crt_dac_r[7:0] = dac test value[7: 0] ([27:20] is this register) crt_dac_g[7:0] = dac test value[7:0] ([27:20] is this register) crt_dac_b[7:0] = dac test value[7:0] ([27:20] is this register) to enable dac test value to be driven to crt dac: (dac test value select must = 0) and ((vtm[6] = 0 and mbd_msr_diag[18:16] = 101h) or (vtm[6] = 1 and vtm[3:0] = 0001h) 19 d dac test value select. selects which data stream is sent to crt dac during crt dac test mode. 0: 24-bit data to crt dac = {3{dac test va lue[27:20]}} (3 time repeated 8-bit value). 1: 24-bit data to crt dac = gfx_data[23: 0] (raw input from display controller). 18:16 rsvd reserved. reserved for test purposes. set to 000 for normal operation. 15:0 sp spares. read/write, no function.
420 amd geode? lx processors data book video processor register descriptions 33234h 6.8.2.2 pad select msr (msr_padsel) msr address 48002011h ty p e r / w reset value 00000000_00000000h msr_padsel register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd vopcinv rsvd df_drgb[31:26] 313029282726252423222120191817161514131211109876543210 df_drgb[25:24] rsvd df_dclk df_disp_en df_lde df_vsync df_hsync df_drgb[23:0] msr_padsel bit descriptions bit name description 63:40 rsvd reserved. 39 vopcinv invert vop clock. this is used to invert the vop output clock. this may be used to meet system timing requirements. 0: non-inverted. 1: inverted. 38 rsvd reserved. 37:0 pads select for registered or non-registered vp outputs. bits select whether to use the registers in the pad logic. the reset value of 38?b0 is valid for tft 2 pixel per clock and crt mode. bits [37:30]: df_drgb[31:24] 0: registered output. 1: direct output. bit 29: rsvd. always write 0. bit 28: df_dclk bit 27: df_disp_en bit 26: df_lde bit 25: df_vsync bit 24: df_hsync bits [23:0]: df_drgb[23:0] 0: registered output. 1: direct output.
amd geode? lx processors data book 421 video processor register descriptions 33234h 6.8.3 video processor module c ontrol/configuration registers 6.8.3.1 video conf iguration (vcfg) vp memory offset 000h ty p e r / w reset value 00000000_00000000h vcfg register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd en_420 bit_8_line_size bit_9_line_size sp init_rd_ln_size init_rd_addr vid_lin_siz sp sc_byp rsvd vid_fmt rsvd vid_en vcfg bit descriptions bit name description 63:29 rsvd (ro) reserved (read only). reads back as 0. 28 en_420 enable 4:2:0 format. 0: disable. 1: enable. note: when the input video stream is rgb, this bit must be set to 0. 27 bit_8_ line_size bit 8 line size. when enabled, this bit increases line size from vid_lin_siz (bits [15:8]) dwords by adding 256 dwords. 0: disable. 1: enable. 26 bit_9_ line_size bit 9 line size. when enabled, this bit increases line size from {bit_8_line_size, vid_lin_siz (bits [15:8])} dwords by adding 512 dwords. 0: disable. 1: enable. 25 sp spare. bit is r/w but has no function. 24 init_rd_ ln_size increase initial buffer read address. increases init_rd_addr (bits [23:16]) by add- ing 256 dwords to the initial buffer addr ess. (effectively init_rd_addr becomes 9 bits (bits [24:16]) of address to the line buffers. each line buffer location contains 4 pixels. therefore init_rd_addr is restricted to 4 pixel resolution.) if sub-4 pixel start is desired, use the vp memory offset 010h[11:0]. 0: disable. 1: enable. 23:16 init_rd_addr initial buffer read address. this field preloads the starting read address for the line buffers at the beginning of each display line. it is used for hardware clipping of the video window at the left edge of the active display. since each line buffer contains 4 pixels, init_rd_addr is restricted to 4 pixel resolution. for an unclipped window, this value should be 0. for 420 mode, set bits [17:16] to 00. 15:8 vid_lin_siz video line size (in dwords). represents the number of dwords that make up the horizontal size of the source video data. 7:6 sp spares. bits are r/w but have not function.
422 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.2 display configuration (dcfg) 5 sc_byp scaler bypass. bypass scaling math functions. should only be used for non-scaled video outputs. scale factors set to 10000h. 0: scaler enabled. 1: scaler disabled. 4 rsvd (ro) reserved (read only). reads back as 0. 3:2 vid_fmt video format. byte ordering of video data on the video input bus. the interpretation of these bits depends on the settings for bit 28 (en_420) and bit 13 (gv_sel) of the vde register (vp memory offset 098h). if gv_sel and en_420 are both set to 0 (4:2:2): 00: cb y0 cr y1 01: y1 cr y0 cb 10: y0 cb y1 cr 11: y0 cr y1 cb if gv_sel is set to 0 and en_420 is set to 1 (4:2:0): 00: y0 y1 y2 y3 01: y3 y2 y1 y0 10: y1 y0 y3 y2 11: y1 y2 y3 y0 if gv_sel is set to 1 and en_420 is set to 0 (5:6:5): 00: p1l p1m p2l p2m 01: p2m p2l p1m p1l 10: p1m p1l p2m p2l 11: p1m p2l p2m p1l both rgb 5:6:5 and yuv 4:2:2 contain two pixels in each 32-bit dword. yuv 4:2:0 contains a stream of y data fo r each line, followed by u and v data for that same line. cb = u, cr = v. 1 rsvd (ro) reserved (read only). reads back as 0. 0vid_en video enable. enables video acceleration hardware. 0: disable (reset) video module. 1: enable. vp memory offset 008h ty p e r / w reset value 00000000_00000000h vcfg bit descriptions (continued) bit name description dcfg register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 sp rsvd dac_vref rsvd gv_gam vg_ck rsvd crt_sync_skw sp crt_vsync_pol crt_hsync_pol rsvd sp dac_bl_en vsync_en hsync_en crt_en
amd geode? lx processors data book 423 video processor register descriptions 33234h dcfg bit descriptions bit name description 63:32 rsvd (ro) reserved (read only). reads back as 0. 31:28 sp spares. bits are read/write, but have no function. 27 rsvd (ro) reserved (read only). reads back as 0. 26 dac_vref select crt dac vref. allows use of an external voltage reference for crt dac. 0: disable external vref. 1: use external vref. 25:22 rsvd (ro) reserved (read only). reads back as 0. 21 gv_gam graphics/video gamma. selects whether the graphic or video data should pass through the gamma correction ram. 0: graphic data passes through the gamma correction ram. 1: video data passes through the gamma correction ram. 20 vg_ck video/graphics color key select. selects whether the graphic data is used for color- keying or the video data is used for chroma-key ing. note that this affects the final output with or without blending enabled. see figure 6-31 on page 438 and table 6-64 on page 439 for details. 0: graphic data is compared to the color key. 1: video data is compared to the chroma key. 19:17 rsvd (ro) reserved (read only). reads back as 0. 16:14 crt_sync _skw crt sync skew. represents the number of pixel clocks to skew the horizontal and ver- tical sync that are sent to the crt. this field should be programmed to 100 (i.e., baseline sync is not moved) as the baseline. via this register, the sync can be moved forward (later) or backward (earlier) relative to the pixel data. this register can be used to com- pensate for possible delay of pixel data being processed via the video processor. 000: sync moved 4 clocks backward. 001: sync moved 3 clocks backward. 010: sync moved 2 clocks backward. 011: sync moved 1 clock backward. 100: baseline sync is not moved. (default) 101: sync moved 1 clock forward. 110: sync moved 2 clocks forward. 111: sync moved 3 clocks forward. 13:10 sp spares. bits are read/write, but have no function. 9 crt_vsync _pol crt vertical synchronization polarity. selects the polarity for crt vertical sync. 0: crt vertical sync is normally low and is set high during the sync interval. 1: crt vertical sync is normally high and is set low during the sync interval 8crt_hsync _pol crt horizontal synchronization polarity. selects the polarity for crt horizontal sync. 0: crt horizontal sync is normally low and is set high during sync interval. 1: crt horizontal sync is normally high and is set low during sync interval. 7:6 rsvd (ro) reserved (read only). reads back as 0. 5:4 sp spares. bits are read/write, but have no function. 3 dac_bl_en dac blank enable. controls blanking of the crt dacs. 0: dacs are constantly blanked. 1: dacs are blanked normally (i.e., during horizontal and vertical blank).
424 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.3 video x position (vx) 2 vsync_en crt vertical sync enable. enables/disables crt vertical sync (used for vesa dpms support). 0: disable. 1: enable. 1 hsync_en crt horizontal sync enable. enables/disables crt horizontal sync (used for vesa dpms support). 0: disable. 1: enable. 0crt_en crt enable. enables the graphics display control logic. this bit is also used to reset the display logic. 0: reset display control logic. 1: enable display control logic. vp memory offset 010h ty p e r / w reset value 00000000_00000000h dcfg bit descriptions (continued) bit name description vx register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd vid_x_end rsvd vid_x_start vx bit descriptions bit name description 63:28 rsvd (ro) reserved (read only). reads back as 0. 27:16 vid_x_end video x end position. represents the horizontal end pos ition of the video window. this register is programmed relative to crt hor izontal sync input (not the physical screen position). this value is calculated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 13. (note 1) 15:12 rsvd (ro) reserved (read only). reads back as 0. 11:0 vid_x_start video x start position. represents the horizontal start position of the video window. this value is calculated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 14. (note 1) note 1. h_total and h_sync_end are the values writ ten in the display controller module registers.
amd geode? lx processors data book 425 video processor register descriptions 33234h 6.8.3.4 video y position (vy) 6.8.3.5 video scale (scl) vp memory offset 018h ty p e r / w reset value 00000000_00000000h vy register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd vid_y_end rsvd vid_y_start vy bit descriptions bit name description 63:27 rsvd (ro) reserved (read only). reads back as 0. 26:16 vid_y_end video y end position. represents the vertical end position of the video window. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 2. (note 1) 15:11 rsvd (ro) reserved (read only). reads back as 0. 10:0 vid_y_start video y start position. represents the vertical start position of the video window. this register is programmed relative to crt ve rtical sync input (not the physical screen posi- tion). this value is calculated according to the following formula: value = desired screen position + (v_t otal ? v_sync_end) + 1. (note 1) note 1. v_total and v_sync_end are the values wri tten in the display controller module registers. vp memory offset 020h ty p e r / w reset value 00000000_00000000h scl register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 gp gb rsvd sp dhd coed lps sp vsl scl bit descriptions bit name description 63:32 rsvd (ro) reserved (read only). reads back as 0. 31 gp (ro) gliu passed (read only). this bit set indica tes the gliu line buffer fill has been passed by the dot display. screen display tearing might occur. this bit clears on read. this bit is typically set if during vertical downscale, the 2nd line buffer fill hasn?t started before the dot display has started. this indicates an error in that the gliu line buffer fill can?t keep up with the dot clock display rate.
426 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.6 video color key register (vck) 30 gb (ro) gliu behind (read only). this bit set indicates the gliu line buffer fill is falling behind the dot display. this bit clears on read. this bit is typically set if during vertical downscale, the 2nd line buffer fill has not com- pleted before the dot display has started. this does not necessarily indicate an error, recovery is possible. 29:16 rsvd reserved. 15 sp spare. bit is r/w but has no function. 14 dhd double horizontal downscale. selects which method data gets written into line buffers. 0: write data from video interface directly. 1: write data from video interface averaged each 2 pixels. this bit should only be set when horizontal downscale greater than 4:1 is desired. 13 coed coefficient mode. selects between 128 and 256 coefficient usage. 0: use common 256 ver t/horz coefficient table. 1: use separate 128 vert/ horz coefficient tables. when using separate tables, the vertical coefficient should be placed in the lower half of the coefficient ram (0-127 = ve rtical 128-255 = horizontal). 12 lps last pixel select. selects method to choose last pixel for the scaler to use. 0: use video source line size. 1: use video window size. the preferred setting is 0. this will avoid unnecessary horizontal mirroring. 11 sp spare. bit is r/w but has no function. 10:0 vsl video source lines. represents the total number of video source lines. for example, a 720x480 video image would have vsl = 480. vp memory offset 028h ty p e r / w reset value 00000000_00000000h scl bit descriptions bit name description vck register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd vid_clr_key vck bit descriptions bit name description 63:24 rsvd (ro) reserved (read only). reads back as 0.
amd geode? lx processors data book 427 video processor register descriptions 33234h 6.8.3.7 video co lor mask (vcm) 23:0 vid_clr_key video color key. the video color key is a 24-bit rgb or yuv value. ? if vg_ck (vp memory offset 008h[20]) is se t to 0, the video pixel is selected within the target window if the corresponding graphics pixel matches the color key. the color key is an rgb value. ? if vg_ck (vp memory offset 008h[20]) is se t to 1, the video pixel is selected within the target window only if it (the video pixel) does not match the color key. the color key is usually an rgb value. however, if both gv_sel and csc_video (vp memory offset 098[13,10] are set to 0, the color key is a yuv value (i.e., video is not converted to rgb). the graphics or video data being compared can be masked prior to the compare via the video color mask register (vp memory offset 030h). the video color key can be used to allow irregular shaped overlays of graphics onto video, or video onto graphics, within a scaled video window. vp memory offset 030h ty p e r / w reset value 00000000_00000000h vck bit descriptions (continued) bit name description vcm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd vid_clr_mask vcm bit descriptions bit name description 63:24 rsvd (ro) reserved (read only). reads back as 0. 23:0 vid_clr_ mask video color mask. this mask is a 24-bit rgb value. zeros in the mask cause the corre- sponding bits in the graphics or video stream to be forced to match. for example: a mask of ffffffh causes all 24 bits to be compared (single color match). a mask of 000000h causes none of the 24 bi ts to be compared (all colors match). for more information about the color key, see vp memory offset 028h on page 426. the video color mask is used to mask bits of the graphics or video stream being compared to the color key. it allows a range of values to be used as the color key.
428 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.8 palette address (par) 6.8.3.9 palette data (pdr) vp memory offset 038h ty p e r / w reset value 00000000_000000xxh par register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pal_addr par bit descriptions bit name description 63:8 rsvd (ro) reserved (read only). reads back as 0. 7:0 pal_addr gamma address. specifies the address to be used for the next access to the palette data register (vp memory offset 040h[23:0 ]). each access to the pdr automatically increments the par. if non-sequential access is made to the palette, the par must be loaded between each non-sequential data block. vp memory offset 040h ty p e r / w reset value 00000000_00xxxxxxh pdr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pal_data pdr bit descriptions bit name description 63:24 rsvd (ro) reserved (read only). reads back as 0. 23:0 pal_data palette data. contains the read or write data for a gamma correction ram (palette). provides the video palette data. the data can be read or written to the gamma correc- tion ram (palette) via this register. prior to accessing this register, an appropriate address should be loaded to the par (vp memory offset 038h[7:0]). subsequent accesses to the pdr cause the internal address counter to be incremented for the next cycle. note: when a read or write to the gamma co rrection ram occurs, the previous output value is held for one additional dotclk period. this effect should go unnoticed during normal operation.
amd geode? lx processors data book 429 video processor register descriptions 33234h 6.8.3.10 saturation scale (slr) vp memory offset 048h ty p e r / w reset value 00000000_00000000h slr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd en spare sat_scale slr bit descriptions bit name description 63:10 rsvd (ro) reserved (read only). reads back as 0. 9en enable. enable saturation scaling. if this bit is cleared, saturation conversion does not occur. if it is set, saturation conversion and scaling occurs prior to yuv conversion of the graphics. 8spare spare. bit is r/w but has no function. 7:0 sat_scale saturation scale. saturation scale value set by software to scale the saturation value derived by the rgb to hsv conversion of the graphics. after scaling the s value, the result is then converted to yuv format prior to blending with the video. this 8-bit value represents 256 equal steps between 0 and 1.
430 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.11 miscellaneous (misc) vp memory offset 050h ty p e r / w reset value 00000000_00000c00h misc register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd sp apwrdn dacpwrdn rsvd byp_both misc bit descriptions bit name description 63:13 rsvd (ro) reserved (read only). reads back as 0. 12 sp spare. read/write; no function. 11 apwrdn analog interface power down. enables power down of the analog section of the inter- nal crt dac. 0: normal. 1: power down. 10 dacpwrdn dac power down. enables power down of the digital section of the internal crt dac. for this bit to take effect: vp memory offset 130h[6] must be = 1 or msr address 48000010h[18:16] must not equal 101. 0: normal. 1: power down. 9:1 rsvd (ro) reserved (read only). reads back as 0. 0 byp_both bypass both. indicates if both graphics and video data should bypass gamma correc- tion ram. 0: the stream selected by the display config uration (dcfg) register (vp memory offset 008h[21]) is passed through gamma correction ram. 1: both graphics and video bypass gamma correction ram.
amd geode? lx processors data book 431 video processor register descriptions 33234h 6.8.3.12 crt clock select (ccs) this register is made up of read only reserv ed bits and spare bits with no functions. 6.8.3.13 video y scale (vys) 6.8.3.14 video x scale (vxs) vp memory offset 058h ty p e r / w reset value 00000000_00000000h vp memory offset 060h ty p e r / w reset value 00000000_00000000h vys register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 y_acc_init vid_y_scl vys bit descriptions bit name description 63:32 rsvd (ro) reserved (read only). reads back as 0. 31:20 y_acc_init y accumulator initial value. load this value before each video frame. works with verti- cal scaling, in case a sub-line offset is required prior to displaying video. pad 4 lsbs with 0 when loading. 19:0 vid_y_scl video y scale factor. bits [19:16] represent the integer part of vertical scale factor of the video window according to the following formula: y_scl_int = 1/ys where: ys = arbitrary vertical scaling factor. bits [15:0] represent the fractional part of vertical scale factor of the video window according to the following formula: vid_y_scl = ff ffh * 1/ys note: if no scaling is intended, set to 10000h. will be greater than 10000h when down- scaling. will be less than 10000h when upscaling. vp memory offset 068h ty p e r / w reset value 00000000_00000000h vxs register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 x_acc_init vid_x_scl
432 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.15 video downscaler control (vdc) vxs bit descriptions bit name description 63:32 rsvd (ro) reserved (read only). reads back as 0. 31:20 x_acc_init x accumulator initial value. load this value before each video line. works with hori- zontal scaling, in case a sub-pixel offset is required prior to displaying video. pad 4 lsbs with 0 when loading. 19:0 vid_x_scl video x scale factor. bits [19:16] represent the integer pa rt of horizontal scale factor of the video window according to the following formula: x_scl_int = 1/xs where: xs = arbitrary horizontal scaling factor. bits [5:0] represent the fractional part of horizontal scale factor of the video window according to the following formula: vid_x_scl = ff ffh * 1/xs note: if no scaling is intended, set to 10000h. will be greater than 1000h when down- scaling. will be less than 10000h when upscaling. vp memory offset 078h ty p e r / w reset value 00000000_00000000h vdc register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dts rsvd dfs dcf vdc bit descriptions bit name description 63:7 rsvd (ro) reserved (read only). reads back as 0. 6dts downscale type select. 0: type a (downscale formula is 1/m + 1, m pixels are dropped, one pixel is kept). 1: type b (downscale formula is m/m + 1, m pixels are kept, one pixel is dropped). 5 rsvd (ro) reserved (read only). reads back as 0. 4:1 dfs downscale factor select. determines the downscale factor to be programmed into these bits, where m is used to derive the desired downscale factor depending on bit 6 (dts). only values up to 7 are valid. 0 dcf downscaler and filtering. enables/disables downscaler and filtering logic. 0: disable. 1: enable.
amd geode? lx processors data book 433 video processor register descriptions 33234h 6.8.3.16 crc signature (crc) vp memory offset 088h ty p e r / w reset value 00000000_00000000h crc register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd sigval sigfr sigen crc bit descriptions bit name description 63:3 rsvd (ro) reserved (read only). reads back as 0. 2 sigval (ro) signature valid (read only). if this bit is set, the signature operation has completed and the signature may be safely read from the 32-bit crc signature register (vp mem- ory offset 090h). 1sigfr signature free run. 0: disable. (default). if this bit was previous ly set to 1, the signat ure process will stop at the end of the current frame (i.e., at the next falling edge of vsync). 1: enable. if signen (bit 0) is set to 1, th e signature register captures data continuously across multiple frames. 0sigen signature enable . 0: disable. the sigval (bits [31:8]) is rese t to 000001h in 24-bit mode or 000000h in 32- bit mode and held (no capture). (default) 1: enable. when this bit is set to 1, the next falling edge of vsync is counted as the start of the frame to be used for crc checking with each pixel clock beginning with the next vsync. if sigfr (bit 1) is set to 1, the signature register captures the pi xel data signature con- tinuously across multiple frames. if sigfr (bit 1) is cleared to 0, a signatur e is captured one frame at a time, starting from the next falling vsync. after a signature capture is complete, the sigval (bit 2) can be read to determine the crc check status. in 32-bit crc mode, the fu ll 32-bit signature can be read from the 32- bit crc signature (vp memory offset 090h[31 :0]). then proceed to reset sigen, which initializes sigval as an essential preparation for the next round of crc checks.
434 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.17 32-bit crc signature (crc32) 6.8.3.18 video de-interlacing and alpha control (vde) vp memory offset 090h ty p e r o reset value 00000000_00000001h crc32 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 sig_value crc32 bit descriptions bit name description 63:32 rsvd (ro) reserved (read only). reads back as 0. 31:0 sig_value (ro) signature value (read only). a 32-bit signature value is stored in this field when in 32- bit crc mode and can be read at any time. the 32-bit crc mode select bit is located in vp diagnostic msr (msr 48000010h[31]). th e signature is produced from the rgb data before it is sent to the crt dacs. this field is used for test purposes only. see vp memory offset 088h for more information. vp memory offset 098h ty p e r / w reset value 00000000_00000400h vde register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd a3p a2p a1p alpha_drbg vid_alpha_en gv_sel csc_vop csc_gfx csc_video hdsd gfx_ins_video yuv_csc_en hdsd_video rsvd sp rsvd sp vde bit descriptions bit name description 63:22 rsvd (ro) reserved (read only). reads back as 0. 21:20 a3p alpha window 3 priority. indicates the priority of alpha window 3. a higher number indi- cates a higher priority. priority is used to determine display order for overlapping alpha windows. this field is reset by hardware to 00. 19:18 a2p alpha window 2 priority. indicates the priority of alpha window 2. a higher number indi- cates a higher priority. priority is used to determine display order for overlapping alpha windows. this field is reset by hardware to 00.
amd geode? lx processors data book 435 video processor register descriptions 33234h 17:16 a1p alpha window 1 priority. indicates the priority of alpha window 1. a higher number indi- cates a higher priority. priority is used to determine display order for overlapping alpha windows. this field is reset by hardware to 00. 15 alpha_drgb enable alpha on drgb[31:24]. the source of the alpha value is the upper 8 bits [31:24] of the graphics input bus. when this bit is set, the upper 8 bits of the graphics input bus is passed through to the upper 8 bits [31:24] of t he drgb output bus. if bit 14 is also set, the actual video blended alpha value replaces the graphics alpha value when inside an alpha window. 00: drgb[31:24] are not driven. 01: drgb[31:24] are not driven. 10: drgb[31:24] contain contents of graphics input bus [31:24]. 11: drgb[31:24] contain conten ts of graphics input bus [31:24] when not inside any alpha window; inside any alpha window, drg b[31:24] contains actual video alpha value. 14 vid_alpha_en enable video alpha value onto drgb[31:24]. when inside an alpha window, drive the video alpha value (graphics per-pixel alpha va lue multiplied by the multiplier) onto bits [31:24] of the drgb output bus. 00: drgb[31:24] are not driven. 01: drgb[31:24] are not driven. 10: drgb[31:24] contain contents of graphics input bus [31:24]. 11: drgb[31:24] contain conten ts of graphics input bus [31:24] when not inside any alpha window; inside any alpha window, drg b[31:24] contains actual video alpha value. 13 gv_sel graphics video select. selects input video format. 0: yuv format. 1: rgb format. if this bit is set to 1, bit en_420 (vp me mory offset 000h[28]) must be set to 0. 12 csc_vop color space converter for vop. determines whether or not the output from the blender is passed through the color space converter (csc) before entering the vop. 0: disable. the output of the blender is sent ?as is? to the mixer/blender. 1: enable. the output of the blender is passed through the csc (for rgb to yuv conver- sion). 11 csc_gfx color space converter for graphics. determines whether or not the graphics stream is passed through the color space converter (csc). 0: disable. the graphics stream is sent ?as is? to the mixer/blender. 1: enable. the graphics stream is passed through the csc (for rgb to yuv conver- sion). 10 csc_video color space converter for video. determines whether or not the video stream from the video module is passed through the color space converter (csc). 0: disable. the video stream is se nt ?as is? to the video mixer/blender. 1: enable. the video stream is passed thr ough the csc (for yuv to rgb conversion). 9 hdsd high definition/stand ard definition csc. determines which algorithm to use for graphics color space conversion from rgb to yuv. 0: standard definition. 1: high definition. vde bit descriptions (continued) bit name description
436 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.19 cursor color key (cck) 8gfx_ins_ video graphics window inside video window. 0: disable. the video window is assumed to be inside the graphics window. outside the alpha window, graphics or video is displayed, depending on the result of color key comparison. 1: enable. the graphics window is assumed to be inside the video window. outside the alpha windows, video is displayed instead of graphics. color key comparison is not performed outside the alpha window. 7yuv_csc_en yuv color space conversion enable. enables yuv to yuv color space conversion on the video yuv input. hdsd_video (bit 6) is used to determine which resolution the source video is. the video will be converted to the opposite resolution. if hdsd_video = 0: yuv sd -> yuv hd if hdsd_video = 1: yuv hd -> yuv sd 6 hdsd_video high definition/standard definition csc on video. determines what the source video resolution is for both yuv to rgb and yuv to yuv color space conversion algorithms. 0: video source is in standard definition (rec.itu-r bt-601). 1: video source is in high definition (rec.itu-r bt-709). 5 rsvd (ro) reserved (read only). reads back as 0. 4sp spare. read/write , no function. 3 rsvd (ro) reserved (read only). reads back as 0. 2:0 sp spares. read/write, no function. vp memory offset 0a0h ty p e r / w reset value 00000000_00000000h vde bit descriptions (continued) bit name description cck register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd cck_en color_reg_ offset cur_color_key cck bit descriptions bit name description 63:30 rsvd (ro) reserved (read only). reads back as 0. 29 cck_en cursor color key enable. this bit enables the cursor color key matching function. 0: disable. graphics data will never match the cursor color key. 1: enable. graphics data is compared to the cursor color key. 28:24 color_reg_ offset cursor color register offset. this field indicates a bit in the incoming graphics stream that is used to indicate which of the two possi ble cursor color registers should be used for color key matches for the bi ts in the graphics stream. 23:0 cur_color_ key cursor color key. specifies the 24-bit rgb value of the cursor color key. the incoming graphics stream is compared with this value. if a match is detected, the pixel is replaced by a 24-bit value from one of the cursor color registers.
amd geode? lx processors data book 437 video processor register descriptions 33234h 6.8.3.20 cursor co lor mask (ccm) 6.8.3.21 cursor color 1 (cc1) vp memory offset 0a8h ty p e r / w reset value 00000000_00000000h ccm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd cur_color_mask ccm bit descriptions bit name description 63:24 rsvd (ro) reserved (read only). reads back as 0. 23:0 cur_color_ mask cursor color mask. this mask is a 24-bit value. zeroes in the mask cause the corre- sponding bits in the incoming graphics stream to be forced to match. example: a mask of ffffffh causes all 24 bits to be compared (single color match). a mask of 000000h causes none of the 24 bi ts to be compared (all colors match). vp memory offset 0b0h ty p e r / w reset value 00000000_00000000h cc1 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd cur_color_reg1 cc1 bit descriptions bit name description 63:24 rsvd (ro) reserved (read only). reads back as 0. 23:0 cur_color_ reg1 cursor color register 1. specifies a 24-bit cursor color value. this is an rgb value (for rgb blending). this is one of two possible cursor color valu es. bits[28:24] of the cursor color key regis- ter (vp memory offset 0a0h) determine a bit of the graphics data that if even, selects this color to be used.
438 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.22 cursor color 2 (cc2) 6.8.3.23 alpha window 1 x position (a1x) vp memory offset 0b8h ty p e r / w reset value 00000000_00000000h cc2 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd cur_color_reg2 cc2 bit descriptions bit name description 63:24 rsvd (ro) reserved (read only). reads back as 0. 23:0 cur_color_ reg2 cursor color register 2. specifies a 24-bit cursor color value. this is an rgb value (for rgb blending). this is one of two possible cursor color values.color_reg_offset (vp memory off- set 0a0h[28:24] determine a bit of the graphics da ta that if odd, selects this color to be used. vp memory offset 0c0h ty p e r / w reset value 00000000_00000000h a1x register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd alpha1_x_end rsvd alpha1_x_start a1x bit descriptions bit name description 63:28 rsvd (ro) reserved (read only). reads back as 0. 27:16 alpha1_x_ end alpha window 1 x end. indicates the horizontal end position of alpha window 1. this value is calculated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 1. (note 1) 15:12 rsvd (ro) reserved (read only). reads back as 0. 11:0 alpha1_x_ start alpha window 1 x start. indicates the horizontal start position of alpha window 1. this value is calculated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 2. (note 1) note 1. h_total and h_sync_end are values progra mmed in the display controller module registers. the value of (h_total ? h_sync_end) is someti mes referred to as ?horizontal back porch.?
amd geode? lx processors data book 439 video processor register descriptions 33234h 6.8.3.24 alpha window 1 y position (a1y) 6.8.3.25 alph a window 1 color (a1c) vp memory offset 0c8h ty p e r / w reset value 00000000_00000000h a1y register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd alpha1_y_end rsvd alpha1_y_start a1y bit descriptions bit name description 63:27 rsvd (ro) reserved (read only). reads back as 0. 26:16 alpha1_y_ end alpha window 1 y end. indicates the vertical end pos ition of alpha window 1. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 2. (note 1) 15:11 rsvd (ro) reserved (read only). reads back as 0. 10:0 alpha1_y_ start alpha window 1 y start. indicates the vertical start position of alpha window 1. this value is calculated according to the following formula: value = desired screen position + (v_t otal ? v_sync_end) + 1. (note 1) note 1. v_total and v_sync_end are values programm ed in the display controller module registers. the value of (v_total ? v_syn c_end) is sometimes referred to as ?vertical back porch.? vp memory offset 0d0h ty p e r / w reset value 00000000_00000000h a1c register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd alpha1_color_reg_en alpha1_color_reg
440 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.26 alpha window 1 control (a1t) a1c bit descriptions bit name description 63:25 rsvd (ro) reserved (read only). reads back as 0. 24 alpha1_ color_reg_ en alpha window 1 color register enable. enable bit for the color key matching in alpha window 1. 0: disable. if this bit is disabled, the alpha window is enabled, and vg_ck = 0 (vp mem- ory offset 008h[20]); then where there is a color key match within the alpha window, video is displayed. if this bit is disabled, the alpha window is enabled, and vg_ck = 1 (vp memory offset 008h[20]); then where there is a chroma-key match within the alpha window, graphics are displayed. see figure 6-31 on page 438. 1: enable. if this bit is enabled and the alpha window is enabled, then where there is a color key match within the alpha window; the color value in alpha1_color_reg (bits [23:0]) is displayed. 23:0 alpha1_ color_reg alpha window 1 color register. specifies the color to be displayed inside the alpha window when there is a color key match in the alpha window. this color is only displayed if the alpha window is enabled and alpha1_color_reg_en (b it 24) is enabled. vp memory offset 0d8h ty p e r / w reset value 00000000_00000000h a1t register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd ppa1_en load_alpha alpha1_win_en alpha1_inc alpha1_mul
amd geode? lx processors data book 441 video processor register descriptions 33234h 6.8.3.27 alpha window 2 x position (a2x) a1t bit descriptions bit name description 63:19 rsvd (ro) reserved (read only). reads back as 0. 18 ppa1_en per-pixel alpha window 1 enable. enable per-pixel alpha functionality for alpha win- dow 1. 0: single alpha value for entire alpha window 1 (alpha1_mul). 1: each pixel has its own alpha value defined in the upper 8 bits of the graphics bus. 17 load_alpha (wo) load alpha (write only). when set to 1, this bit causes the video processor to load the alpha value (bits [31:24] of the video data pa th) multiplied with the alpha multiplier bits (alpha1_mul, bits [7:0]) at the start of the next frame. this bit is cleared by the de- assertion of vsync. 16 alpha1_win_ en alpha window 1 enable. enable bit for alpha window 1. 0: disable alpha window 1. 1: enable alpha window 1. 15:8 alpha1_inc alpha window 1 increment. specifies the alpha value increment/decrement. this is a signed 8-bit value that is added to the alpha value for each frame. the msb (bit 15) indi- cates the sign (i.e., increment or decrement). when this value reaches either the maxi- mum or the minimum alpha value (255 or 0), it keeps that value (i.e., it is not incremented/decremented) until it is reloaded via load_alpha (bit 17). 7:0 alpha1_mul alpha window 1 value. specifies the alpha value to be used for this window. vp memory offset 0e0h ty p e r / w reset value 00000000_00000000h a2x register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd alpha2_x_end rsvd alpha2_x_start a2x bit descriptions bit name description 63:28 rsvd (ro) reserved (read only). reads back as 0. 27:16 alpha2_x_ end alpha window 2 x end. indicates the horizontal end position of alpha window 2. this value is calculated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 1. (note 1) 15:12 rsvd (ro) reserved (read only). reads back as 0. 11:0 alpha2_x_ start alpha window 2 x start. indicates the horizontal start position of alpha window 2. this value is calculated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 2. (note 1) note 1. h_total and h_sync_end are values progra mmed in the display controller module registers. the value of (h_total ? h_sync_end) is sometimes referred to as ?horizontal back porch.?
442 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.28 alpha window 2 y position (a2y) 6.8.3.29 alph a window 2 color (ac2) vp memory offset 0e8h ty p e r / w reset value 00000000_00000000h a2y register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd alpha2_y_end rsvd alpha2_y_start a2y bit descriptions bit name description 63:27 rsvd (ro) reserved (read only). reads back as 0. 26:16 alpha2_y_ end alpha window 2 y end. indicates the vertical end posit ion of alpha window 2. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 2. (note 1) 15:11 rsvd (ro) reserved (read only). reads back as 0. 10:0 alpha2_y_ start alpha window 2 y start. indicates the vertical start position of alpha window 2. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 1. (note 1) note 1. v_total and v_sync_end are values programm ed in the display controller module registers. the value of (v_total ? v_syn c_end) is sometimes referred to as ?vertical back porch.? vp memory offset 0f0h ty p e r / w reset value 00000000_00000000h a2c register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd alpha2_color_reg_en alpha2_color_reg
amd geode? lx processors data book 443 video processor register descriptions 33234h 6.8.3.30 alpha window 2 control (a2t) a2c bit descriptions bit name description 63:25 rsvd (ro) reserved (read only). reads back as 0. 24 alpha2_ color_reg_ en alpha window 2 color register enable. enable bit for the color key matching in alpha window 2. 0: disable. if this bit is disabled, the alpha window is enabled, and vg_ck = 0 (vp mem- ory offset 008h[20]); then where there is a color key match within the alpha window, video is displayed. if this bit is disabled, the alpha window is enabled, and vg_ck = 1 (vp memory offset 008h[20]); then where there is a chroma-key match within the alpha window, graphics are displayed. see figure 6-31 on page 438. 1: enable. if this bit is enabled and the alpha window is enabled, then where there is a color key match within the alpha window; the color value in alpha2_color_reg (bits [23:0]) is displayed. 23:0 alpha2_ color_reg alpha window 2 color register. specifies the color to be displayed inside the alpha window when there is a color key match in the alpha window. this color is only displayed if the alpha window is enabled and alpha2_color_reg_en (b it 24) is enabled. vp memory offset 0f8h ty p e r / w reset value 00000000_00000000h a2t register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd ppa2_en load_alpha alpha2_win_en alpha2_inc alpha2_mul a2t bit descriptions bit name description 63:19 rsvd (ro) reserved (read only). reads back as 0. 18 ppa2_en per-pixel alpha window 2 enable. enable per-pixel alpha functionality for alpha win- dow 2. 0: single alpha value for entire alpha window 2 (alpha2_mul). 1: each pixel has its own alpha value defined in the upper 8 bits of the graphics bus. 17 load_alpha load alpha (write only). when set to 1, this bit causes the video processor module to load the alpha value (bits [31:24] of the vi deo data path) multiplied with the alpha multi- plier (alpha2_mul, bits [7:0]) at the start of the next frame. this bit is cleared by the de- assertion of vsync.
444 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.31 alpha window 3 x position (a3x) 16 alpha2_win_ en alpha window 2 enable. enable bit for alpha window 2. 0: disable alpha window 2. 1: enable alpha window 2. 15:8 alpha2_inc alpha window 2 increment. specifies the alpha value increment/decrement. this is a signed 8-bit value that is added to the alpha value for each frame. the msb (bit 15) indi- cates the sign (i.e., increment or decrement). when this value reaches either the maxi- mum or the minimum alpha value (255 or 0) it keeps that value (i.e., it is not incremented/ decremented) until it is reload ed via load_alpha (bit 17). 7:0 alpha2_mul alpha window 2 value. specifies the alpha value to be used for this window. vp memory offset 100h ty p e r / w reset value 00000000_00000000h a2t bit descriptions (continued) bit name description a3x register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd alpha3_x_end rsvd alpha3_x_start a3x bit descriptions bit name description 63:28 rsvd (ro) reserved (read only). reads back as 0. 27:16 alpha3_x_ end alpha window 3 x end. indicates the horizontal end position of alpha window 3. this value is calculated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 1. (note 1) 15:12 rsvd (ro) reserved (read only). reads back as 0. 11:0 alpha3_x_ start alpha window 3 x start. indicates the horizontal start position of alpha window 3. this value is calculated according to the following formula: value = desired screen position + (h_total ? h_sync_end) ? 2. (note 1) note 1. h_total and h_sync_end are values progra mmed in the display controller module registers. the value of (h_total ? h_sync_end) is sometimes referred to as ?horizontal back porch.?
amd geode? lx processors data book 445 video processor register descriptions 33234h 6.8.3.32 alpha window 3 y position (a3y) 6.8.3.33 alph a window 3 color (a3c) vp memory offset 108h ty p e r / w reset value 00000000_00000000h a3y register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd alpha3_y_end rsvd alpha3_y_start a3y bit descriptions bit name description 63:27 rsvd (ro) reserved (read only). reads back as 0. 26:16 alpha3_y_ end alpha window 3 y end. indicates the vertical end posit ion of alpha window 3. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 2. (note 1) 15:11 rsvd (ro) reserved (read only). reads back as 0. 10:0 alpha3_y_ start alpha window 3 y start. indicates the vertical start position of alpha window 3. this value is calculated according to the following formula: value = desired screen position + (v_t otal ? v_sync_end) + 1. (note 1) note 1. v_total and v_sync_end are values pr ogrammed in the display controller module. the value of (v_total ? v_syn c_end) is sometimes referred to as ?vertical back porch.? vp memory offset 110h ty p e r / w reset value 00000000_00000000h a3c register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd alpha3_color_reg_en alpha3_color_reg
446 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.34 alpha window 3 control (a3t) a3c bit descriptions bit name description 63:25 rsvd (ro) reserved (read only). reads back as 0. 24 alpha3_ color_reg_ en alpha window 3 color register enable. enable bit for the color key matching in alpha window 3. 0: disable. if this bit is disabled, the alpha window is enabled, and vg_ck = 0 (vp mem- ory offset 008h[20]); then where there is a color key match within the alpha window, video is displayed. if this bit is disabled, the alpha window is enabled, and vg_ck = 1 (vp memory offset 008h[20]); then where there is a chroma-key match within the alpha window; graphics are displayed. see figure 6-31 on page 438. 1: enable. if this bit is enabled and the alpha window is enabled, then where there is a color key match within the alpha window; the color value in alhpa3_color_reg (bits [23:0]) is displayed. 23:0 alpha3_ color_reg alpha window 3 color register. specifies the color to be displayed inside the alpha window when there is a color key match in the alpha window. this color is only displayed if the alpha window is enabled and the alpha3_color_reg_en (b it 24) is enabled. vp memory offset 118h ty p e r / w reset value 00000000_00000000h a3t register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd ppa3_en load_alpha alpha3_win_en alpha3_inc alpha3_mul a3t bit descriptions bit name description 63:19 rsvd (ro) reserved (read only). reads back as 0. 18 ppa3_en per-pixel alpha window 3 enable. enable per-pixel alpha functionality for alpha win- dow 3. 0: single alpha value for entire alpha window 3 (alpha3_mul) 1: each pixel has its own alpha value defined in the upper 8 bits of the graphics bus. 17 load_alpha (wo) load alpha (write only). when set to 1, this bit causes the video processor to load the alpha value (bits [31:24] of the video data path) multiplied with the alpha multiplier (alpha3_mul, bits [7:0]) at the start of the next frame. this bit is cleared by the de- assertion of vsync.
amd geode? lx processors data book 447 video processor register descriptions 33234h 6.8.3.35 video request (vrr) 16 alpha3_win_ en alpha window 3 enable. enable bit for alpha window 3. 0: disable alpha window 3. 1: enable alpha window 3. 15:8 alpha3_inc alpha window 3 increment. specifies the alpha value increment/decrement. this is a signed 8-bit value that is added to the alpha value for each frame. the msb (bit 15) indi- cates the sign (i.e., increment or decrement). when this value reaches either the maxi- mum or the minimum alpha value (255 or 0) it keeps that value (i.e., it is not incremented/ decremented) until it is reload ed via load_alpha (bit 17). 7:0 alpha3_mul alpha window 3 value. specifies the alpha value to be used for this window. vp memory offset 120h ty p e r / w reset value 00000000_001b0017h a3t bit descriptions (continued) bit name description vrr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd xrq rsvd yrq vrr bit descriptions bit name description 63:28 rsvd (ro) reserved (read only). reads back as 0. 27:16 xrq video x request. indicates the horizontal (pixel) location to start requesting video data from. 15:11 rsvd (ro) reserved (read only). reads back as 0. 10:0 yrq video y request. indicates the line number to start requesting video data from.
448 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.36 alpha watch (awt) alpha values may be automatically incr emented/decremented for successive frames. this register can be used to read alpha values that are being used in the current frame. 6.8.3.37 video processor test mode (vtm) vp memory offset 128h ty p e r o reset value 00000000_00000000h awt register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd aw3 aw2 aw1 awt bit descriptions bit name description 63:24 rsvd reserved. reads back as 0. 23:16 aw3 alpha value for window 3 . 15:8 aw2 alpha value for window 2 . 7:0 aw1 alpha value for window 1 . vp memory offset 130h ty p e r / w reset value 00000000_00000000h vtm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 sp rsvd sp rsvd rsvd rsvd vtm bit descriptions bit name description 63:32 rsvd (ro) reserved (read only). reads back as 0. 31 sp spare. read/write; no function. 30:11 rsvd (ro) reserved (read only). reads back as 0. 10:9 sp spares. read/write; no function. 8:7 rsvd (ro) reserved (read only). reads back as 0. 6 rsvd reserved. reserved for test purposes. 5:4 rsvd (ro) reserved (read only). reads back as 0. 3:0 rsvd reserved. reserved for test purposes.
amd geode? lx processors data book 449 video processor register descriptions 33234h 6.8.3.38 even video y position (vye) 6.8.3.39 even alpha window 1 y position (a1ye) vp memory offset 138h ty p e r / w reset value 00000000_00000000h vye register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd vid_y_end rsvd vid_y_start vye bit descriptions bit name description 63:27 rsvd (ro) reserved (read only). reads back as 0. 26:16 vid_y_end video y end position. represents the vertical end position of the video window. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 2. (note 1) 15:11 rsvd (ro) reserved (read only). reads back as 0. 10:0 vid_y_start video y start position. represents the vertical start position of the video window. this register is programmed relative to crt ve rtical sync input (not the physical screen posi- tion). this value is calculated according to the following formula: value = desired screen position + (v_t otal ? v_sync_end) + 1. (note 1) note 1. v_total and v_sync_end are the values wri tten in the display controller module registers. vp memory offset 140h ty p e r / w reset value 00000000_00000000h a1ye register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd alpha1_y_end rsvd alpha1_y_start a1ye bit descriptions bit name description 63:27 rsvd (ro) reserved (read only). reads back as 0. 26:16 alpha1_y_ end alpha window 1 y end. indicates the vertical end position of alpha window 1. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 2. (note 1) 15:11 rsvd (ro) reserved (read only). reads back as 0. 10:0 alpha1_y_ start alpha window 1 y start. indicates the vertical start position of alpha window 1. this value is calculated according to the following formula: value = desired screen position + (v_t otal ? v_sync_end) + 1. (note 1) note 1.v_total and v_sync_end are values programmed in the display controller module registers. the value of (v_total ? v_sync_end) is sometimes referred to as ?vertical back porch?.
450 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.40 even alpha window 2 y position (a2ye) 6.8.3.41 even alpha window 3 y position (a3ye) vp memory offset 148h ty p e r / w reset value 00000000_00000000h a2ye register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd alpha2_y_end rsvd alpha2_y_start a2ye bit descriptions bit name description 63:27 rsvd (ro) reserved (read only). reads back as 0. 26:16 alpha2_y_ end alpha window 2 y end. indicates the vertical end position of alpha window 2. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 2. (note 1) 15:11 rsvd (ro) reserved (read only). reads back as 0. 10:0 alpha2_y_ start alpha window 2 y start. indicates the vertical start position of alpha window 2. this value is calculated according to the following formula: value = desired screen position + (v_t otal ? v_sync_end) + 1. (note 1) note 1. v_total and v_sync_end are values programmed in t he display controller module registers. the value of (v_total ? v_sync_end) is sometimes referred to as ?vertical back porch?. vp memory offset 150h ty p e r / w reset value 00000000_00000000h a3ye register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd alpha3_y_end rsvd alpha3_y_start a3ye bit descriptions bit name description 63:27 rsvd (ro) reserved (read only). reads back as 0. 26:16 alpha3_y_ end alpha window 3 y end. indicates the vertical end position of alpha window 3. this value is calculated according to the following formula: value = desired screen position + (v_total ? v_sync_end) + 2. (note 1) 15:11 rsvd (ro) reserved (read only). reads back as 0. 10:0 alpha3_y_ start alpha window 3 y start. indicates the vertical start position of alpha window 3. this value is calculated according to the following formula: value = desired screen position + (v_t otal ? v_sync_end) + 1. (note 1) note 1. v_total and v_sync_end are values programmed in t he display controller module registers. the value of (v_total ? v_sync_end) is sometimes referred to as ?vertical back porch?.
amd geode? lx processors data book 451 video processor register descriptions 33234h 6.8.3.42 video coefficient ram (vcr) 6.8.3.43 panel timing register 1 (pt1) vp memory offset 1000h-1fffh ty p e r / w reset value xxxxxxxx_xxxxxxxxh vcr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 vc3 vc2 313029282726252423222120191817161514131211109876543210 vc1 vc0 vcr bit descriptions bit name description 63:48 vc3 coefficient 3. coefficient for tap 3 of filter. 47:32 vc2 coefficient 2. coefficient for tap 2 of filter. 31:16 vc1 coefficient 1. coefficient for tap 1 of filter. 15:0 vc0 coefficient 0. coefficient for tap 0 of filter. vp memory offset 400h ty p e r / w reset value 00000000_00000000h pt1 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd fp_vsync_pol fp_hsync_pol rsvd hsync_src rsvd hsync_delay hsync_pls_width pt1 bit descriptions bit name description 63:32 rsvd (ro) reserved (read only). reads back as 0. 31 rsvd reserved. this bit is not defined. 30 fp_vsync_ pol fp_vsync input polarity. selects positive or negative polarity of the fp_vsync input. program this bit to match the polarity of the incoming fp_vsync signal. note that fp memory offset 408h[23] controls the polarity of the output vsync. 0: fp_vsync is normally low, transitioning high during sync interval. (default) 1: fp_vsync is normally high, transitioning low during sync interval
452 amd geode? lx processors data book video processor register descriptions 33234h 29 fp_hsync_ pol fp_hsync input polarity. selects positive or negative polarity of the fp_hsync input. program this bit to match the polarity of the incoming fp_hsync signal. note that fp memory offset 408h[22] controls the polarity of the output hsync. 0: fp_hsync is normally low, transitioning high during sync interval. (default ) 1: fp_hsync is normally high, transitioning low during sync interval 28 rsvd reserved. this bit is not defined. 27 hsync_src tft horizontal sync source. selects a delayed or undelayed tft horizontal sync out- put. this bit determines whether to use the hsync for the tft panel without delaying the input hsync, or delay the hsync before sending it on to tft. hsync_delay (bits [7:5]) determine the amount of the delay. 0: do not delay the input hsync before it is output onto the lp/hsync. (default) 1: delay the input hsync before it is output onto the lp/hsync 26:8 rsvd reserved. r/w; no function. 7:5 hsync_delay horizontal sync delay. selects the amount of delay in the output hsync pulse with respect to the input hsync pulse. the delay is programmable in steps of one dotclk. sync_src (bit 27) must be set in order for hsync_delay to be recognized. hsync_delay is only used for tft modes. 000: no delay from the input hsync. (default) 001-111: delay the hsync start by one to seven dotclks. 4:0 hsync_pls_ width horizontal sync pulse width. stretch the hsync pulse width by up to 31 dotclks. the pulse width is programmable in steps of one dotclk. hsync_pls_width is only used for tft modes. 00000: does not generate the hsync pulse. the tft panel uses the default input tim- ing, which is selected by keeping the hsync_src bit (bit 27) set to 0. (default) 00001-11111: the hsync pulse width can be varied from one to 31 dotclks. pt1 bit descriptions (continued) bit name description
amd geode? lx processors data book 453 video processor register descriptions 33234h 6.8.3.44 panel timing register 2 (pt2) vp memory offset 408h ty p e r / w reset value 00000000_00000000h pt2 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 sp tft_pass_thru lpol rsvd scrc rsvd vsp hsp rsvd mcs pixf rsvd pt2 bit descriptions bit name description 63:32 rsvd (ro) reserved (read only). reads back as 0. 31 sp spare. bit is read/write, but has no function. 30 tft_pass_ thru tft pass through. activates the tft pass through mode. in tft pass through mode, the input timing and the pixel data is passed directly on to the panel interface tim- ing and the panel data pins to drive the tft panel. in pass through mode the internal fp tft logic and timing is not used. 0: normal mode; uses the tft logic and timing from the fp. 1: tft pass through mode; fp tft ti ming logic functions are not used. 29 lpol display timing strobe polarity select. selects the polarity of the lde/mod pin. this can be used for panels that require an active low timing lde interface signal. 0: lde/mod signal is active high. (default) 1: lde/mod signal is active low 28 rsvd reserved. this bit is not defined. 27 scrc panel shift clock retrace activity control. programs the shift clock (shfclk) to be either free running, or active only during the display period. some tft panels recom- mend keeping the shift clock running during the retrace time. 0: shift clock is active only during active display period. 1: shift clock is free running during the entire frame period. 26:24 rsvd reserved . these bits are not defined. 23 vsp vertical sync output polarity. selects polarity of the output vsync signal. note that vp memory offset 400h[30 ] selects the polarity of the input vsync. 0: vsync output is active high. 1: vsync output is active low 22 hsp horizontal sync output polarity. selects polarity of output hsync signal. note that vp memory offset 400h[29] selects the polarity of the input hsync, and this bit controls the output polarity. 0: hsync output is active high. 1: hsync output is active low 21:20 rsvd reserved. these bits are not defined.
454 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.45 power management (pm) 19 mcs color/mono select. selects color or monochrome lcd panel. 0: color. 1: monochrome. 18:16 pixf pixel output format . these bits define the pixel output format. the selection of the pixel output format determines how the pixel da ta is formatted before being sent on to the drgb pins. these settings also determine the shfclk frequency for the specific panel. 000: up to 24-bit tft panel with one pixel per clock. shfclk = dotclk. 001: 18/24-bit tft xga panel with two pixels per clock. shfclk = 1/2 of dotclk. 010, 011, 100, 101, 1 10, and 111: reserved. 15:0 rsvd reserved. these bits are not defined. fp memory offset 410h ty p e r / w reset value 00000000_00000002h pt2 bit descriptions (continued) bit name description pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 sp pwr_seq_sel pnl_pwr_sim d p pub2 pub1 pub0 pd2 pd1 pd0 hdel vdel sinv sp panel_pwr_up panel_pwr_down pa n e l _ o f f panel_on pm bit descriptions bit name description 63:32 rsvd (ro) reserved (read only). reads back as 0. 31:28 sp spares. read/write; no function. 27 pwr_seq_sel power sequence select. selects whether to use internal or external power sequence. the power sequence controls the order in which vdden, the data and control signals, and the backlight co ntrol signal dispen become active during power up, and inactive during power down. 0: use internal power sequencing (tim ing is controlled by bits [24:18]). 1: use external power sequencing. must be written to 0. 26 pnl_pwr_sim panel power sequence test mode. this bit should always be set to 0. for simulating the model of the panel power sequence logic, this bit may be set to 1. it connects the 14 mhz reference clock to the 32 hz panel power sequence clock for faster simulations. the hardware will not function properly if this bit is set to 1.
amd geode? lx processors data book 455 video processor register descriptions 33234h 25 d display off control source. selects how dispen is controlled. independent control may be used to disable the backlight to save power even if the panel is otherwise on. 0: dispen is controlled by with the power up/down sequence. 1: dispen is controlled independently of the power sequence. 24 p panel power on. selects whether the panel is powered down or up following the power sequence mechanism. 0: power down. 1: power up. 23 pub2 panel power up phase bit 2. selects the amount of time from when v core is enabled to when the panel data signals are enabled. 0: 32 ms 1: 128 ms 22 pub1 panel power up phase bit 1. selects the time amount of from when the panel data signals are enabled to pub0. 0: 32 ms. 1: 128 ms. 21 pub0 panel power up phase bit 0. selects the amount of time from pub1 to when dis- pen is enabled. 0: 32 ms. 1: 128 ms. 20 pd2 panel power down phase bit 2. selects the amount of time from when panel dis- pen is disabled to pd1. 0: 32 ms. 1: 128 ms. 19 pd1 panel power down phase bit 1. selects the amount of ti me from pd2 to when the panel data signals are disabled. 0: 32 ms. 1: 128 ms. 18 pd0 panel power down phase bit 0. selects the amount of ti me from when the panel data signals are disabled to when panel v core is disabled. 0: 32 ms. 1: 128 ms. 17:16 hdel hsync delay. delays hsync 0 - 3 dot clocks. 15:14 vdel vsync delay. delays vsync 0 - 3 dot clocks. 13 sinv shfclk invert. invert shfclk to panel. 12:4 sp spares. read/write; no function. 3 panel_pwr_up (ro) panel power-up status (read only). a 1 indicates the flat panel is currently power- ing up. 2 panel_pwr_ down (ro) panel power-down status (read only). a 1 indicates the flat panel is currently pow- ering down. 1 panel_off (ro) panel off status (read only). a 1 indicates the flat panel is currently fully off. 0 panel_on (ro) panel on status (read only). a 1 indicates the flat panel is currently fully on. pm bit descriptions (continued) bit name description
456 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.46 dither and frame rate control (dfc) vp memory offset 418h ty p e r / w reset value 00000000_00000000h dfc register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd rrs rsvd rvrs rsvd bc dbs denb dfc bit descriptions bit name description 63:13 rsvd (ro) reserved (read only). reads back as 0. 12 rrs ram or rom select. this bit selects either internal rom or internal ram as the source of the dither patterns. 0: selects fixed (internal to fp) rom for dither patterns. (default) 1: selects programmable (internal to fp) ram for dither patterns. to update the dither ram, this bit must = 1. see fp memory offset 448h[6]. 11 rsvd (ro) reserved (read only). reads back as 0. 10 rvrs negative image. this converts the black to white and white to black and all colors in between to their logical inverse to provide a negative im age of the original image. it acts as though the incoming data stream were logically inverted (1 becomes 0 and 0 becomes 1). 0: normal display mode. 1: negative image display mode. 9:7 rsvd (ro) reserved (read only). reads back as 0. 6:4 bc base color. this field is used in conjunction with the dbs field (bits [3:1[). the value in bits [6:4] sets the base color used prior to dithering. 000: select 1 msb for base color use prior to dithering. 001: select 2 msb for base color use prior to dithering. 010: select 3 msb for base color use prior to dithering. 011: select 4 msb for base color use prior to dithering. 100: select 5 msb for base color use prior to dithering. 101: select 6 msb for base color use prior to dithering. 110: select 7 msb for base color use prior to dithering. 111: select 8 msb for base color, no dithering. 3:1 dbs dithering bits select. this field is used to select the num ber of bits to be used for the dither- ing pattern. dither bits are the lsbs of each pi xel?s final color value; frm bits are the msbs. 000: selects 6 bits as dither bits. 001: selects 5 bits as dither bits. 010: selects 4 bits as dither bits. 011: selects 3 bits as dither bits. 100: selects 2 bits as dither bits. 101: selects 1 bits as dither bits. 110, 111: reserved.
amd geode? lx processors data book 457 video processor register descriptions 33234h 6.8.3.47 dither ram control and address (dca) 0denb dithering enable. enable/disable dithering. the dither bit must be enabled in order for dither ram reads or writes to occur. when this bit is cleared, the internal dither ram is powered down, which saves power. 0: dither disable. the dithering function is tur ned off. when the dither is disabled the dithering bits select (bits [3:1]) do not have any effect and the dither ram is not accessible. 1: dither enable. the dit her functions with the number of dither bits as set in the dithering bits select (bits [3:1]). vp memory offset 448h ty p e r / w reset value 00000000_00000000h dfc bit descriptions (continued) bit name description dca register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd a u addr dca bit descriptions bit name description 63:8 rsvd (ro) reserved (read only). reads back as 0. 7a dither ram access bit. allows reads and writes to/from dither ram. 0: disable (do not allow reads or writes). 1: enable (allow reads and writes). to perform dither ram writes and reads, both bits 7 and 6 must be set to 1. in addition vp memory offset 418h bits 12 and 0 must both be set to 1. if any of these bits are not set to 1, the ram goes into power-down mode. 6u dither ram update. this bit works in conjunction with bit 7. if this bit is enabled, it allows the data to update the ram. 0: disable (do not allow dither ram accesses). 1: enable (allow dither ram accesses). to perform dither ram writes and reads, both bits 7 and 6 must be set to 1. in addition vp memory offset 418h bits 12 and 0 must both be set to 1. if any of these bits are not set to 1, the ram goes into power-down mode. 5:0 addr ram address. this 6-bit field specifies the address to be used for the next access to the dither ram.
458 amd geode? lx processors data book video processor register descriptions 33234h 6.8.3.48 dither memory data (dmd) 6.8.3.49 panel crc signature (crc) vp memory offset 450h ty p e r / w reset value 00000000_00000000h dmd register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rdat dmd bit descriptions bit name description 63:32 rsvd (ro) reserved (read only). reads back as 0. 31:0 rdat ram data. this 32-bit field contains the read or write data for the ram access. vp memory offset 458h ty p e r / w reset value 00000000_00000000h crc register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd frct sigval sigfr sigen crc bit descriptions bit name description 63:9 rsvd (ro) reserved (read only). reads back as 0. 8:3 frct (ro) frame count (read only). represents the frame count, which is an index for the gener- ated signature for that frame. 2 sigval (ro) signature valid (read only). if this bit is set, the signature operation has completed and the signature may be safely read from the 32-bit panel crc register (vsp memory offset 468h). 1sigfr signature free run. if this bit is high, with signature enabled (bit 0 = 1), the signature generator captures data continuously across multiple frames. this bit may be set high when the signature is started, then later se t low, which causes the signature generation process to stop at the end of the current frame. 0: capture signature for only one frame. 1: free run across multiple frames. 0sigen signature enable. enables/disables signature capture. 1: enable signature capture. 0: disable signature capture.
amd geode? lx processors data book 459 video processor register descriptions 33234h 6.8.3.50 32-bit panel crc (crc32) 6.8.3.51 video output port configuration (vop_config) vp memory offset 468h ty p e r o reset value 00000000_00000001h crc32 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 crc crc32 bit descriptions bit name description 63:32 rsvd reserved. reads back as 0. 31:0 crc 32-bit crc. 32-bit signature when in 32-bit crc mode. see fp memory offset 458h for additional information. vp memory offset 800h ty p e r / w reset value 00000000_00000000h vop_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 spare vbi_swap rsvd rgb_mode valid_sig inv_de_pol inv_vs_pol inv_hs_pol uv_swap vsync_shft dis_dec 601_mode vbi rsvd task sgfr sige sc120x_mode 422_mode ext_vip_codes vip_level vip_mode vop_config bit descriptions bit name description 63:32 rsvd (ro) reserved (read only). reads back as 0. 31:25 spare spare. 24 vbi swap vbi swap. when set to 1, swap upper and lower bytes of vbi data. 22:23 rsvd reserved. 21 rgb mode rgb mode. set this bit to 1 if rgb data sent: applicable in 24-bit 601 mode so as to choose correct blanking data. if this bit is se t, then blanking data is 0, otherwise it is yuv = 10, 80, 80. 20 valid sig (ro) valid signature (read only). if signature enabled, this bit can be read to determine if the signature is valid. 19 inv de pol invert display enable polarity. set to 1 to invert polarity of display enable (for 601 mode only).
460 amd geode? lx processors data book video processor register descriptions 33234h 18 inv vs pol invert vsync polarity. set to 1 to invert polarity of vsync (for 601 mode only). 17 inv hs pol invert hsync polarity. set to 1 to invert polarity of hsync (for 601 mode only). 16 uv swap uv swap. 0: no swap. 1: swap lowest byte with next lowest byte in [23:0] input data stream. this is essentially swapping the u and v, and if in rgb, swapping g and b. 15:14 vsync shft vsync shift . this is the number of vop clocks to shift the vsync with respect to hsync for odd field detection in 601 mode. 00: shift vsync earlier by 4 cycles (-4). 01: shift vsync earlier by 2 cycles (-2). 10: zero shift - both are aligned as they were received from display controller. 11: shift later based on programmable value in dc memory offset 080h. 13 dis dec disable decimation. this is used in conjunction with 601 mode for 24-bit yuv/rgb out- put on vop. 12 601 mode enable 601 mode . 0: disable. 1: enable. 11 vbi vertical blanki ng interval. when this bit is set to 1, the task bit (bit 9) is used to indi- cate vbi data. in bt.656 mode, the task bit (bit 9) in the eav/ sav is fixed at 1, if this vbi bit is set, then a value of 0 in the task bit location indicates vbi data. in vip 1.1 mode, the task bit in the eav/sav is defined such that 0 is vbi data, and 1 is active video data. therefore, this vbi bit has no effect in vip 1.1 mode. in vip 2.0 mode, the task bit determines t he value of the task bi t in the eav/sav. with the vbi bit set, the invers e of task indicates vbi data. 10 rsvd reserved. reads back as 0. 9 task task. value for the task bit in vip 2.0 mode. 8sgfr signature free run . 0: disable. if this bit was previously set to 1, the signature process will stop at the end of the current frame. 1: enable. if sige (bit 7) is set to 1, the signature register captures data continuously across multiple frames. 7sige signature enable. 0: disable. vp memory offset 808h[31:0] is reset to 0000_0000h and held (no capture). 1: enable. the next falling edge of vsync is counted as at the start of the frame to be used for crc checki ng with each pixel clock b eginning with the next vsync. if the sgfr bit (bit 8) is set to 1, the sig nature register captures the pixel data signature continuously across multiple frames. if sgfr is cleared to 0, a signature is capt ured for one frame at a time, starting from the next falling vsync. after a signature capture is complete, vp memory offset 808h[31:0] can be read to determine the crc check stat us. then proceed to reset the sige which initializes vp memory offset 808h[31:0] as an essential pr eparation for the next round of crc checks. vop_config bit descriptions (continued) bit name description
amd geode? lx processors data book 461 video processor register descriptions 33234h 6.8.3.52 video output po rt signature (vop_sig) 6 sc120x_mode sc120x compatible mode. creates eav/sav codes consistent with the amd geode? sc1200 and sc1201 processor?s vop. 0: normal mode. 1: sc1200/sc1201 compatible mode. set to 1 for bt.601 mode. 5:4 422_mode 4:4:4 to 4:2:2 conversion algorithm. selects which method is used to convert 4:4:4 data to 4:2:2. 00: 4:2:2 co-sited. 01: 4:2:2 interspersed (u,v sample s from respective co-samples). 10: 4:2:2 interspersed (u,v samples fr om alternating successive samples). 11: not used. 3 ext_vip_ codes extended vip sav codes. additional sav codes not defined in vip 2.0 spec, but used in numerous available other applications (also used in bt.656). 0: do not use extended codes. 1: use extended codes. note: selecting bt.656 mode (in bits [1:0]) automatically uses the extended codes. 2 vip_level vip 2.0 level selection. 0: vip 2.0 level i (8-bit), 601 8-bit. 1: vip 2.0 level ii (16-bit), 601 16-bit. 1:0 vip_mode vip mode. selects between vesa vip standards. 00: vop disabled (logic 0?s on data buses). 01: vip v1.1. 10: vip v2.0/ bt.601. selects vip v2.0 or bt.601 if 601 mode bit (bit 12) is set. 11: bt.656. vp memory offset 808h ty p e r o reset value 00000000_00000000h vop_config bit descriptions (continued) bit name description vop_sig register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 crc vop_sig bit descriptions bit name description 63:32 rsvd reserved. reads back as 0. 31:0 crc 32-bit crc. 32-bit signature when in 32-bit crc mode.
462 amd geode? lx processors data book video input port 33234h 6.9 video input port 6.9.1 features ? vesa 1.1, 2.0 and bt.601, bt.656 compliant, 150 mhz (excludes host interface). ? standard 9 or 17 pin interface (8/16 data + clock) ? 8/16-bit bt.656 video ? task a/b video and vbi (two video streams) ? 8/16-bit ancillary data ? hd capable (up to 1280x720 progressive scan, 1920x1080 interlaced) ? vip 1.1 compatible mode (8 bit) ? 8/16-bit bt.601 type input video with hsync and vsync ? 8-bit message and streaming video transfer mode ? (8 + clock + control on vid[10:8]) ? video data stored in linear or planar buffers ? even line or even field decimation (4:2:2 -> 4:2:0 transla- tion) ? automatic paging for multi-frame storage ? provides full frame buffer generation from interlaced input (weave) ? mutli-burst gliu packets (programmable) ? internal loopback using vop outputs as source data ? vip_sync_to_pin output pin to r equest next frame or data packet from external data source (genlock) ? vip_sync_to_vg output to dc/vp for frame synchroniza- tion (vsync indication) ? frame_to_vg output to dc/vp for frame synchronization (odd/even field indication) ? vip_int output for interrupt generation on frame/field/line boundaries 6.9.1.1 performance metrics ? system goals: ? 150 mhz video interface ? 400 mhz gliu interface ? adequate gliu bandwidth in hd capture mode (hd vip requires ~20 million qwords/sec) ? gliu latency requirements table 6-72. vip capabilities input output (to memory) memory storage supports task yuv 4:2:2 interlaced (8/16-bit) sd/hd yuv 4:2:2 linear, single frame buffer weave a or b yuv 4:2:2 planar, single frame buffer not applicable a or b yuv 4:2:2 linear, odd/even field buffers bob a or b yuv 4:2:2 planar, odd/even field buffers not applicable a or b yuv 4:2:0 planar, single frame buffer rotation/weave a or b yuv 4:2:0 planar, odd/even field buffers rotation/bob a or b yuv 4:2:2 progressive (8/16-bit) sd/hd yuv 4:2:2 linear, single frame buffer standard mode a or b yuv 4:2:2 planar, single frame buffer not applicable a or b yuv 4:2:0 planar, single frame buffer rotation a or b yuv 4:2:0 yuv 4:2:0 linear sc1200 compatible a or b vbi data (8/16-bit) vbi da ta linear vbi data a or b ancillary data (8/16-bit) anc data linear, circular buffer ancillary data n/a message data (8-bit only) msg data linear, dual buffers message data n/a streaming data (8-bit only) raw data linear, dual buffers raw data n/a
amd geode? lx processors data book 463 video input port 33234h 6.9.2 vip block descriptions figure 6-39. vip block diagram 8/16 address address formatter generator memory registers vip data vip clock vip clock control gliu clock gliu clock control vipclk gliu_clk input control qword = 64 bits take req reg write reg read mapped gliu interface clock control input output control dual port input ctl output ctl 16 bits capture ram vip int sync_to_pin sync_to_vg (256x64) video_ok field_to_vg vipsync vip vsync vip hsync vip clock gliu clock msr registers gliu write master gliu slave gliu planar mode: 512 byte(64 qwords) yuv, ancillary fifo linear mode: 1536 byte(192 qwords) video , 256 (64 qwords) byte ancillary fifo vip register block
464 amd geode? lx processors data book video input port 33234h 6.9.2.1 input formatter the input formatter receives 8- or 16-bit vip input data, it does a 4:2:2 to 4:2:0 translation (if enabled) and formats it into either linear data or planar data for storage in the cap- ture ram. 6.9.2.2 input control the input control block operates in either vip 2.0 16-bit mode, vip 2.0 8-bit mode, vip 1.1 compatible mode, mes- sage passing mode, data streaming mode, or bt.601 input mode. the input cont rol block decodes preamble and status from eav/sav and ancillary packets as well as start/stop control for message passing packets or hsync/ vsync timing in bt.601 like input mode and generates control to the input formatter and capture ram. video frame timing is decoded and passed on to the address generator and gliu. the vip in put state machine is imple- mented in the input control block. it should be noted that values from the configuration and control registers are synchronized to the video clock before being used by the input control block. the vip input control block contains: ? a state machine that keeps track of the video stream protocol. ? logic to infer the odd/even vbi/ancillary packet informa- tion necessary to store data in memory. ? sequencing control generation for the input formatter. ? generation of start and stop ca pture, as well as capture active status. ? line start and end logic. 6.9.2.3 vip capture ram the capture fifo is a 256 wordx64bit dual port ram. the input side is driven by t he vip clock. the output side is driven by the gliu clock. the memory is divided into a 192 qword buffer for video and a 64 qword buffer for ancil- lary data when linear buffers are defined in system mem- ory. it is partitioned into four 64 qword buffers when planar buffers are defined in system memory. one 64 qword buffer is used for each of the y, u, v and ancillary data types. data is stored in qwords. the watermark at which the fifo begins emptyi ng is programmable. gener- ally, a minimum of eight qwords are stored in a buffer before gliu write. this enables two consecutive burst write requests to be issued, which should provide the most effi- cient cycle times to system memory. programmable thresh- old level flags are available to monitor data levels. this should be helpful in debugging. memory bist is imple- mented and can be invoked from the jtag logic from a msrs. the memory can also be read/written using vip memory mapped registers. 6.9.2.4 vip register block the vip register block contains the address generator, msr registers and memory mapped registers. the address generator support s up to four data streams (y, cr, cb, and ancillary). each data stream has an inde- pendent logical fifo. the capture ram is partitioned into four fifos for planar storage mode (y, cr, cb, and ancil- lary) each being 64 qwords deep. in linear storage mode the capture ram is partitioned into two fifos (y = 192 qwords, ancillary = 64 qwords). four vip_output_addr blocks provide individual fifo management and the vip output control block controls the time-slicing of gliu request for each fifo. a separate buffer (system memory address) is maintained for each data type as described by table 6-74 on page 475. the video base addresses regis- ters are double buffered so address updates can be made for the next frame while the current frame is being pro- cessed. the memory mapped registers are contained in the vip register block. interrupt generation, and logic for updating the base registers at frame bou ndaries is also implemented in this block. 6.9.2.5 gliu interface the gliu provides a standard interface to the amd geode lx processor. the vip is both a write master and a slave on this bus. as a write master, the vip per forms write requests to send single beat writes, or a burst of four qwords to memory. the vip is considered a low-bandwidth isochronous mas- ter to the gliu. a fifo watermark threshold is program- mable, which allows the write transaction priority to be increased when the data count in the fifo exceeds the threshold. handshaking exists between the gliu master and the output control/addre ss generation blocks so that address and data is supp lied at the correct cycles. as a slave, the vip stores regi ster data from the gliu and returns register data being read by the gliu. bursts are not supported by the slave interface. both msrs and memory mapped registers are accessible through the slave inter- face. the front end control generates the per-byte write enables to all registers except the base registers.
amd geode? lx processors data book 465 video input port 33234h 6.9.3 functional description the video input port (vip) receives 8- or 16-bit video or ancillary data, 8-bit message data, or 8-bit raw video, and passes it to data buffers lo cated in system memory. the primary operational mode is as a compliant vip 2.0 slave. the vip 2.0 specification defines the protocol for receiving video, vbi, and ancillary data. the addition of the message passing and data streaming modes provide flexibility in receiving non-vip 2.0 compliant data streams. the vip is essentially a dma engine. input data is packed into qwords, buffered into a fi fo, and sent to system mem- ory over the gliu. the vip masters the internal gliu and transfers the data from the fifo to system memory. the maximum input data rate (8 or 16 bits) is 150 mhz. the glbus (64 bits) operates from 200-400 mhz correspond- ing to the ddr clock rate to external memory. the vip can successfully input line sizes as small as 12 clocks with 20 clocks of blanking, with a 16-bit data/100 mhz vip clock rate at 400 mhz gliu, when the vip's prior- ity is equal to that of the dc. the limitation has to do with the total line length (active data + blanking time). any size of active data can be received if a reasonable amount of blanking is provided. the above case corresponds to a 6- pixel line. this is likely smaller then anything that realisti- cally will be received (and at a higher frequency then the 75 mhz max). the vip line size limitation is determined by the input frequency and the gliu latency. the worst case is with a high frequency vip clock and low frequency gliu clock in a busy system. the vi p fifo line wrap interrupt (int) is generated if the line is not received correctly. if this int occurs, vip priority should be increased and/or the blanking time of the input line increased. as there is no specification/requirement re garding vip minimum line size, it is recommended that any non-standard input have ~100 clocks of blanking. this prevents any special priority requirements for ?postage stamp? size frames. 6.9.4 vip operation modes the vip provides direct hardware compatibility with the vesa 2.0 standard (vip 2.0), level ii. vip 2.0 data is a simplified bt.656 video format. the simplification is due to vip only having to receive data. (vip does not concern itself with specific frame timi ng) the data the vip receives is only stored in system memory . in addition to receiving bt.656 video format data, the vip can also receive 8-bit message data and 8-bit streaming data, allowing the amd geode cs5536 companion device connected to the vip to load data directly into the amd geode lx proces- sor?s system memory. the message passing and data streaming modes are not defi ned in the vesa 2.0 specifi- cation. the vipsync output provides a software controlled output that can be used for frame/data synchronization with output devices that support da ta throttling. vip must be configured to receive specific data types. the following input modes are supported by the vip. ? mode 1a - vip 1.1 compatible mode (bt.656 data with following notes): ? task bit is used to indicate vbi data within the video stream (t = 0 for vbi data, t = 1 for active video). ? video data is stored in the task a video base address. vbi data is saved in the task a vbi base address. ? video flags t, f, and v can only be changed in the eav code. ? during vertical blanking there must be a minimum of one sav/eav scan line. ? 8-bit data only (eav/sav packets + ancillary data packets). ? mode 1b - 8-bit vip 2.0 level i mode (bt.656 data with following notes): ? video flags t, f, and v are valid in the eav and sav code, valid values must appear no later then the sav of the first scan line of the next active region. ? task bit differentiates between two video streams. these streams can be interleaved at a scan or field rate. ? v bit differentiates between active video and vbi data (v = 1 for vbi data, v = 0 for active video). ? during vertical blanking there must be a minimum of one sav/eav scan line. ? new video flags - the p nibble is redefined as [non_int,repeat,rese rved,ext_flag]. ? 8-bit data only (eav/sav packets + ancillary data packets). ? mode 1c - 16-bit vip 2.0 leve l ii mode (bt.656 data with following notes): ? video flags t, f, and v are valid in the eav and sav code, valid values must appear no later then the sav of the first scan line of the next active region. ? task bit differentiates between two video streams. these streams can be interleaved at a scan or field rate. ? v bit differentiates between active video and vbi data (v = 1 for vbi data, v = 0 for active video). ? during vertical blanking there must be a minimum of one sav/eav scan line. ? new video flags - the p nibble is redefined as [non_int,repeat,rese rved,ext_flag]. ? 16-bit data only (eav/sav packets + ancillary data packets). ? mode 2 - message passing mode (8-bit): ? vip_vdata[8] = start_msg, vip_vdata[9] = end_msg. ? 8-bit data only. ? mode 3 - data streaming mode (8-bit): ? vip_data[8] = start_ msg, vip_vdata[9] = vip_data_enable. ? 8-bit data only. ? mode 4 - bt.601 mode (8/16-bit): ? no sav/eav recognition. input timing based on vsync and hsync inputs. ? hsync input on pin ldemod, vsync input on pin vdden. ? tft output mode cannot be used when vip is config- ured in bt.601 mode.
466 amd geode? lx processors data book video input port 33234h 6.9.5 mode 1a,b,c - vip input data (simplified bt.656) the vip 2.0 specification describes an 8- or 16-bit data stream incorporating both control and data. the data/con- trol is delivered in packets. there are two different packet types, sav/eav and ancillary packets. the specification also requires backwards compatibility to vip 1.1 data for- mats. three different vip data modes are supported: vip 1.1 compatible mode , vip 2.0 8-bit mode, and vip 2.0 16- bit mode. differences in these modes are noted in the descriptions of the different packet types in section 6.9.5.1 on page 466. 6.9.5.1 sav/eav packets the sav/eav packets begin with 3 bytes of preamble fol- lowed by a start of active video (sav) status word. active data follows. the packet ends with the reception of another 3 bytes of preamble followed by an end of active video (eav) status word. the preamble consists of ff- 00-00. the codes ff and 00 codes are prohibited as video samples and reserved for header and synchronization pur- poses. the code 00 can be used within a packet to mark an empty cycle. if a 00 code appears between the sav and eav, that sample is ignore. note that in 16-bit mode, only the 8 lsbs are checked. if 00, the entire 16-bit word is ignored. the preamble and status word always occurs on bits [7:0] of the input data, even in 16-bit mode. the active data is received on bits [7:0] in 8-bit mode and on bits [15:0] in 16-bit mode. the y va lues appear on bits [7:0] and cx values on bits [15:8]. both active video and vbi data are received in sav/eav packets. the format of the sav and eav preamble and status word is shown in table 6-73. a sample sav/eav line is shown in figure 6-40 on page 467. a full frame is shown in figure 6-41 on page 468. the status word provides the raster reference information: vip 1.1 compatible mode: ? video flags t, f, and v can only be changed in the eav code per the vip 1.1 specification. these flags are only captured in the eav code. ? in vip 1.1, the task bit is used to indicate vbi data within the video stream (t = 0 for vbi data, t = 1 for active video). in vip 1.1 mode, the task bit is used in place of the v bit to indicate vbi data. ? p3-p0 are ignored. vip 2.0 modes (8- or 16-bit data): ? video flags t, f, and v are valid in the eav and sav code. valid values must appear no later then the sav of the first scan line of the next active region. ? task bit differentiates between two video streams. these streams can be interleaved at a line or field rate. ? v bit differentiates between active video and vbi data (v = 1 for vbi data, v = 0 for active video). ? new video flags - the p nibble is redefined as [non_int,repeat,rese rved,ext_flag]: ? non_int: 1 = non-interlaced source, 0 = inter- laced source (not used). ? repeat: 1 = repeat field in 3:2 pull-down, 0 = not a repeat field (repeat fields can be ignored by vip). the repeat flag must be set in the sav for every line in the field. the line will be saved to memory if the repeat flag is not set. (this function needs to be enabled in vip memory offset 04h[29]). ? ext_flag: 1 = extra flag byte follows this eav, 0 = no extra flag byte (not implemented). table 6-73. sav/eav sequence parameter d7d6d5d4d3d2d1d0 preamble 11111111 00000000 00000000 status word t f v h p3 p2 p1 p0 t = task bit 0 = task b 1 = task a f = field id 0 = odd 1 = even v = vertical blanking 0 = active video 1 = vertical blanking h = horizontal blanking 0 = active line 1 = horizontal blanking p3-0 = reserved in vip 1. 1, new flags in vip 2.0
amd geode? lx processors data book 467 video input port 33234h vip 2.0 video flags two new video flags are defined in the vip 2.0 specification to decode whether the input video is interlaced or noninter- laced and whether the data is merely a repeated field. these flags are meant to enable vip to handle bob and weave, as well as 3:2 pull down in hardware. the new flags are embedded in the lower nibble of the sav and eav header. the non-interlace flag non_int (bit 3 of the status word) is ignored by the vip. the video stream must be known and the software must set up the appropriate base and pitch addresses to store the video into system mem- ory. the repeat flag (bit 2 of the status word) can be decoded by the vip if the feat ure is enabled in the vip control register 2 (vip me mory offset 04h[29]). the repeat flag is set during 3:2 pull down. in 3:2 pull down, fields are repeated to increase the frame rate. the vip ignores fields (lines) with the repeat flag set. this reducers the amount of data being tr ansferred to system memory, reducing overall bandwidth requirements. additional flag bytes are also supported in the vip 2.0 specification. these extra flag bytes can only occur during eav (not sav). the vip ignores extra flag bytes. note: since the extra flag byte can only occur during eav, they can be ignored without effecting the reception of following sav/eav packets. . figure 6-40. bt.656, 8/16-bit line data f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b c r yyc b c r y eav code sav code 4 horizontal blanking 4 active video start of digital line 4:2:2 sampled video data f f 0 0 0 0 x y eav code f f 0 0 0 0 r p 8 0 1 0 8 0 1 0 8 0 1 0 f f 0 0 0 0 r p yy yyyy y f f 0 0 0 0 r p x x x x x x x x 8 0 1 0 8 0 1 0 8 0 1 0 x x x x x x x x c b c b c b c b x x x x x x x x 8-bit vip data 16-bit vip data 4 horizontal blanking 4 active video c r c r c r 4 eav code sav code 4:2:2 sampled video data eav code vip_data[7:0] vip_data[7:0] vip_data[15:8] (vip 2.0 level ii) (vip 1.1 and vip 2.0 level i)
468 amd geode? lx processors data book video input port 33234h figure 6-41. 525 line, 60 hz digital vertical timing line 1 (v = 1) line 20(v = 0) line 264 (v = 1) line 283 (v = 0) line 525 (v = 0) blanking field 1 active video blanking field 2 active video line 4 line 266 line 3 field 1 (f = 0) odd field 2 (f = 1) even h = 1 eav h = 0 sav line number f v h (eav) h (sav) 1-3 1 1 1 0 4-19 0 1 1 0 20-263 0 0 1 0 264-265 0 1 1 0 266-282 1 1 1 0 283-525 1 0 1 0 (vbi data) (vbi data) in vip 1.1 mode, the t,f,v video flags are only captured from t he eav code. in vip 2.x modes, these flags are captured from both the sav and the eav codes. (the h bit is always captured to distinguish between and sav and eav code). note that for vip 1.1 mode, there must be a minimum of one sav/eav scan line during vertical blanking in order for the vblank flag to transition from 0->1->0. an end-of-frame event is detected the same in vip 1.1 and vi p 2.0 modes. (a 0->1 transition of vblank when f = 1 causes an end-of-frame event during interlaced video, a 0->1 transition of v-blank causes an end-of-frame event during progressive scan video) an end-of-frame event is used for starting/stopping capture and for updating bu ffer addresses. line #1 of a frame does n ot necessarily coincide with the end-of-frame event. line #1 is specified differently with respect to vblank depending on the fram e type (resolution/interlaced/...). when line#1 is defined other then on the falling transition of vblank, vbi data received afte r the v- blank transition will be stored in updated buffer addres s. vbi data is generally not sent during this time.
amd geode? lx processors data book 469 video input port 33234h 6.9.5.2 ancillary packets ancillary packets are received during vertical and/or hori- zontal blanking. the ancillary packet has a 6-byte header of 00-ff-ff-did-sdid-nn. t he first three bytes are the pre-amble. the did and sdid bytes are the data identifier and the secondary data identifier bytes. the nn byte is the data count and specifies the length of the ancillary data block in dwords (4-byte blocks). the entire ancillary data packet is stored to memory, including all 6 bytes of pream- ble/header. see section 6.9.10 on page 475 for further explanation. there is no restriction on the code in the data section of the packet (codes 00 and ff are allowed) the sav/eav packet preamble detection circuitry is disabled during the reception of these nn blocks of data to allow reception of 00, ff codes. the active data is received on bits [7:0] in 8-bit mode, [9:0] in 10-bit mode and on [15:0] in 16-bit mode. a sample ancillary packet is shown in figure 6-42. figure 6-42. ancillary data packets 0 0 f f f f d i s i n n 6 byte ancillary header dd first dword last dword i d0 d1 d2 d d d d d check sum fill byte 0 0 f f f f d i s i dd first last d0 d2 d4 d6 ddddd check xxxx xx d1 d3 d5 d7 ddddd fill byte d d dword 6 byte ancillary header n n 8/10-bit ancillary packet 16-bit ancillary packet sum d d i d d dword vid[7:0] vid[7:0] vid[15:8]
470 amd geode? lx processors data book video input port 33234h 6.9.6 message passing mode the message passing mode (msg) allows an external device to pass raw data packets to the amd geode lx pro- cessor system memory (see figure 6-43). in message passing mode, vid8 is redefined as a start message indi- cation and vid9 is redefined as an end message indica- tion. video data reception (sav/eav packets and ancillary packets) is disabled while in message passing mode. 6.9.7 data streaming mode the data streaming mode (strm) allows an external device to pass raw data to the processor system memory (see figure 6-44). when in data streaming mode, the vid9 data pin is redefined as a data_valid control input. vid8 is the start_msg indica tor. the vip stores all data during the time that the data _valid input is active. the data is stored sequentially into system memory. figure 6- 44 shows the data streaming format. video data reception (sav/eav packets and ancillary packets) is disabled while in data streaming mode. figure 6-43. message passing data packet figure 6-44. data streaming data packet vip_data[7:0] start_msg end_msg (vid[8]) (vid[9]) d0 d1 d2 d3 d4 d5 d6 d7 xx xx xx xx xx vip_data[7:0] data_valid (vid[9]) d0 d1 d2 d3 d4 d5 d6 d7 xx xx xx xx xx start_msg (vid[8])
amd geode? lx processors data book 471 video input port 33234h 6.9.8 bt.601 mode bt.601 mode allows reception of 8- or 16-bit video input which consists of hsync, vsync, and 8/16 bit data. verti- cal and horizontal start/stop registers provide the informa- tion for data capture in each field/frame. the bt.656 sav/ eav codes (if present) are ignored. frame/line timing is derived from the hsync and vsync inputs only. odd/ even field is determined by the leading edges of vsync and hsync. default field detection is shown in figure 6- 45. a detection window is programmable using the vip memory offset 50h. if the leading edge of vsync occurs within the window, the field is odd. if the leading edge of vsync occurs outside the window, the field is even. the vip memory offset 50h default value requires that the hsync and vsync leading edges occur simultaneously for odd field detection (see figure 6-46 on page 472). the horizontal and vertical input timings of the input video frame are also programmable. see figure 6-47 and figure 6-48. figure 6-45. bt.601 mode default field detection hsync vsync active low hsync/vsync (hsync polarity = 0 / vsync polarity = 0) active high hsync/vsync (hsync polarity = 1 / vsync polarity = 1) vsync hsync (for odd field) (for even field) even field odd field line #1 line #1 even field odd field (line #1) (line #1) even field (line #2) odd field (line #2) vsync vsync (for odd field) (for even field) even field odd field even field odd field (line #1) (line #1) even field (line #2) odd field (line #2) odd field is indicated when leading edge of vsync and the leading edge of hsync occur simultaneously (vip allows for a programmable detection window for odd field). even field is indicated when leading edge of vsync occurs prior to the leading edge of hsync.
472 amd geode? lx processors data book video input port 33234h . figure 6-46. bt.601 mode programmable field detection figure 6-47. bt.601 mode horizontal timing hsync vsync odd_field_detect_start field_detect_duration active low hsync/vsync (hsync polarity = 0 / vsync polarity = 0) active high hsync/vsync (hsync pola rity = 1 / vsync polarity = 1) vsync (for odd field) (for even field) even field odd field line #1 hsync vsync odd_field_detect_start field_detect_duration vsync (for odd field) (for even field) even field odd field line #1 a = 3 b = 12 a - horizontal_start for 601 (vip memory offset 3ch) clk hsync b - horizontal_end for 601 (vip memory offset 38h) video data * clock #1 occurs at leading transition of hsync 2 1* 3 d2 d3 d4 d5 d6 4 d1 10 11 5 6 7 8 9
amd geode? lx processors data book 473 video input port 33234h figure 6-48. bt.601 mode vertical timing 6.9.9 yuv 4:2:2 to yuv 4:2:0 translation the vip provides the option to translate incoming 4:2:2 co- sited video to yuv 4:2:0. the u and v values of even lines are simply discarded. no filter ing is performed. vip stores the 4:2:0 data to system memory in a planar format. in pla- nar format, the y, u, and v data is partitioned into separate buffers. a single y, u, v buffer (three buffers) can be used in the case of progressive scan or with interlaced data when using weave. two sets of buffers (six buffers) are used to store the odd and even field data separately when using the bob method of de-interlacing. figure 6-49 on page 474 illustrates the positioning of the ycbcr samples for the 4:2:2 and 4:2:0 formats when: 1) receiving a progressive scan frame. 2) receiving interlaced odd and even fields for use with the bob display mode. 3) for receiving odd and even fields with the weave dis- play mode. in addition to the standard 4:2:2 translation, vip can also decimate all u/v values in the even field. c = 4 d = 7 e = 4 f = 7 hsync vsync (even field) vsync (odd field) c - vertical_start for 601 odd field (vip memory offset 6ch[11:0]) d - vertical_end for 601 odd field (vip memory offset 6ch[27:16]) e - vertical_start for 601 even field (vip memory offset 48h[11:0]) f - vertical_end for 601 even field (vip memory offset 48h[27:16]) video data ** frame timing starts at leading edge of vsync 12345678 g = 2 h = 3 vsync g - vbi_start for 601 (vip memory offset 44h[11:0]) h - vbi_end for 601 (vip memory offset 40h[11:0]) vbi data
474 amd geode? lx processors data book video input port 33234h figure 6-49. yuv 4:2:2 to yuv 4:2:0 translation 1 2 4 6 3 5 7 1 2 4 6 3 5 7 yuv 4:2:2 yuv 4:2:0 123 456 123 456 1 2 4 3 1 [1] [2] [3] 2 3 4 y sample cb,cr sample yuv 4:2:2 yuv 4:2:0 123 456 123 456 [1] [2] [3] 123 456 1 2 4 3 1 [1] [2] [3] 2 3 4 yuv 4:2:2 yuv 4:2:0 123 456 123 456 5 6 7 progressive scan - discard even line uv values interlaced (weave) - discard even line uv values in both input fields (single frame buffer in system memory) (odd and even field buffers in system memory) interlaced (bob) - discard even line uv values in both input fields (single frame buffer in system memory)
amd geode? lx processors data book 475 video input port 33234h 6.9.10 software model the vip receives data and st ores it into system memory. the vip input modes with associated data types are shown in table 6-74. vip 2.0 is the vesa vip 2.0 level i (8-bit) standard or the vesa vip 2.0 le vel ii (16-bit) standard. vip 1.1 is the vesa (8-bit) standard in which only a single video stream is supported and the task bit is used to dis- tinguish between video and vbi data. msg is the 8-bit message passing mode, and strm, the data streaming mode, provides support for generic 8-bit data streaming. msg and strm modes are proprietary data transfer for- mats and are not defined in the vesa vip specification. table 6-74 defines the data types received in each mode. vip 2.0 supports nine different data types. this allows reception of two separate video streams (task a and b) plus ancillary data. vip 1.1 mode supports five data types (task a only). one data type is associated with the msg and strm modes. table 6-74. vip data types / memory registers mode data type t f v (flags) base register pitch/size register planar registers vip 2.0 task a, odd field, active video 1 0 0 vip_task_a_vid_odd_base vip_task_a_vid_pitch vip_task_a_u_offset vip_task_a_v_offset task a, even field, active video 1 1 0 vip_task_a_vid_even_base vip_task_a_u_offset vip_task_a_v_offset task a, odd field, vbi 1 0 1 vip_task_a_vbi_odd_base n/a task a, even field, vbi 1 1 1 vip_task_a_vbi_even_base n/a task b, odd field, active video 0 0 0 vip_task_b_vid_odd_base vip_task_b_vid_pitch vip_task_b_u_offset vip_task_b_v_offse task b, evenfield, active video 0 1 0 vip_task_b_vid_even_base vip_task_b_u_offset vip_task_b_v_offse task b, odd field, vbi 0 0 1 vip_task_b_vbi_odd_base n/a task b, even field, vbi 0 1 1 vip_task_b_vbi_even_base n/a ancillary n/a vip_anc_msg_1_base vip_anc_msg_size n/a vip 1.1 task a, odd field, active video 1 0 0 vip_task_a_vid_odd_base vip_task_a_vid_pitch vip_task_a_u_offset vip_task_a_v_offse task a, even field, active video 1 1 0 vip_task_a_vid_even_base vip_task_a_u_offset vip_task_a_v_offse task a, odd field, vbi 0 0 1 vip_task_a_vbi_odd_base n/a task a, even field, vbi 0 1 1 vip_task_a_vbi_even_base n/a ancillary n/a vip_anc_msg_1_base vip_anc_msg_size n/a bt. 601 task a, odd field, active video 1 0 0 vip_task_a_vid_odd_base vip_task_a_vid_pitch vip_task_a_u_offset vip_task_a_v_offse task a, even field, active video 1 1 0 vip_task_a_vid_even_base vip_task_a_u_offset vip_task_a_v_offse task a, odd field, vbi 0 0 1 vip_task_a_vbi_odd_base n/a task a, even field, vbi 0 1 1 vip_task_a_vbi_even_base n/a msg message passing n/a vip_anc_msg_1_base, vip_anc_msg_2_base vip_anc_msg_size n/a strm data streaming n/a vip_anc_msg_1_base, vip_anc_msg_2_base n/a
476 amd geode? lx processors data book video input port 33234h 6.9.10.1 video data buffers video data buffers can be organized in linear or planar for- mats. linear buffers pack yuv values contiguous in mem- ory. planar buffers have separate subbuffers for each set of yuv values in a field or frame. the vip control 1 register (vip memory offset 00h[4]) determines if the video storage format is linear or planar. in linear format, the first video line is stored beginning at the vid_base address, the second line is stored beginning at vid_base + pitch, the third line at task_base + (2 x pitch) and so on until the end of the field/frame. see figure 6-51 on page 477 for an example of a 4:2:2 sav/eav packets stored in system memory in a linear format. in planar format, the y buffer begins at the task_base address, the u buffer begins at the (vid_base + u_buffer_offset), and the v values start at the (vid_base + v_buffer_offset). the pitch value for y is vid_pitch. the pitch value for v and u is task_a_uv_pitch (for task a uv data) or task_b_pitch/2 (task b uv data). in 4:2:2 or 4:2:0 video, there are twice as many y data values per line as there are u or v values. additional odd/even offsets and pitch registers are provided for task a data. input u/v val- ues can be decimated (even lines or even fields). this fur- ther reduces the u and v data to 1/4 of the y data. see figure 6-51 on page 477 and figure 6-52 on page 478 for examples of sav/eav packets stored in linear buffer and planar buffer format. 6.9.10.2 vbi data buffers the vbi data packets are stored in linear format. vbi data is essentially a line of video that occurs during vertical blanking. the first vbi line is stored beginning at vbi_base, the second line is stored beginning at vbi_base + vid_pitch, the third line at vbi_base + (2 x vid_pitch) and on until the end of the vertical blanking period. 6.9.10.3 ancillary data buffers ancillary data packets are stored starting at the buffer address defined by anc_msg_1. packet storage continues to address anc_msg_1 + anc_msg_size at which point the address is wrapped back around to anc_msg_1. when a new packet is received, the packet count is incremented. when software reads a packet from the buffer, it decre- ments the count by writing a 1 to the decrement ancillary packet count bit in the vip status register (vip memory offset 08h[18]). ancillary data packets include a checksum. after packet reception, the internally generated checksum is compared to the checksum sent with the ancillary packet. if these val- ues do not compare, the packet is marked bad by writing a f0 in fill byte immediately following the checksum byte (8/ 16 ancillary data) or a 1111 in bits [15:12] of the checksum dword for 10-bit ancillary data. parity checking is also performed on the did, sdid, nn, and checksum words. packets with parity errors set the same error bits as when a checksum error occurs. parity and checksum errors are reported in the vip status register (vip memory offset 08h). they share a status bit. parity checking can be dis- abled via the ancpen bit in control register 2 (vip mem- ory offset 04h[26]). figure 6-53 on page 479 shows an example of ancillary packets stored in system memory. 6.9.10.4 message passing/ data streaming modes the msg and strm modes provide a mechanism for the amd geode cs5536 companion device to send raw data to the amd geode lx processor system memory. msg and strm modes have identical software models. two buffers are used (see figure 6-50). the vip_anc_msg_1_base and vip_anc_msg_2_base registers (vip memory offset 58h and 5ch) define the two buffer locations. the vip_anc_msg_size register (vip memory offset 60h) defines the maximum size of each buffer. the first packet (data associated with a start/end indication) is saved starting at msg_1_base address. the mb bit in control register 1 (vip memory offset 00h[18]) determines when buffer swapping occurs. when mb = 0, buffers are swapped each packet. when mb = 1, buffers are only swapped when full. this mode might be used if a continuous data stream is being delivered. a message buffer full interrupt occurs when a buffer swap occurs. software can read the vip status register to determine which buffer or buffers are full. software must reset the bit in order for the buffer to become available. the msg buffer error status bit (bit 14) is set when a buffer swap occurs from buffer 1 to buffer 2 with buffer 2 being unavailable or if a buffer swap occurs from buffer 2 to buffer 1 with buffer 1 being unavailable. figure 6-50. dual buffer for message passing and data streaming modes buffer 1 in use buffer 2 in use buffer1_full/ buffer2_full buffer overrun buffer2_full buffer1_full buffer2_full# buffer1_full# mode_2 or mode_3 new pkt or new pkt
amd geode? lx processors data book 477 video input port 33234h figure 6-51. example vip yuv 4:2:2 sav/eav packets stored in system memory in a linear buffer 0 1 2 3 vid_base (buffer start) cb y cr y line 1 start line 2 start line 3 start * line is 00 filled if not qword aligned cb y cr y cb y cr y cb y cr y cb y cr y 00* 00* 00* 00* cb y cr y cb y cr y cb y cr y cb y cr y cb y cr y 00* 00* 00* 00* cb y cr y vid_base + vid_pitch vid_base + 2 x vid_pitch * similar buffer can exist for task a odd video, task a even video, task b odd video, task b even video, task a odd vbi data, task a even vbi data, task b odd vbi data, task b even vbi data
478 amd geode? lx processors data book video input port 33234h figure 6-52. example vip yuv 4:2:0 planar buffer (all base registers are 8-byte aligned) u buffer v buffer line #1 y values y pitch = task_a_vid_pitch y buffer task_a_uv_pitch + u_buffer_even_offset +v_buffer_even_offset line #1 u values line #1 v values vid_base vid_base vid_base ** similar buffers can exist for task a even video note: line lengths, which are not divisible by 8, will re sult in an odd number of u and v data for each line. when this occurs, the fill values used (for qword boundaries) may not be 00. this occurs only if non-standard video formats are used. th e non 00 data is not part of the line. ** odd/even de-interlacing is not supported for task b (task b shares pointers between odd/even fields) u pitch = task_a_u_pitch v pitch = task_a_v_pitch
amd geode? lx processors data book 479 video input port 33234h figure 6-53. example vip 8/16- and 10-bit ancillary packets stored in system memory 0 1 2 3 (8-byte aligned) 00 ff ff did sdid nn=4 data data data data data data data data data data data data data data packet 1 start - buffer start packet 2 start 00 ff ff did sdid nn=6 data data data data data data data data data data data data data data data data data data data data data data 00* cs data data packet 3 start * packet is 00 filled to qword aligned address anc_message_base 00* cs data data * packet is 00 filled if not qword aligned sid nn=7 data data 0 1 000 3ff did sdid nn=4 data data data data packet 1 start - buffer start packet 2 start sdid nn=8 data data data data data data data data packet 3 start * packet is 00 filled to qword aligned address 00* cs * packet is 00 filled if not qword aligned 3ff 2 3 cs 000 3ff 3ff did 00* 000 3ff 8/16-bit ancillary data 10-bit ancillary data
480 amd geode? lx processors data book video input port 33234h 6.9.11 bob and weave bob and weave are two methods of outputting interlaced video, captured by the vip, in a progressive scan format. an example of this is when vip receives 30 hz interlaced (ntsc format) and the data is to be displayed on a tft panel that requires progressive scan with a 60-85 hz refresh rate. in the bob method, vip stores the odd and even fields in separate buffers. this uses less bandwidth since each field is line doubled by the display controller, and displayed as a full frame. the disadvantage is that there are some observable visual effects due to the reduc- tion in resolution. in the weave method, vip assembles a full frame from the two fields. the display controller then displays a full resolution frame. this requires more band- width. 6.9.11.1 bob in the bob method, vip saves the even and odd fields in separate buffers. the vip field interrupt is enabled to indi- cate to software when a field has been completed. a field status bit is available that indicates whether an odd or even field was received. software can manage these field buff- ers so that the display c ontroller always accesses fully assembled field data. 6.9.11.2 weave in the weave method, vip assembles the odd field and even fields together to form the complete frame in system memory. since both fields are rendered simultaneously, the frame must be double buffered. this allows vip to render a frame while the display controller is outputting a previous frame. to assemble the odd and even fields into a single frame, the vip must be setup such that the video data odd base address is separated from the video data even base address by one horizontal line. the video pitch register must be programmed with the value of two horizontal lines. the vip field interrupt is enabled to indicate to software when each field has been completed. a field status bit is available that indicates whether an odd or even field was received. software can manage these field/frame buffers so that the display controlle r always accesses fully assem- bled frame data. 6.9.12 vip interrupts software applications need synchronization events and input error indications from the vip to manage video dis- play and processing. interrupt s are generated by the vip in the form of interrupts (int ) and/or asynchronous system management interrupts (asmi). the following events can generate an int or asmi. thes e ints/asmis are disabled at power-up. fifo line wrap error - in cases where minimum line sizes are input with a low gliu frequency and high gliu latency, there is a potential error condition where the vip can receive a third line of video before the first line has been completely output. vip can not handle more then two lines of video in its fifo. if this condition occurs, the input video line size should be increased by increasing the blanking time between each line. fifo overflow error - fifo overflows can occur if gliu latencies become too long. if a fifo overflow occurs, the vip automatically rese ts the fifo. data in the fifo is dis- carded. video reception begins again at the start of the next line. no software intervention is required. this int is generated to indicate that a fifo overflow occurred. a high frequency of these interrupts is likely an indication of sys- tem bandwidth issues. fifo threshold hit - the fifo threshold hit is a program- mable count that gets compared to the number of words in a fifo. if the fifo da ta level surpasses the fifo threshold, then a fifo threshold hit int is generated. the request priority level is also elevated to its high value. sep- arate threshold values exist for video and ancillary data. this int may be enabled for debug to determine if potential bandwidth issues are ef fecting video capture. runaway line (> 3000 clocks) error - this error occurs when a sav code occurs, but a corresponding eav does not. vip memory offset 00 h[23] (err_detect) must be set to 1 to enable the runaway line error. a runaway line error causes video reception to stop. video reception starts again at the beginning of the next line.
amd geode? lx processors data book 481 video input port 33234h vertical timing error (frame or address error) /mes- sage missed error - this error indicates a frame error or an address error. a frame error occurs when the time between vsyncs exceeds the window defined by the vip_sync_err_count regist er (vip memory offset 78h). the vip_sync_err_count register must be pro- grammed. an address error occurs when the gliu address equals or exceeds the address programmed in the vip_max_addr register (vip memory offset 14h). the a_err_en bit must be enabled (vip memory offset 04h[30] = 1). an address error causes data reception to stop. the a_err_en must be set to a 0 to reset the address error so data reception can restart. setting the vrst bit in control register 1 also resets the address error (vip memory offset 00h[0]. active pixels per line error - this error is only valid when receiving bt.656 data. this int indicates that the amount of active data received between sav and eav codes is not the same from one line to the ne xt. this indicates that there is a problem in the video input data stream. vip clock input error - this error indicates that the vip input clock has stopped for 128 gliu clocks. ancillary checksum or parity error - this error indicates that a checksum value on an ancillary packet was wrong or the parity on an ancillary packet was wrong. the ancillary parity check can be disabled by setting the ancpen bit to 0 (vip memory offset 04h[26] = 0). message buffer full or ancillary threshold packet count reached - when in message passing mode, this indicates that a message buffer swap has occurred. the status register can be read to find out which message buffer has been filled. when in a video mode, this indicates that the number of outst anding ancillary packets has reached the threshold count programmed in vip memory offset 60h. end of vertical blanking - indicates that a falling edge of vblank has occurred. start of vertical blanking - indicates that a rising edge of vblank has occurred. start of even field - indicates that the start of the even field has occurred (for interlaced video data only). start of odd field - indicates that the start of the odd field has occurred (for interlaced video data only). current line = vip line target - indicates that the video line number programmed in the vip current/target register (vip memory offset 10h) has been reached. 6.9.13 vip input video status the vip checks the input video for conditions that could indicate an invalid data stream. these indications are pro- vided to software via interrupts. another component of the video detection story is the generation of the video_ok sig- nal to the dc. when in genlock mode, the vip transfers video data to memory and synchronously to the dc extracting the video from memory and sending it on to a display. if the video data is interrupted, the dc needs to know so that it can switch ov er to internally generated tim- ing and data. the video_ok signal provides the indication that the video data being received by the vip is ok. the err_detect bits (vip memo ry offset 00h[23:20]) are used to enable/disable the specific checks. when an error occurs, the video_ok signal remains 0 until the error is reset by clearing the associated interrupt pending bit in the vip interrupt register (vip memory offset 0ch). the follow- ing checks on the video data can be performed. ? clock input error - enabled when bit 20 = 1 ? line input error - enabled when bit 21 = 1 ? runaway line input error - enabled when bit 23 = 1 ? vertical timing error - enabled when bit 22 = 1 ? address error (vip memory offset 04h[30] must = 1) - enabled when bit 22 = 1
482 amd geode? lx processors data book video input port register descriptions 33234h 6.10 video input port register descriptions the registers associated with the vip are the standard geodelink device (gld) msrs (accessed via the rdmsr and wrmsr instructions) and vip configuration/control registers. table 6-75 and table 6-76 are register summary tables that include reset values and page references where the bit descriptions are provided. note: the msr address is derived from the perspective of the cpu core. see section 4.1 "msr set" on page 45 for more details on msr addressing. table 6-75. standard geodelink? device msrs summary msr address type register name reset value reference 54002000h ro gld capabilities msr (gld_msr_cap) 00000000_ 0003c4xxh page 484 54002001h r/w gld configuration msr (gld_msr_config) 000000000_ 00000000h page 484 54002002h r/w gld smi msr (gld_msr_smi) 000000000_ xxxx7fffh page 485 54002003h r/w gld error msr (gld_msr_error) 000000000_ 00000000h page 486 54002004h r/w gld power management register (gld_msr_pm) 000000000_ 00000005h page 487 54002005h r/w gld diagnostic msr (gld_msr_diag) 000000000_ 00000000h page 487 table 6-76. vip configuration/control registers summary vip memory offset type register name reset value reference 00h r/w vip control register 1 (vip_ctl_reg1) 42000001h page 488 04h r/w vip control register 2 (vip_ctl_reg2) 00000000h page 490 08h r/w vip status (vip_status) xxxxxxxxh page 492 0ch r/w vip interrupt (v ip_int) xxxxfffeh page 494 10h r/w vip current/target (vip_cur_tar) 00000000h page 495 14h r/w vip max address (vip_max_addr) ffffffffh page 495 18h r/w vip task a video even base address (vip_task_a_vid_even_base) 00000000h page 496 1ch r/w vip task a video odd base address (vip_task_a_vid_odd_base) 00000000h page 496 20h r/w vip task a vbi even base address (vip_task_a_vbi_even_base) 00000000h page 497 24h r/w vip task a vbi odd base address (vip_task_a_vbi_odd_base) 00000000h page 497 28h r/w vip task a video pitch (vip_task_a_vid_pitch) 00000000h page 498 2ch r/w vip control register 3 (vip_contrl_reg3) 00000020h page 498 30h r/w vip task a v offset (vip_task_a_v_offset) 00000000h page 499 34h r/w vip task a u offset (vip_task_a_u_offset) 00000000h page 500 38h r/w vip task b video even base/horizontal end (vip_task_b_vid_even_base_horiz_end) 00000000h page 500 3ch r/w vip task b video odd base/horizontal start (vip_task_b_vid_odd_base_horiz_start) 00000000h page 501 40h r/w vip task b vbi even base/vbi end (vip_task_b_vbi_even_base_vbi_end) 00000000h page 501
amd geode? lx processors data book 483 video input port register descriptions 33234h 44h r/w vip task b vbi odd base/vbi start (vip_task_b_vbi_odd_base_vbi_start) 00000000h page 502 48h r/w vip task b data pitch/vertical start even (vip_task_b_data_pitch_vert_start_even) 00000000h page 502 4ch -- reserved -- -- 50h r/w vip task b v offset (vip_task_b_v_offset) 00000000h page 503 54h r/w vip task b u offset (vip_task_b_u_offset) 00000000h page 504 58h r/w vip ancillary data/message passing/data streaming buffer1 base address (vip_anc_msg_1_base) 00000000h page 504 5ch r/w vip ancillary data/message passing/data streaming buffer 2 base addre ss (vip_anc_msg_2_base) 00000000h page 505 60h r/w vip ancillary data/message passing/data streaming buffer size (vip_anc_msg_size) 00000000h page 505 64h -- reserved -- -- 68h r/w vip page offset/ page count (vip_page_offset) 00000000h page 506 6ch r/w vip vertical start/stop (vip_vert_start_stop) 00000000h page 506 70h r/w vip fifo address (vip _fifo_r_w_addr) 00000000h page 507 74h r/w vip fifo data (vip_fifo_data) xxxxxxxxh page 507 78h r/w vip vsync error count (vip_sync_err_count) 00000000h page 508 7ch r/w vip task a u even offset (vip_task_a_u_even_offset) 00000000h page 508 80h r/w vip task a v even offset (vip_task_a_v_even_offset) 00000000h page 509 table 6-76. vip configuration/control registers summary vip memory offset type register name reset value reference
484 amd geode? lx processors data book video input port register descriptions 33234h 6.10.1 standard geodelink? device (gld) msrs 6.10.1.1 gld capabilities msr (gld_msr_cap) 6.10.1.2 gld configuratio n msr (gld_msr_config) msr address 54002000h ty p e r o reset value 00000000_ 0003c4xxh gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nsmi nclk dev_id rev_id gld_msr_cap bit descriptions bit name description 63:32 rsvd reserved. 31:27 nsmi number of smi registers. the vip generates 15 possible smi interrupts. 26:24 nclk number of clock domains. the vip contains two clock domains; gliu clock and vip video clock. 23:8 dev_id device id. identifies device (03c4h). 7:0 rev_id revision id. identifies device revision. see amd geode? lx processors specification update document for value. msr address 54002001h ty p e r / w reset value 000000000_ 00000000h gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pri1 rsvd pri0 rsvd pid gld_msr_config bit descriptions bit name description 63:11 rsvd reserved. 10:8 pri1 secondary priority level. this value is the priority level the vip uses when performing high priority gliu accesses. this is the case when the fifo is nearly full. 7 rsvd reserved. 6:4 pri0 primary priority level. this value is the priority level the vip uses for most accesses (i.e., when the vip fifo is not in danger of being full). 3 rsvd reserved. 2:0 pid priority id. this value is the priority id (pid) value used when the vip initiates gliu transactions.
amd geode? lx processors data book 485 video input port register descriptions 33234h 6.10.1.3 gld smi msr (gld_msr_smi) msr address 54002002h ty p e r / w reset value 000000000_ xxxx7fffh gld_msr_smi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd smi_status rsvd smi_mask gld_msr_smi bit descriptions bit name description 63:31 rsvd reserved. 30:16 smi_status vip smi interrupt status. 0: smi not pending. 1: smi pending. writing a 1 to this bit clears the status: bit 30: reserved. bit 29: fifo overflow error. bit 28: fifo threshold hit. bit 27: long line (> 3000 clocks) error. bit 26: vertical timing error. bit 25: active pixels per line error. bit 24: vip clock input error. bit 23: ancillary packet checksum error. bit 22: message buffer full or ancillary threshold packet count reached. bit 21: end of vertical blanking. bit 20: start of vertical blanking. bit 19: start of even field. bit 18: start of odd field. bit 17: current line = vip line target (see current/target line register). bit 16: gliu address or type error. 15 rsvd reserved. 14:0 smi_mask vip smi masks. 0: enable, unmask the smi. 1: disabled, mask the smi. bit 14: reserved. bit 13: fifo overflow error. bit 12: fifo threshold hit. bit 11: long line (> 3000 clocks) error. bit 10: vertical timing error. bit 9: active pixels per line error. bit 8: vip clock input error. bit 7: ancillary pa cket checksum error. bit 6: message buffer full or ancillary threshold packet count reached. bit 5: end of vertical blanking. bit 4: start of vertical blanking. bit 3: start of even field. bit 2: start of odd field. bit 1: current line = vip line target (see current/target line register). bit 0: gliu address or type error.
486 amd geode? lx processors data book video input port register descriptions 33234h 6.10.1.4 gld error msr (gld_msr_error) msr address 54002003h ty p e r / w reset value 000000000_ 00000000h gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd e1 e0 rsvd em1 em0 gld_msr_error bit descriptions bit name description 63:18 rsvd reserved. 17 e1 error status 1. writing a 1 to this bit clears the status. 0: vip error not pending. 1: vip error pending. types of errors reported: bit 17: unexpected address. 16 e0 error status 0. writing a 1 to this bit clears the status. 0: vip error not pending. 1: vip error pending. types of errors reported: bit 16: unexpected type. 15:2 rsvd reserved. 1em1 error mask 1. 0: unmask the error (enabled). 1: mask the error (disabled). 0em0 error mask 0. 0: unmask the error (enabled). 1: mask the error (disabled).
amd geode? lx processors data book 487 video input port register descriptions 33234h 6.10.1.5 gld power management register (gld_msr_pm) 6.10.1.6 gld diagnostic msr (gld_msr_diag) this register is reserved for internal use by amd and should not be written to. msr address 54002004h ty p e r / w reset value 000000000_ 00000005h gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd 0 p1 0 p0 gld_msr_pm bit descriptions bit name description 63:4 rsvd reserved. 3 rsvd reserved. always set to 0. 2p1 vip clock power mode. 0: disable clock gating. vip clock is always on. 1: enable active hardware clock gating. the vip input clock to the video input block is enabled when this bit is 0. when this bit is 1, the vip input clock is enabled whenever the vip reset bit (vip memory offset 00h[0]) is 0 or if vip_mode (vip memory offset 00h bit [3:1]) is in a non 000 state. this bit defaults to 1. 1 rsvd reserved. always set to 0. 0p0 gliu clock power mode. 0: disable clock gating. gliu clock is always on. 1: enable active hardware clock gating. gliu clock is always on if the vip reset bit (v ip memory offset 00h[0]) is 0. when the vip reset bit is 1 and this bit is 1, the internal vip gliu clocks are only turned on in response to requests (memory mapped read/writes and msr read/writes) from the gliu. this bit defaults to 1. msr address 54002005h ty p e r / w reset value 000000000_ 00000000h
488 amd geode? lx processors data book video input port register descriptions 33234h 6.10.2 vip control/configuration registers 6.10.2.1 vip control regi ster 1 (vip_ctl_reg1) vip memory offset 00h ty p e r / w reset value 42000001h vip_ctl_reg1 register map 3130292827262524232221201918171615141312111098 7 6 543210 anc_ff vid_ff err_detect ni mb dz dd dt_en run_mode p vip_mode vrst vip_ctl_reg1 bit descriptions bit name description 31:29 anc_ff ancillary fifo flush. watermark level for flushing the 64-deep ancillary fifo. this value determines how full the ancillary fifo is before vip starts writing qwords to sys- tem memory. if the fifo has greater than 4 qwords and the address is aligned, vip generates a burst (4 qwords) transaction.t his value is reset to 2 (flush when 17 qwords). 0: flush when there is at least 1 qword. 1: flush when there are at least 9 qwords. 2: flush when there are at least 17 qwords. (default) n: flush when there are at least nx8 +1 qwords (up to n = 7x8 +1 = 57). (anc fifo size is 64 qwords). 28:24 vid_ff video fifo flush. watermark level for flushing the 64-deep (planar mode) or 192-deep (linear mode) fifo(s). this value determines how full the ancillary fifo is before vip starts writing qwords to system memory. if the fifo has great er than 4 qwords and the address is aligned, vip generates a burs t (4 qwords) transaction. this value is reset to 2 (flush when 17 qwords). 0: flush when there is at least 1 qword. 1: flush when there are at least 9 qwords. 2: flush when there are at least 17 qwords. (default) n: flush when there are at least nx8+1 qwords). (fifo size is 192 qwords in linear mode, maximum value is 17h/23d). (fifo size is 64 qwords in planar mode, maximum value is 7). 23:20 err_detect video detection enable. selects what detection circuitry is used to detect loss of valid video input. when an error is detected, the video_ok output is set low. the associated interrupt pending bit must be cleared to allow the video_ok signal to return high. bit 23: runaway line error abort (aborts line if a line is detec ted longer then 3000 clocks). bit 22: vertical timing error (vertical count register must be programmed) or address- ing error (max_addr reg must be programmed). bit 21: number of clocks per active line error (checks that each line has the same # of data). bit 20: loss of vip clock (watchdog time r using gliu clocks --128 gliu clocks).
amd geode? lx processors data book 489 video input port register descriptions 33234h 19 ni non-interlaced video input. this bit determines if the start/end-of-frame event occurs each field (for non-interlaced video) or at the end of the odd field (for interlaced video). the start/end-of-frame indication is used as the start/end-of-frame indication for the run mode capture. when in 601 input modes, the ni bit determines if separate vertical back- porch values are used. for interlaced modes, different vertical start/end values can be programmed. 0: interlaced video (use field and vblank flags for start/end-of-frame indication). 1: non-interlaced video (use only vblank flag for start/end-of-frame indication). 18 mb message/streaming control. 0: switch buffers each packet input or at end of buffer. 1: switch buffers only when buffer is full. store multiple packets in buffer. 17 dz disable zero detect. disables ignoring zero data within sav/eav packets. when set, zero data is received and saved in system memory. 0: normal operation - zero data in sav/eav packets is ignored and not saved to system memory. 1: accept 0 data and save in system memory. 16 dd disable decimation. disables decimation of even lines of cr,cb data for 4:2:2->4:2:0 translation. 0: normal operation - even lines of cr,cb data do not get saved in cr,cb buffers when in planar mode. 1: all cr,cb data is stored in cr,cb main memory buffers. 15:8 dt_en data type capture enable. (only used when vip_mode (bits [3:1]) = 001, 010, 011) 0: disable capture data. 1: enable capture data. bit 8: task a video. bit 9: task a vbi. bit 10: task b video. bit 11: task b vbi. bit 12: ancillary, rising edge resets the ancillary packet count, the next packet will be stored starting at the base address. bit 13: reserved (always program to 0). bit 14-15: reserved (always program to 0). 7:5 run_mode run mode capture. selects capture run mode. 000: stop capture. 001: stop capture at end of the current line. 010: stop capture at end of next field. 011: stop capture at end of the next frame. 100: start capture at beginning of next line. 101: start capture at beginning of the next field. 110: start capture at beginning of next frame. 111: start capture (required for msg/data streaming modes). 4p planar. determines if video data is stored in a linear format or planar format in system memory. 0: store data in linear format. 1: store video data in planar format. vip_ctl_reg1 bit descriptions (continued) bit name description
490 amd geode? lx processors data book video input port register descriptions 33234h 6.10.2.2 vip control regi ster 2 (vip_ctl_reg2) 3:1 vip_mode vip operating mode. 000: idle. this mode forces vid[ 15:0] to 0 from pads to vip. 001: vip 2.0 8-bit mode. 010: vip 2.0 16-bit. 011: vip 1.1 8-bit. 100: message passing. 101: data streaming. 110: 601 type 8-bit mode. 111: 601 type 16-bit mode. 0vrst vip reset. when set to 1, this bit causes the vip input logic to be reset. the control reg- isters and base registers are not reset. data is received/stored once this bit is set back to 0 according to control register 1 and 2. a 1 should also be written to the fifo reset (control register 3 (vip memory offset 2ch[ 0])) between writing a 1 and 0 to this regis- ter. the power-up value of vrst is 1. vip memory offset 04h ty p e r / w reset value 00000000h vip_ctl_reg1 bit descriptions (continued) bit name description vip_ctl_reg2 register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fi a_err_en r_en swc anc10 ancpen lpb ff_r/w pag e _ c n t anc_ff_thresh rsvd vid_ff_thresh sync_to_pin field_to_dc sync_to_dc vip_ctl_reg2 bit descriptions bit name description 31 fi field invert. when set to 1, the polarity of the input field bit is inverted. this allows for devices that violate t he vip 2.0 specification. 30 a_err_en address error enable. when set to 1, the gliu address that vip is writing to is com- pared to the max address register (vip memo ry offset 14h). if a comparison is made, the vip run mode control is forced to 0 causing vip to stop capturing data. the frame error interrupt is generated. 29 r_en repeat flag enable. when set to 1, the repeat flag in the sav or eav header is used to determine if the packet is saved. this allows the vip to drop repeat fields during 3:2 pull down. 28 swc sub-window capture enable. when set to 1, only a portion of the frame/field is cap- tured. capture starts on the line specified in the vertical start/stop register (vip memory offset 6ch) and ends after the line specif ied in the vertical start/stop register. 27 anc10 10-bit ancillary data input. when set to 1, ancillary data is received as 10-bit data. (this is only applicable in 16-bit vip mode).
amd geode? lx processors data book 491 video input port register descriptions 33234h 26 ancpen ancillary parity check enable. when set to 1, ancillary did, sdid, nn, and check sum bytes are checked for even parity. the error is reported on msr 4002002h[23]. when this bit is 0, the ancillary checksum or parity error bit only indicates ancillary checksum errors. 25 lpb vop to vip loopback. when set to 1, the vop clock and data are used as the clock and data inputs to the vip. this allows for loopback testing of the vop and vip functions. this bit must be set to 0 for normal vip operation. 24 ff_r/w fifo r/w enable. when set to 1, the fifo address (vip memory offset 70h) and fifo data (vip memory offset 74h) registers can be used to write and read the 256x32 bit fifo. this bit must be set to 0 for normal vip operation. 23:21 page_cnt page count. determines how many pages of video data are used. when this value is 000, a single page of video data is stored (d efault). additional pages are saved by add- ing the value in the page offset register (vip memory offset 68h) to each base. 000: 1 page. (default) 001: 2 pages. ? 111: 8 pages. 20:16 anc_ff_ thresh ancillary fifo threshold. watermark level for setting the ancillary fifo threshold. this value also determines when the secondary priority is used during a write request. if the fifo word count exceeds this value, the sec ondary priority id is used. an int or smi can also be generated if this threshold is exceeded. threshold value. 0-31. the ancillary fifo depth is always 64 qwords. 15 rsvd reserved. 14:8 vid_ff_ thresh video fifo threshold. watermark level for setting the video fifo threshold. this value also determines when the secondary priority is used during a write request. if the fifo word count exceeds this value, the secondary priority id is used. an int or smi can also be generated if this threshold is exceeded. threshold value. 0-127 linear mode: y buffer depth is 192 qwords. planar mode: y,u,v buffer depths are all 64 qwords 7:5 sync_to_pin sync select. selects signal timing for vip_vsync pin. 000: 0 (output disabled). 001: select vsync_in from dc. 010: select vsync_in from dc (inverted). 011: select bit 17 of status regi ster (vip memory offset 08h). 100-111: 0. 4:3 field_to_dc field to dc select. selects signal for field_to_vg. 00: field input. 01: inverted field input. 10: lsb of page being written (indicat es which page is currently active). 11: inverted lsb of page being written. 2:0 sync_to_dc vsync select. selects signal timing for vip_vsync output to the dc. 000: sync from pin. 001: inverted sync from pin. 010: vblank. 011: inverted vblank. 100: field. 101: inverted field. 110: when vip_current_line = target_line. 111: 0. vip_ctl_reg2 bit descriptions (continued) bit name description
492 amd geode? lx processors data book video input port register descriptions 33234h 6.10.2.3 vip status (vip_status) vip memory offset 08h ty p e r / w reset value xxxxxxxxh vip_status register map 313029282726252423222120191817161514131211109876543210 apc rsvd fpe rsvd dpc so brnu rsvd msg_berr b2_full b1_full rsvd glwc fe rsvd f v run_status vip_status bit descriptions bit name description 31:24 apc (ro) ancillary packet count (read only). number of ancillary packets available in the ancil- lary buffer in system memory. this count is incremented each time an ancillary packet is received. it gets decremented when a 1 is written to the dpc bit (bit 18). 23 rsvd reserved. 22:20 fpe (ro) fifo pointer error (read only) . these bits indicate if the fifo pointers are misaligned at the point when the base registers are updated. a 1 indicates that the pointers may be misaligned, which could result in an horizontal image shift. these bits are valid only when vbi data reception is disabled. int15 is generated when any of these bits go active. [22] - b fifo. [21] - r fifo. [20] - y fifo. 19 rsvd reserved. 18 dpc (wo) decrement ancillary pac ket count (write only). writing a 1 to this bit causes the ancillary packet count to be decremented by 1. 17 so (wo) sync out (write only) . writing a 1 to this bit causes a 0-1-0 transition on the vip_vsync pin (32 gliu clocks). 16 brnu (ro) base register not updated (read only). 0: all base registers are updated. 1: one or more of the base registers have been written but have not yet been updated. note: the following base registers are updated at a start-of-frame event. task_a_vid_even_base, task_a_vid_ odd_base, task_a_vbi_even_base, task_a_vid_odd_base, task_a_vid_e ven_base, task_a_vid_odd_base, task_a_vbi_even_base, task_a_vid_odd_base the start-of-frame event occurs when entering a vertical blanking interval during the odd field (for interlaced video) or when entering any vertical blanking interval (non-interlaced video). since the base pointers are initialized to 0 at reset, a start-of-frame event must occur before enabling vip to receive data. other wise, vip will save the first video frame to address 0 in system memory. one way of insu ring this is to initialize vip to receive video data with the run_mode bits (vip memory offset 00h bits [7:5]) set to 0. this enables the vip input interface, but it will not capture video. poll this bit until the internal base register updates have occurred. the run_mode control can then be programmed to start capturing data on the next line/field/frame boundary. 15 rsvd reserved.
amd geode? lx processors data book 493 video input port register descriptions 33234h 14 msg_berr message buffer error. 0: no error. 1: message buffer was overwritten. this occurs when both msg buffers are full and a msg/dstrm packet is received. writing a 1 to the bit resets it to 0. 13 b2_full msg buffer 2 full. 0: buffer 2 empty. 1: buffer 2 full. writing a 1 to the bit resets it to 0. 12 b1_full msg buffer 1 full. 0: buffer 1 empty. 1: buffer 1 full. writing a 1 to the bit resets it to 0. 11:10 rsvd reserved. 9glwc gliu writes completed. 0: vip has outstanding gliu transactions. 1: vip has completed all outstanding gliu transactions. 8fe vip fifo empty. 0: vip fifo is not empty. 1: vip fifo is empty. 7:5 rsvd reserved. 4 f (ro) field indication (read only). indicates current status of field being received. 0: odd field is being received. 1: even field is being received. 3v (ro) vblank indication (read only) . indicates current status of vblank being received. 0: active video. 1: vertical blanking. 2:0 run status (ro) run status (read only). indicates active data types received. bit 2: indicates that an ancillary packet has been received. bit 1: indicates that a vbi packet has been received. bit 0: indicates that a video packet or msg/data streaming packet has been received. writing a 1 to a bit resets it to 0. thes e bits are enabled when the corresponding dt_en bits are set in the vip control 1 register (vip memory offset 00h) along with the vip_mode bits. vip_status bit descriptions (continued) bit name description
494 amd geode? lx processors data book video input port register descriptions 33234h 6.10.2.4 vip interrupt (vip_int) vip memory offset 0ch ty p e r / w reset value xxxxfffeh vip_int register map 313029282726252423222120191817161514131211109876543210 int_status int_mask vip_int bit descriptions bit name description 31:16 int_status vip interrupt status. 0: int not pending. 1: int pending. writing a 1 to this bit clears the status. bit 30: fifo line wrap error. bit 29: fifo overflow error. bit 28: fifo threshold hit. bit 27: long line (> 3000 clocks) error. bit 26: vertical timing error (frame error or address error)/msg missed error. bit 25: active pixels per line error. bit 24: vip clock input error. bit 23: ancillary checks um or parity error. bit 22: msg buffer full or ancillary threshold packet count reached. bit 21: end of vertical blanking. bit 20: start of vertical blanking. bit 19: start of even field. bit 18: start of odd field. bit 17: current line = vip line target (see current/target line register). bit 16: not used (0). 15:0 int_mask vip interrupt masks. 0: enable, unmask the int. 1: disabled, mask the int. bit 14: when enabled (0), allows fifo line wrap error int. bit 13: when enabled (0), allows fifo overflow error int. bit 12: when enabled (0), allows fifo threshold hit int. bit 11: when enabled (0), allows long line (> 3000 clocks) error int. bit 10: when enabled (0), allows vertical ti ming error (frame error or address error) int. bit 9: when enabled (0), allows the active pixel input video error int. bit 8: when enabled (0),allows the vip clock input error int. bit 7: when enabled (0), allows ancillary checksum or parity error int. bit 6: when enabled (0), allows msg buffer full int or ancillary threshold packet count reached int. bit 5: when enabled (0), allows end of vertical blanking int. bit 4: when enabled (0), allows start of vertical blanking int. bit 3: when enabled (0), allows start of even field int. bit 2: when enabled (0), allows start of odd field int. bit 1: when enabled (0), allows current li ne = vip line target in t (see current/target line register). bit 0: not used (r/w).
amd geode? lx processors data book 495 video input port register descriptions 33234h 6.10.2.5 vip current/target (vip_cur_tar) 6.10.2.6 vip max address (vip_max_addr) vip memory offset 10h ty p e r / w reset value 00000000h vip_cur_tar register map 313029282726252423222120191817161514131211109876543210 line_target current_line vip_cur_tar register bit descriptions bit name description 31:16 line_target line target. indicates the video line to generate an interrupt on. 15:0 current_ line (ro) current line (read only). indicates the video line currently being captured. line count- ing begins on the first active line. the count indicated in this field is reset to 0 at the start of each field (interlaced) or frame (non-interlated). vip memory offset 14h ty p e r / w reset value ffffffffh vip_max_addr register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 max_addr rsvd vip_max_addr bit descriptions bit name description 31:3 max_addr max address. this value is compared with the gliu address. if the gliu address is equal or greater then this value, a vip add ressing error is detected. this resets the run_mode bits (vip memory offset 00h[7:5]) to 000, stopping t he vip from capturing data. a frame error int is also generated. the a_err_en bit (vip memory offset 04h[30])must be set to enable this function. th e vip must be reset by writing a 1 to the vrst bit (vip memory offset 00h[0]) to clear t he addressing error. bits [2:0] of this regis- ter are not used in the comparison. note that the vip will only stop capturing data on this address, it will continue writing data from the fifo into memory. up to 192 qwords (1536 bytes) can be written past this addr ess (max # data in fifo, although it is more likely that ~10-20 qwords are written. 2:0 rsvd reserved. set to 0.
496 amd geode? lx processors data book video input port register descriptions 33234h 6.10.2.7 vip task a video even base address (vip_task_a_vid_even_base) 6.10.2.8 vip task a video odd base address (vip_task_a_vid_odd_base) vip memory offset 18h ty p e r / w reset value 00000000h vip_task_a_vid_even_base register map 313029282726252423222120191817161514131211109876543210 task_a_video_even_base_address program to 00000 vip_task_a_vid_even_base bit descriptions bit name description 31:0 task_a video_even base task a video even base address. this register specifies the base address in graphics memory where task a even video field data will be stored. changes to this register take effect at the beginning of the next field. this value needs to be 32-byte aligned. (bits [4:0] are required to be 00000.) note: this register is double buffered. when a new value is written to this register, the new value is placed in a special pending register, and the base register not updated bit (vip memory offset 08h[16]) is set to 1. the task a video data even base address register is not updat ed at this point. when the first data of the next field is captured, the pending values of all ba se registers are written to the appropriate base registers, and the base register not updated bit is cleared. vip memory offset 1ch ty p e r / w reset value 00000000h vip_task_a_vid_odd_base register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 task_a_video_odd_base program to 00000 vip_task_a_vid_odd_base bit descriptions bit name description 31:0 task_a_vide o_odd_base task a video odd base address. this register specifies the base address in graphics memory where task a odd video field data will be stored. changes to this register take effect at the beginning of the next field. this value needs to be 32-byte aligned. (bits [4:0] are required to be 00000.) note: this register is double buffered. when a new value is written to this register, the new value is placed in a special pending register, and the base register not updated bit (vip memory offset 08h[16]) is set to 1. the task a video data odd base address register is not updated at this point. when the first data of the next field is captured, the pending values of all base registers are written to the appropriate base registers, and the base register not updated bit is cleared.
amd geode? lx processors data book 497 video input port register descriptions 33234h 6.10.2.9 vip task a vbi even base address (vip_task_a_vbi_even_base) 6.10.2.10 vip task a vbi odd base address (vip_task_a_vbi_odd_base) vip memory offset 20h ty p e r / w reset value 00000000h vip_task_a_vbi_even_base register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 task_a_vbi_data_even_base program to 00000 vip_task_a_vbi_even_base bit descriptions bit name description 31:0 task_a_vbi_e ven_base task avbi even base address. this register specifies the base address in graphics memory where vbi data for even fields is stored. changes to this register take effect at the beginning of the next field. the value in this register is 16-byte aligned. this value needs to be 32-byte aligned. (bits [4:0] are required to be 00000.) note: this register is double buffered. when a new value is written to this register, the new value is placed in a special pending register, and the base register not updated bit (vip memory offset 08h[16]) is set to 1. the task a vbi even base address register is not updated at this point. when the first data of the next field is captured, the pending values of all bas e registers are written to the appropriate base registers, and the base regi ster not updated bit is cleared. vip memory offset 24h ty p e r / w reset value 00000000h vip_task_a_vbi_odd_base register map 313029282726252423222120191817161514131211109876543210 task_a_vbi_data_odd_base program to 00000 vip_task_a_vbi_odd_base bit description bit name description 31:0 task_a_vbi_o dd_base task a vbi odd base address. this register specifies the base address in graphics memory where task a vbi data for odd fields are stored. changes to this register take effect at the beginning of the next field. the value in this register is 8-byte aligned. this value needs to be 32-byte aligned. (bits [4:0] are required to be 00000.) note: this register is double buffered. when a new value is written to this register, the new value is placed in a special pending register, and the task a base register not updated bit (vip memory offset 08h [16]) is set to 1. the task a vbi odd base address register is not updated at th is point. when the first data of the next field is captured, the pending values of al l base registers are written to the appro- priate base registers, and the base register not updated bit is cleared.
498 amd geode? lx processors data book video input port register descriptions 33234h 6.10.2.11 vip task a video pi tch (vip_task_a_vid_pitch) 6.10.2.12 vip contro l register 3 (vip_contrl_reg3) vip memory offset 28h ty p e r / w reset value 00000000h vip_task_a_vid_pitch register map 313029282726252423222120191817161514131211109876543210 task_a_uv_pitch program to 00000 task_a_video_pitch program to 00000 vip_task_a_vid_pitch bit descriptions bit name description 31:16 task_a_uv_ pitch task a uv pitch. specifies the logical width of the video data buffer when in linear mode. specifies the logical width of the u and v buffers when in planar mode. this value is added to the start of the line address to ge t the address of the ne xt line where captured video data will be stored. this value must be an integral number of qwords. this value needs to be 32-byte aligned. (bit s [20:16] are requ ired to be 00000.) 15:0 task_a_ video_pitch task a video pitch. specifies the logical width of the video data buffer when in linear mode. specifies the logical width of the y buffer when in planar mode. this value is added to the start of the line address to get th e address of the next line where captured video data will be stored. this value must be an integral number of qwords. this value needs to be 32-byte aligned. (bits [4:0] are required to be 00000.) vip memory offset 2ch ty p e r / w reset value 00000020h vip_contrl_reg3 register map 313029282726252423222120191817161514131211109876543210 rsvd pdm bru dor efd tp vp hp rsvd fr vip_contrl_reg3 bit descriptions bit name description 31:11 rsvd reserved. 10 pdm planar de-interlace mode. when set to 1, the u/v even buffers are referenced to the task a video odd base address (vip memory offset 18h) rather then the task a video even base address (vip memory offset 1ch). this bit should always be set to 0. (possi- bly used in some de-interlacing schemes, but not likely.) 9bru base register update. when set to 1, base registers are updated at the beginning of each field when in interlaced mode. when 0, the base registers are updated at the begin- ning of each frame when in interlaced mode . this bit has no effect in non-interlaced mode where start of field is the same as start of frame. 8dor disable overflow recovery. when set to 1, the overflow recovery logic is disabled. an overflow interrupt is generated. it is then up to the software to do a fifo reset to recover from the overflow condition
amd geode? lx processors data book 499 video input port register descriptions 33234h 6.10.2.13 vip task a v offset (vip_task_a_v_offset) 7efd even field uv decimation. when set to 1, the u and v values of the even frame will be discarded. note: the dd bit (vip memory offset 00h[16]) should be set to 1 or even lines will also be decimated. 6tp task polarity. when set to 1, the input task bit is inverted. 5vp vsync polarity. this bit is set to 1 when the vsync input is active high (high during vblank) or 0 when the vsync input is active low (low during vblank). this is only used for 601 type input video where hsy nc and vsync signals are used rather then the sav/eav codes. 4hp hsync polarity. this bit is set to 1 when the hsync input is active high (high during hblank) or 0 when the hsync input is active low (low during hblank). this is only used for 601 type input video where hsy nc and vsync signals are used rather then the sav/eav codes. 3:1 rsvd reserved. 0fr fifo reset. setting this bit forces the vip fifo pointers and data co unts to their reset state. this might be used in cases where high gliu latencies cause continuous fifo overflows, when a line overrun error occurs, or if the line offset gets corrupted which could result in an image shift. this bit re mains a 1 during the fifo reset sequence. when the fifo reset sequence has completed, this bit is automatically reset to a 0. the fifo reset sequence consists of: input reception is halted. the input and output fifo addres ses and data counts are reset. wait for all outstanding gliu requests to be completed. the fifo reset bit is set to 0. input data reception starts af ter the programmed run control event has occurred (i.e., start of line, field, frame). vip memory offset 30h ty p e r / w reset value 00000000h vip_contrl_reg3 bit desc riptions (continued) bit name description vip_task_a_v_offset register map 313029282726252423222120191817161514131211109876543210 task_a_v_odd_offset program to 00000 vip_task_a_v_offset bit descriptions bit name description 31:0 task_a_v_ odd_offset task a v odd offset. this register determines the st arting address of the v buffer when data is stored in planar format. the start of the v buffer is determined by adding the con- tents of this register to that of the base add ress. this value must be 32-byte aligned. (bits [4:0] are required to be 00000.)
500 amd geode? lx processors data book video input port register descriptions 33234h 6.10.2.14 vip task a u offset (vip_task_a_u_offset) 6.10.2.15 vip task b video even base/horizon tal end (vip_task_b_vi d_even_base_horiz_end) vip memory offset 34h ty p e r / w reset value 00000000h vip_task_a_u_offset register map 313029282726252423222120191817161514131211109876543210 task a u odd offset program to 00000 vip_task_a_u_offset bit descriptions bit name description 31:0 task a u odd offset task a u odd offset. this register determines the st arting address of the u buffer when data is stored in planar format. for interlaced input, this register will determine the start- ing address of the u data for the odd field. the start of the u buffer is determined by add- ing the contents of this register to that of the base address. this value needs to be 32- byte aligned. (bits [4:0] are required to be 00000.) vip memory offset 38h ty p e r / w reset value 00000000h vip_task_b_vid_even_base_horiz_end register map 313029282726252423222120191817161514131211109876543210 task_b_vid_even_base_horiz_end (601 type modes) vip_task_b_vid_even_base_ho riz_end bit descriptions bit name description 31:0 task_b_vid_ even_base task b video even base address. this register specifies the base address in graphics memory where even video field data are stored. changes to this register take effect at the beginning of the next field. the value in this register is 16-byte aligned. bits [3:0] are always 0, and define the required address space. note: this register is double buffered. when a new value is written to this register, the new value is placed in a special pending register, and the base register not updated bit (vip memory offset 08h[16]) is set to 1. the task b video even base address register is not updated at th is point. when the first data of the next field is captured, the pending values of al l base registers are written to the appro- priate base registers, and the base register not updated bit is cleared. 15:0 horiz_end horizontal end. this register is redefined in bt.601 mode. in bt. 601 type input modes timing is derived from the external hsync and vsync inputs. this value specifies where video data ends for the line.
amd geode? lx processors data book 501 video input port register descriptions 33234h 6.10.2.16 vip task b video odd base/horizontal start (vip_task_b_vid_ odd_base_horiz_start) 6.10.2.17 vip task b vbi even base/vbi end (vip_task_b_vbi_even_base_vbi_end) vip memory offset 3ch ty p e r / w reset value 00000000h vip_task_b_vid_odd_base_horiz_start register map 313029282726252423222120191817161514131211109876543210 task_b_vid_odd_base_horiz_start (601 type modes) vip_task_b_vid_odd_base_ho riz_start bit descriptions bit name description 31:0 task_b_vid_ odd_base task b video odd base address. this register specifies the base address in graphics memory where odd video field data is stored. c hanges to this register take effect at the beginning of the next field. this value must be 32-byte aligned. (bit s[4:0] are required to be 00000.) note: this register is double buffered. when a new value is written to this register, the new value is placed in a special pending register, and the ?base register not updated? bit (vip memory offset 08h[16] ) is set to 1. the video data odd base address register is not updated at this point. when the first data of the next field is captured, the pending values of all bas e registers are written to the appropriate base registers, and the base regi ster not updated bit is cleared. 11:0 horiz_start horizontal start. this register is redefined in bt.601 mode. in bt.601 type input modes timing is derived from the external hsync and vsync inputs. this value specifies where video data starts for the line. see figure 6-47 "bt.601 mode horizontal timing" on page 472 for programing information. vip memory offset 40h ty p e r / w reset value 00000000h vip_task_b_vbi_even_base_vbi_end register map 313029282726252423222120191817161514131211109876543210 task_b_vbi_data_even_base_vbi_end (for 601 type modes) vip_task_b_vbi_even_base_vbi_end bit descriptions bit name description 31:0 task_b_vbi_ data_even_ base_vbi_ end task b vbi even base address. this register specifies the base address in graphics memory where vbi data for even fields is stored. changes to this register take effect at the beginning of the next field. this val ue must be 32-byte aligned. (bits [4:0] are required to be 00000.) note: this register is double buffered. when a new value is written to this register, the new value is placed in a special pending register, and the base register not updated bit (vip memory offset 08h[16]) is set to 1. the vbi odd base address register is not updated at this point. when the first data of the next field is cap- tured, the pending values of all base regi sters are written to the appropriate base registers, and the vbi base register not updated bit is cleared.
502 amd geode? lx processors data book video input port register descriptions 33234h 6.10.2.18 vip task b vbi odd base/vbi st art (vip_task_b_vbi_odd_base_vbi_start) 6.10.2.19 vip task b data pitch/vertical start even (vip_task_b_data_pitch_vert_start_even) 11:0 vbi_end vbi end. this register is redefined in bt.601 mode. in bt.601 type input modes, timing is derived from the external hsync and vsync inputs. this value specifies what line the vbi data ends in each field/frame. the end of vbi data is reached when the number of lines from the falling edge of vsync equals this value. see figure 6-48 "bt.601 mode vertical timing" on page 473 for additional detail. vip memory offset 44h ty p e r / w reset value 00000000h vip_task_b_vbi_even_base_vbi_en d bit descripti ons (continued) bit name description vip_task_b_vbi_odd_base_vbi_start register map 313029282726252423222120191817161514131211109876543210 task_b_vbi_data_odd_base_vbi_start (for 601 type modes) vip_task_b_vbi_odd_base_vbi_start bit descriptions bit name description 31:0 task_b_vbi_ data_odd_ base task b vbi odd base address. this register specifies the base address in graphics memory where vbi data for odd fields is stored . changes to this register take effect at the beginning of the next field. this val ue must be 32-byte aligned. (bits [4:0] are required to be 00000.) note: this register is double buffered. when a new value is written to this register, the new value is placed in a special pending register, and the base register not updated bit (vip memory offset 08h[16]) is set to 1. the vbi odd base address register is not updated at this point. when the first data of the next field is cap- tured, the pending values of all base regi sters are written to the appropriate base registers, and the vbi base register not updated bit is cleared. 11:0 vbi_start vbi start. this register is redefined in bt.601 mode. in bt.601 type input modes, timing is derived from the external hsync and vsync inputs. this value specifies what line the vbi data starts in each fi eld/frame. the start of vbi dat a begins when the number of lines from the leading edge of vsync equals this value. see figure 6-48 "bt.601 mode vertical timing" on page 473 for additional detail. vip memory offset 48h ty p e r / w reset value 00000000h vip_task_b_data_pitch_vert_ start_even register map 313029282726252423222120191817161514131211109876543210 rsvd vertical_end_even task_b_data_pitch_vert_start_even vip_task_b_data_pitch_vert_start_even bit descriptions bit name description 31:28 rsvd reserved.
amd geode? lx processors data book 503 video input port register descriptions 33234h 6.10.2.20 vip task b v offset (vip_task_b_v_offset) 27:16 vertical_ end_even (even/second field) vertical end even. this register is redefined in bt.601 mode. in bt.601 type input modes timing is derived from the external hsync and vsync inputs. this value speci- fies the last line of the even field captured in interlaced modes. this value is ignored when the ni bit (vip memory offset 00h[19] ) is set (indicating non-interlaced input). the vert_end (vip memory offset 6ch[27:16]) value is used for non-interlaced modes. see figure 6-48 "bt.601 mode vertical timing" on page 473 for additional detail. 15:0 task_b_data _pitch task b data pitch/. specifies the logical width of the video data buffer. this value is added to the start of the line address to get th e address of the next line where captured video data will be stored. the value in this re gister needs to be 32-byte aligned in linear mode, and 64-byte aligned in planar mode. (in linear mode, bits [4:0] are required to be 00000. in planar mode, bits [5:0] are required to be 000000.) 11:0 vert_start_ even (even/second field) vertical start even. this register is redefined in bt.601 mode. in bt.601 type input modes, timing is derived from the external hsync and vsync inputs. this value speci- fies the line that the even field video data beg ins. even field video data is captured until vertical end even this value is ignored when the ni bit (vip memory offset 00h[19]) is set (indicating non-interlaced input). the vert_start (vip memory offset 6ch) value is used for non-interlaced modes. see figur e 6-48 "bt.601 mode vertical timing" on page 473 for additional detail. vip memory offset 50h ty p e r / w reset value 00000000h vip_task_b_data_pitch_vert_start_even bit descriptions (continued) bit name description vip_task_b_v_offset register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 task_b_v_offset_start_odd vip_tas_b_v_offset bit descriptions bit name description 31:0 task_b_v_ offset task b v offset. this register determines the starti ng address of the v buffer when data is stored in planar format. the start of the v buffer is determined by adding the contents of this register to that of th e base address. the value in this register needs to be 32-byte aligned. (bits [4:0] are required to be 00000.) note: this register in not double buffered and should be initialized before start of video capture. 11:0 23:16 start_odd start odd field detect/duration. this register is redefined in bt.601 mode. when in bt.601 interlaced mode, this register determi nes the window for field detection. the start bits [11:0] are the number of clocks from the leading edge of hsync to when the detec- tion window begins, the duration bits [23:16] are the # of clocks that the detection window is active. if the leading edge of vsync occurs within the window, the field is set to odd, otherwise it is set to even. at the default state of 0, the leading edge of vblank must transition simultaneously with the leading edge of hsync for odd field detection. when the ni bit in (vip memory offset 00h[19]) is set (non-interlaced mode), all frames are considered to be odd fields.
504 amd geode? lx processors data book video input port register descriptions 33234h 6.10.2.21 vip task b u offset (vip_task_b_u_offset ) 6.10.2.22 vip ancillar y data/message passing/data streaming buffer1 base address (vip_anc_msg_1_base) vip memory offset 54h ty p e r / w reset value 00000000h vip_task_b_u_offset register map 313029282726252423222120191817161514131211109876543210 task_b_u_offset program to 00000 vip_task_b_u_offset bit descriptions bit name description 31:0 task_b_u_ offset task b u offset. this register determines the starti ng address of the u buffer when data is stored in planar format. the start of the u buffer is determined by adding the contents of this register to that of the base address. the value in this register must be 32-byte aligned. (bits [4:0] are required to be 00000.) note: this register in not double buffered and should be initialized before start of video capture. vip memory offset 58h ty p e r / w reset value 00000000h vip_anc_msg_1_base register map 313029282726252423222120191817161514131211109876543210 anc_msg_1_base program to 00000 vip_anc_msg_1_base bit descriptions bit name description 31:0 anc_msg_1_ base ancillary data/message passing data/data streaming base address. this register specifies the base address for the ancillary data when in vip modes or message/stream- ing data when in message passing or data streaming modes. changes to this register take effect at the beginning of the next field when in vip mode. it takes place immediately when in message passing or data streaming mode. the value in this register must be 32-byte aligned. (bits [4:0] are required to be 00000.) note: this register is not double buffered.
amd geode? lx processors data book 505 video input port register descriptions 33234h 6.10.2.23 vip ancill ary data/message passing/data streaming buffer 2 base address (vip_anc_msg_2_base) 6.10.2.24 vip ancill ary data/message passing/data streaming buffer size (vip_anc_msg_size) vip memory offset 5ch ty p e r / w reset value 00000000h vip_anc_msg_2_base register map 313029282726252423222120191817161514131211109876543210 anc_msg_2_base program to 00000 vip_anc_msg_2_base bit descriptions bit name description 31:0 anc_msg_2_ base message passing data/data streaming base address. this register specifies the base address for the second buffer used in message passing and data streaming modes. data written to this register take s place immediately (no double buffer). the value in this register must be 32-byte ali gned. (bits [4:0] are required to be 00000.) note: this register is not double buffered. vip memory offset 60h ty p e r / w reset value 00000000h vip_anc_msg_size register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 anc_pack_int_thresh rsvd anc_msg_stream_size vip_anc_msg_size bit descriptions bit name description 31:24 anc_pack_ int_thresh ancillary packet interrupt threshold value. this value determines when the ancillary interrupt occurs. the ancillary packet count (apc) bits (vip memory offset 08h[31:24]) is compared to this value. if the apc is equal to or greater then this value, the ancillary interrupt is generated. 23:19 rsvd reserved. 18:0 anc_msg_ stream_size ancillary data/message passing data/data streaming buffer size. this register specifies the size of the ancillary, message pa ssing, and data streaming buffers in bytes. changes to this register take effect immediat ely (not double buffered). the value in this register is 8-byte aligned. bits [2:0] are ignored.
506 amd geode? lx processors data book video input port register descriptions 33234h 6.10.2.25 vip page offset/ page count (vip_page_offset ) 6.10.2.26 vip vertical start/ stop (vip_vert_start_stop ) vip memory offset 68h ty p e r / w reset value 00000000h vip_page_offset register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 page_offset program to 00000 vip_page_offset bit descriptions bit name description 31:0 page_offset page offset. this register specifies the offset to t he next page of buffer data. if the page count is 2 or greater, the next frame of da ta is started at an address of buffer + page_offset. up to eight pages (frames) can be accumulated. the address of the next frame is located at a ?page offset? address. note that ancillary data and msg/ strm data is not paged. this only applies to video and vbi data. the value in this regis- ter needs to be 32-byte aligned. (bits [4:0] are required to be 00000.) vip memory offset 6ch ty p e r / w reset value 00000000h vip_vert_start_stop register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd vert_end rsvd vert_start vip_vert_start_stop bit description bit name description 31:28 rsvd reserved. set to 0. 27:16 vert_end vertical end capture. this register specifies the last line # in a field/frame that is cap- tured when the subwindow capture function is enabled in non bt.601 modes. in bt.601 interlaced modes, this register determines wh en the odd field line capture completes. in 601 non-interlaced modes, this register det ermines when the video capture completes. see figure 6-48 "bt.601 mode vertical timing" on page 473 for additional detail. 15:12 rsvd reserved. set to 0. 11:0 vert_start vertical start capture. this register specifies the first line # in a field/frame that is cap- tured when the subwindow capture function is enabled in non 601 modes. in bt.601 interlaced modes, this register determines wh en the odd field video capture starts. in bt.601 non-interlaced modes, this register determines when the video capture starts. see figure 6-48 "bt.601 mode vertical timing" on page 473 for additional detail.
amd geode? lx processors data book 507 video input port register descriptions 33234h 6.10.2.27 vip fifo address (vip_fifo_r_w_addr) 6.10.2.28 vip fifo da ta (vip_fifo_data) vip memory offset 70h ty p e r / w reset value 00000000h vip_fifo_r_w_addr register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd fifo_address vip_fifo_r_w_addr bit descriptions bit name description 31:9 rsvd reserved. set to 0. 8:0 fifo_address fifo address. fifo address for which a fifo read or write occurs. the data is writ- ten/read via the fifo data register (vip me mory offset 74h). note that the 256x64 bit fifo is mapped as a 512x32 bit memory. vip memory offset 74h ty p e r / w reset value xxxxxxxxh vip_fifo_data register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fifo_data vip_fifo_data bit descriptions bit name description 31:0 fifo_data fifo data . when the ff_r/w bit is set (vip memo ry offset 04h[24] = 1), data written to this register is stored in fifo_addr (vip memory offset 70h[7:0]). when the ff_r/w bit is reset, data from the fifo corresponding to the address in the fifo_addr is returned
508 amd geode? lx processors data book video input port register descriptions 33234h 6.10.2.29 vip vsync error co unt (vip_sync_err_count) 6.10.2.30 vip task a u even off set (vip_task_a_u_even_offset) vip memory offset 78h ty p e r / w reset value 00000000h vip_sync_err_count register map 313029282726252423222120191817161514131211109876543210 vertical_window vertical_count vip_sync_err_count bit descriptions bit name description 31:24 vertical_ window vertical window. this field defines the number of vip clocks the input vblank can vary before it is considered invalid. (16-4095 clocks) 23:0 vertical_ count vertical count. this field provides the check point for verifying that the input data stream is maintaining consistent vsync timing. this count is the minimum number of vip clocks expected in an input field (interlaced video) or frame (non-interlaced video). if the number of video clocks between rising edges of vblank is less then this number (or greater then vertical_count + vertical_windo w), a vsync error interrupt is gener- ated and the video_ok output signal is forced low indicating invalid input video. (0- 16,777,215 clocks) note: a 60 hz vblank rate @75 mhz input clock = 1,250,000 clocks. vip memory offset 7ch ty p e r / w reset value 00000000h vip_task_a_u_even_offset register map 313029282726252423222120191817161514131211109876543210 task_a_u_even_offset program to 00000 vip_task_a_u_even_offset bit descriptions bit name description 31:0 task_a_u_ even_offset task a u even offset. this register determines the st arting address of the u buffer for the even field when in interlaced input mode and data is stored in planar format. this reg- ister is not used when in non-interlaced input mode. the value in this register needs to be 32-byte aligned. (bits [4:0] are required to be 00000.)
amd geode? lx processors data book 509 video input port register descriptions 33234h 6.10.2.31 vip task a v even offs et (vip_task_a_v_even_offset) vip memory offset 80h ty p e r / w reset value 00000000h vip_task_a_v_even_offset register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 task_a_v_even_offset program to 00000 vip_task_a_v_even_offset bit descriptions bit name description 31:0 task_a_v_ even_offset task a v even offset. this register determines the star ting address of the v buffer for the even field when in interlaced input mode and data is stored in planar format. this reg- ister is not used when in non-interlaced input mode. the value in this register needs to be 32-byte aligned. (bits [4:0] are required to be 00000.)
510 amd geode? lx processors data book security block 33234h 6.11 security block the security block provides a hardware advanced encryp- tion standard (aes) encryption/decryption engine and interface for accessing eepr om memory for storing unique ids and/or security keys. the aes and eeprom sections have separate contro l registers but share a single set of interrupt registers. 6.11.1 security block features ? aes ? electronic code book (ecb) or cipher block chaining (cbc) 128-bit hardware encryption and decryption ? cbc 128-bit hardware encryption and decryption ? dma read and write (two contexts) ? hidden key, (stored on eeprom) ? writable key can be written by the x86 processor ? can use interrupts, smis, or be polled for completion status ? memory mapped register interface ? eeprom i/f ? provides 2k bit of eeprom storage ? programmable lock bits ? programmable ?hidden? aes key ? can use interrupts, smis, or be polled for completion status ? memory mapped register interface ? true random number generator (trng) ? read via msr note: for security purposes, the eeprom interface resets to the ?debug disabled? state. it takes approximately 490 us to read the eeprom and unlock the debug interface. therefore, the ?cpu stall? feature must be available even when the debug interface is di sabled. since the eeprom may not respond for up to 10 ms after a write oper- ation, the time out fo r accessing the eeprom is set to approximately 17 ms. therefore it takes approximately 17 ms for a part without an eeprom to unlock after the release from reset. 6.11.1.1 performance metrics ? system goals: ? 400 mhz gliu interface ? > 40 mb/sec. encrypt or decrypt figure 6-54. security block diagram scl sda security block gliu aes engine eeprom id interface dma to p i/o master slave rqout daout dain rqin . . . . . . true random number generator clock control unit clock control unit clock control unit sb specific registers eeprom
amd geode? lx processors data book 511 security block 33234h 6.11.2 functional description the aes engine provides ecb and cbc 128-bit hardware encryption and decryption for the amd geode lx proces- sor using the advanced encryption standard algorithm. the security block has two key sources. one is a hidden 128-bit key stored in non-volatile memory. it is expected that this key is loaded into the non-volatile memory once at the factory and the memory is locked to prevent future writes. this key is loaded automatically by hardware after reset and is not visible to the x86 processor, (also, these locations in non-volatile memory cannot be read using the non-volatile memory interface). the second key is writable, (but not readable) by the x86 processor. it appears as a series of four writable 32-bit qwords in the security block memory address space. reads to these registers always return zeros. note that these bits are accessible via the debug interface unless the debug interface has been locked. for any single operation, the security block can work in either encryption or decryption mode. the same two key registers (hidden and writable) are used for both modes. the security block provides a mastering dma interface to system memory. it contains tw o sets of pointer registers (contexts a and b) for controlling the dma operations. for each set, there is a 32-bit dma source register that points to the start of the source data in memory. the lower four lsbs are zero, forcing the address to align to a 16-byte boundary. there is a 32-bit dm a destination register that points to the region in memory where the aes block writes its results. this pointer also forces alignment to a 16-byte boundary. for consistency with other block architecture specifications, these regist ers are described as qwords in the security block memory space. in addition to the 32- bit dma source register, ther e is a 32-bit length register that holds a count of the numb er of bytes to be encrypted/ decrypted. again the lower four bits are zero forcing the length to be an integer multiple of 16-byte blocks. if the source data does not end on a 16-byte boundary, software must pad the data out to the next 16-byte boundary. having two separate contexts allows the software to queue a sec- ond encryption/decryption request while the first operation is completing. the security block only contains a single aes hardware block so the second request is not pro- cessed until the first request completes. the control registers (sb memory offset 00h and 04h) are used to configure the security block. there are two sets of control bits to select the key source (hidden vs. writable) and the operational mode (encryption/decryption), and the data coherency flags for memory accesses. there are also two start bits (a and b) to initiate an operation once the appropriate pointers have been configured. the security block can be configured to generate an interrupt on com- pletion of an encryption/decryption operation. alternatively, the interrupt can be masked and the completion bit can be polled. for each start command, the security block processes the data starting at the dma source address and continues for the number of bytes specified in the length register. the results are written starting at the address in the destination register. for each start command, the security block pro- cesses the data starting at the dma source address and continues for the number of bytes specified in the length register. the results are written starting at the address in the destination register. for each start command, the aes can be configured for key source, encryption/decryption mode, and memory coherence flags. no changes to the a registers should be made during an encryption or decryp- tion operation for a, and no changes to the b registers should be made during an encryption or decryption opera- tion for b. in cbc mode, the cbc initialization vector regis- ter value is used by both a and b channels. the amd geode lx processor supports aes cbc mode and a true random number generator. cbc encryption/ decryption is similar to ecb. when doing cbc mode encryption/decryption, the 128-bit initialization vector is written to the cbc initialization vector registers (sb mem- ory offset 40h-4ch) prior to the start of the encryption/ decryption. the random number generator function pro- vides true random numbers required for the initialization values for aes cbc encryption. software must read the 32-bit random number register four times to build the 128- bit initialization vector (iv) . this can then be used to pro- gram the cbc initialization vector registers prior to the cbc encryption.
512 amd geode? lx processors data book security block 33234h 6.11.2.1 eeprom id interface the eeprom id interface provides an interface to an eeprom non-volatile memory available for storing id numbers, keys, or other securi ty related information. the eeprom id interface consists of a 2k (256-byte) array with 2 bytes reserved for eeprom control state, 238 bytes are available as general purpose non-volatile storage, and 16 bytes reserved for use as a hidden key for the aes engine. (note that locations 18-33 are reserved for a unique id, but can be used for general purpose storage.) after reset, the eeprom id interface state machine reads the two access control bytes from the eeprom. these define the access policies for the eeprom. it also auto- matically copies the 128-bit hidden key from the array to the aes engine?s hidden key register. when an amd geode lx processor device is initially manufactured, the eeprom is programmed to all ones and the control bytes are set to the unlocked state allowing writing of the entire eeprom array and reading of all locati on except the hidden key. information can be stored in the eeprom and then optionally the eeprom can be locked to prevent fur- ther writes and/or disable ce rtain debug features of the amd geode lx processor. the eeprom controller defaults to the unlocked state if it cannot access an eeprom afte r reset. this allows parts built without eeproms to have functional debug inter- faces. the eeprom id interface works on a byte-wide basis. the eeprom address register (sb memory offset 804h) is first programmed by software, and then the eeprom command register (sb memory offset 804h) is written to initiate a write from the eeprom data register (sb mem- ory offset 808h) to the array or a read from the array to the data register. the start bit in the command register (sb memory offset 800h) resets automatically once the eeprom access has completed. the user may also enable an interrupt to be generated when the access has completed. since the eeprom access is slow, this simple command interface allows the processor to continue with other tasks while waiting for th e access to complete. table 6-77 shows common usage of the eeprom. note: the eeprom interface is designed to work with a gliu frequency up to 400 mhz. for operation above 400 mhz, several internal design parame- ters must be changed. 6.11.2.2 security block interrupts the security block has three possible sources for an inter- rupt: completion of an aes task on context a, completion of an aes task on context b, and completion of an eeprom read or write operation. the interrupt event and interrupt mask registers are memory mapped. these three sources can also generate an smi. the smi event and smi mask registers are accessible via msrs. any one of these events will simultaneously set the smi and interrupt event bits. the mask bits may be used to enable either an inter- rupt or an smi if desired. 6.11.2.3 gliu interface the gliu provides a standard interface to the amd geode lx processor. the security block is both a master and a slave on this bus. table 6-77. eeprom address map byte address range description 0 lower access control byte 0 (wpu and wpl) 1 access control byte 1 (wpe and dbl) 2-17 hidden key storage (128 bits) 18-33 unique id (128 bits) 34-127 user data 128-255 upper user data
amd geode? lx processors data book 513 security block register descriptions 33234h 6.12 security block register descriptions this section provides information on the registers associ- ated with the security block (sb), including the standard geodelink device (gld) msrs, the security block spe- cific msrs (accessed via the rdmsr and wrmsr instructions), and the security block configuration/control reg- isters. table 6-78 through table 6-80 are register summary tables that include reset values and page references where the bit descriptions are provided. the msr address is derived from the perspective of the cpu core. see section 4.1 "msr set" on page 45 for more detail on msr addressing. table 6-78. standard geodelink? device msrs summary msr address type register name reset value reference 58002000h ro gld capabilities msr (gld_msr_cap) 00000000_001304xxh page 515 58002001h r/w gld master configuration msr (gld_msr_config) 00000000_00000000h page 515 58002002h r/w gld smi msr (gld_msr_smi) 00000000_00000007h page 516 58002003h r/w gld error msr (gld_msr_error) 00000000_00000019h page 516 58002004h r/w gld power management msr (gld_msr_pm) 00000000_00000015h page 518 58002005h r/w gld diagnostic msr (gld_msr_diag) 00000000_00000000h page 518 table 6-79. security block specific msrs msr address type register name reset value reference 58002006h r/w gld control msr (gld_msr_ctrl) 00000000_00000003h page 519 table 6-80. security block configuration/control registers summary sb memory offset type register name reset value reference 000h r/w sb control a (sb_ctl_a) 00000000h page 520 004h r/w sb control b (sb_ctl_b) 00000000h page 521 008h r/w sb aes interrupt (sb_aes_int) 00000007h page 522 010h r/w sb source a (sb_source_a) 00000000h page 522 014h r/w sb destination a (sb_dest_a) 00000000h page 523 018h r/w sb length a (sb_length_a) 00000000h page 523 020h r/w sb source b (sb_source_b) 00000000h page 524 024h r/w sb destination b (sb_dest_b) 00000000h page 524 028h r/w sb length b (sb_length_b) 00000000h page 525 030h wo sb writable key 0 (sb_wkey_0) 00000000h page 525 034h wo sb writable key 1 (sb_wkey_1) 00000000h page 526 038h wo sb writable key 2 (sb_wkey_2) 00000000h page 526 03ch wo sb writable key 3 (sb_wkey_3) 00000000h page 527 040h r/w sb cbc initialization vector 0 (sb_cbc_iv_0) 00000000h page 527 044h r/w sb cbc initialization vector 1 (sb_cbc_iv_1) 00000000h page 528
514 amd geode? lx processors data book security block register descriptions 33234h 048h r/w sb cbc initialization vector 2 (sb_cbc_iv_2) 00000000h page 528 04ch r/w sb cbc initialization vector 3 (sb_cbc_iv_3) 00000000h page 528 050h ro sb random number (sb_random_num) 00000000h page 529 054h ro sb random number status (sb_random_num_status) 00000001h page 529 800h r/w sb eeprom command (sb_eeprom_comm) 00000000h page 530 804h r/w sb eeprom address (sb_eeprom_addr) 000000ffh page 531 808h r/w sb eeprom data (sb_eeprom_data) 00000000h page 531 80ch ro sb eeprom security state (sb_eeprom_sec_state) 00000000h page 532 table 6-80. security block configurati on/control registers summary (continued) sb memory offset type register name reset value reference
amd geode? lx processors data book 515 security block register descriptions 33234h 6.12.1 standard geodelink? (gld) device msrs 6.12.1.1 gld capabilities msr (gld_msr_cap) 6.12.1.2 gld master configur ation msr (gld_msr_config) msr address 58002000h ty p e r o reset value 00000000_001304xxh gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. 23:8 dev_id device id. identifies device (1304h). 7:0 rev_id revision id. identifies device revision. see amd geode? lx processors specification update document for value. msr address 58002001h ty p e r / w reset value 00000000_00000000h gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd pri rsvd pid gld_msr_config bit descriptions bit name description 63:7 rsvd reserved. 6:4 pri aes priority level . this is the priority level used by the aes interface. 3 rsvd reserved. 2:0 pid aes priority domain. assigned priority domain identifier.
516 amd geode? lx processors data book security block register descriptions 33234h 6.12.1.3 gld smi msr (gld_msr_smi) 6.12.1.4 gld error msr (gld_msr_error) msr address 58002002h ty p e r / w reset value 00000000_00000007h gld_msr_smi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd smi_stat us 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd smi_mask gld_msr_smi bit descriptions bit name description 63:35 rsvd reserved. 34:32 smi_status smi status. there are three smi status sources. for each source, the individual bit has the following meaning: 0: smi not pending. 1: smi pending. writing a 1 to the bit clears the status. bit 34: eeprom operation complete smi. bit 33: aes context b complete smi. bit 32: aes context a complete smi. 31:3 rsvd reserved. 2:0 smi_mask smi masks. there are three smi status masks. fo r each source, the individual bit has the following meaning: 0: enable. unmask the smi. 1: disable. mask the smi. bit 2: when enabled (0), allows eeprom operation complete smi. bit 1: when enabled (0), allows aes context b complete smi. bit 0: when enabled (0), allows aes context a complete smi. msr address 58002003h ty p e r / w reset value 00000000_00000019h
amd geode? lx processors data book 517 security block register descriptions 33234h gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd rb_err_status ra_err_status rsvd aes_err_status 313029282726252423222120191817161514131211109876543210 rsvd rb_err_mask ra_err_mask rsvd aes_err_mask gld_msr_error bi t descriptions bit name description 63:37 rsvd reserved. 36 rb_err_ status response b error status . when set, this bit indicates that context b received a response with either the ssmi or exception flag set. this can occur on any of the read responses or on the last write of an encrypt or decrypt operation that also requires a response. if the error occurs on a read resp onse, the operation is terminated and the state machine returns to idle and signals completion. write a one to this bit to clear the status. 35 ra_err_ status response a error status. when set, this bit indicate s that context a received a response with either the ssmi or exception flag set. this can occur on any of the read responses or on the last write of an encrypt or decrypt operation that also requires a response. if the error occurs on a read resp onse, the operation is terminated and the state machine returns to idle and signals completion. write a one to this bit to clear the status. 34-33 rsvd reserved. 32 aes_err_ status aes error status. reserved type. this bit is set if the module receives a transaction identified with a reserved transaction type. this implies a hardware error. 0: aes error not pending. 1: aes error pending. writing a 1 to this bit clears the status. 31:3 rsvd reserved. 4 rb_err_ mask response b error mask. when set, this bit masks the response b error (bit 36) and prevents generation of the e rror output. when cleared, the error is enabled and asser- tion of response b error will generate an error. 3 ra_err_ mask response a error mask. when set, this bit masks the response a error (bit 35) and prevents generation of the e rror output. when cleared, the error is enabled and asser- tion of response a error will generate an error. 2:1 rsvd reserved. 0 aes_err_ mask aes error mask. reserved type. 0: unmask the error (enabled). 1: mask the error (disabled).
518 amd geode? lx processors data book security block register descriptions 33234h 6.12.1.5 gld power management msr (gld_msr_pm) 6.12.1.6 gld diagnostic msr (gld_msr_diag) this register is reserved for internal use by amd and should not be written to. msr address 58002004h ty p e r / w reset value 00000000_00000015h gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pmd2 rsvd pmd1 rsvd pmd0 gld_msr_pm bit descriptions bit name description 63:5 rsvd reserved. 4pmd2 power mode 2 (eeprom). 0: disable clock gating. clocks are always on. 1: enable active hardware clock gating. 3 rsvd reserved. 2pmd1 power mode 1 (aes core, gliu clock/2). 0: disable clock gating. clocks are always on. 1: enable active hardware clock gating. 1 rsvd reserved. 0pmd0 power mode 0 (gliu clock). 0: disable clock gating. clocks are always on. 1: enable active hardware clock gating. msr address 58002005h ty p e r / w reset value 00000000_00000000h
amd geode? lx processors data book 519 security block register descriptions 33234h 6.12.2 security block specific msrs 6.12.2.1 gld control msr (gld_msr_ctrl) msr address 58002006h ty p e r / w reset value 00000000_00000003h gld_msr_ctrl register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd t_tm t_ne t_sel rsvd tw sby sbi div gld_msr_ctrl bit descriptions bit name description 63:12 rsvd reserved. these bits are implemented but reserved for future use. when writing to this msr, software should set these bits to 0 and ignore them on read. 11 t_tm trng test mode. this bits enables the trng test mode. deterministic trng values are generated when this bit is 1. 10 t_ne trng noise enable. this bit enables the noise generator for the trng. 0: disable. 1: enable. 9:8 t_sel trng sel. these bits select post proc essing of the trng output. 00: raw output. 01: lfsr output. 10: whitener output. 11: lfsr + whitener output. 7:5 rsvd reserved. these bits are implemented but reserved for future use. when writing to this msr, software should set these bits to 0 and ignore them on read. 4tw time write. this bit controls the eeprom writ e timing within the eeprom interface module. normally the eeprom in terface signals completion i mmediately after it finishes shifting out the last bit of a write operat ion. the start of any other eeprom access begins a polling process. once, the eeprom has completed its internally timed write operation, it responds to the polling and the next operation can begin. setting this bit causes the eeprom interface to delay for slightly more than 10 ms after writing to the eeprom, before indicating write completion. that is, the start bi t will be held high, and the interrupt and smi generation will be delayed for 10 ms. this ensures that the eeprom has completed its internal write and should be ready to re spond to the next access immediately. this is a ?chicken? bit to avoid using the acknowledge polling (as described in the atmel datasheet), after a write. 3 sby swap bytes. this bit controls a byte-swapping feature within the aes module. when set, the bytes within the 16-byte block are swapped on both aes dma reads and writes. byte 15 is swapped with byte 0, byte 14 is swapped with byte 1, etc. asserting this bit does not affect the slave operations to aes re gisters, (including t he writable key), nor does it affect eeprom operations. when th is bit is cleared, the dma operations read and write bytes with the same byte order as they appear in memory.
520 amd geode? lx processors data book security block register descriptions 33234h 6.12.3 security block config uration/control registers 6.12.3.1 sb control a (sb_ctl_a) 2 sbi swap bits. this bit controls a bit-swapping feature within the aes module. when set, the bits within each byte are swapped on both aes dma reads and writes. bit 7 is swapped with bit 0, bit 6 is swapped with 1, et c. asserting this bit does not affect the slave operations to aes regist ers, (including the writable key), nor does it affect eeprom operations. when this bit is cleared, the dma operations read and write bytes with the same bit order as they appear in memory. 1:0 div aes enable divider. these two bits control the ratio between the gliu clock frequency and the updating of the aes encryption engine register s. the aes module is clocked at the gliu frequency, however, the state regi sters only update on an enable pulse that occurs each n cycles, where n is determined by the div value. this register should not be changed during an aes operation. 00: divide by 1 (use for 100 mhz gliu or less). 01: divide by 2 (use for 100 mhz to 200 mhz gliu). 10: divide by 3 (use for 200 mhz to 300 mhz gliu). 11: divide by 4 (use for 300 mhz to 400 mhz gliu). sb memory offset 000h ty p e r / w reset value 00000000h gld_msr_ctrl bit descriptions (continued) bit name description sb_ctl_a register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd cbca sca dca wka eca sta sb_ctl_a register bit descriptions bit name description 31:8 rsvd reserved. 7:6 rsvd reserved. these bits are implemented but reserved for future use. when writing to this register, software should set these bits to 0 and ignore them on read. 5cbca cipher block chaining (cbc) mode for a pointer. when set, the aes engine encrypts/decrypts using the cipher block chaining mode for the a pointer. when reset, the aes engine encrypts/decrypts using the electronic codebook (ecb) mode. no ini- tialization vector is used when in ecb mode. 4sca source coherency for a pointer set. when set, the source memory fetches using the gliu interface are flagged as coherent oper ations. when reset, the operations are non- coherent. 3 dca destination coherency for a pointer set. when set, the destination memory writes using the gliu interface are flagged as coherent operations. when reset, the opera- tions are non-coherent. 2wka writable key for a pointer set. when set, the aes engine us es the key from the writ- able key register (sb memory offset 030h-03ch ) for its next operation. when reset, it uses the hidden key value. 1eca encrypt for a pointer. when set, the aes operates in encryption mode. when reset, it operates in decryption mode.
amd geode? lx processors data book 521 security block register descriptions 33234h 6.12.3.2 sb control b (sb_ctl_b) 0sta start for a pointer. when set, this bit commands t he aes to start a new operation based on the current control register setting and the settings in sb memory offset 010h and 014h. this bit is reset automatically wh en the operation completes. setting this bit also clears the ?complete? flag in the aes interrupt register (sb memory offset 008h[16]) and in sb gld_msr_smi (msr 5800 2002h[32]). if an operation using the b pointer set is already underway, the new operation for pointer set a will not start until the previous b operation completes. if both a and b start bits are asserted in the same write operation, the a operation take precedence. sb memory offset 004h ty p e r / w reset value 00000000h sb_ctl_a register bit descriptions (continued) bit name description sb_ctl_b register map 313029282726252423222120191817161514131211109876543210 rsvd rsvd cbcb scb dcb wkb ecb stb sb_ctl_b register bit descriptions bit name description 31:8 rsvd reserved. 7:6 rsvd reserved. these bits are implemented but reserved for future use. when writing to this register, software should set these bits to 0 and ignore them on read. 5cbcb cipher block chaining (c bc) mode for b pointer. when set, the aes engine encrypts/decrypts using the cipher block chai ning mode for the b pointer. when reset, the aes engine encrypts/decrypts using the electronic codebook (ecb) mode. no ini- tialization vector is used when in ecb mode. 4scb source coherency for b pointer set. when set, the source memory fetches using the gliu interface are flagged as coherent operations. when reset, the operations are non- coherent. 3 dcb destination coherency for b pointer set. when set, the destination memory writes using the gliu interface are flagged as coher ent operations. when reset, the operations are non-coherent. 2wkb writable key for b pointer set. when set, the aes engine uses the key from the writ- able key register (sb memory offset 030h-03ch) for its next operation. when reset, it uses the hidden key value. 1ecb encrypt for b pointer. when set, the aes operates in encryption mode. when reset, it operates in decryption mode. 0stb start for b pointer . when set, this bit commands t he aes to start a new operation based on the current control register setti ng and the settings in sb memory offset 020h and 024h. this bit is reset automatically wh en the operation completes. setting this bit also clears the ?complete? flag in the aes interrupt register (sb memory offset 008h[17]) and in the sb gld_msr_smi (msr 58002002h[33]). if an operation using the a pointer set is already underway, the new operation for pointer set b will not start until the previous a operation completes. if both a and b start bits are asserted in the same write operation, the a operation take precedence.
522 amd geode? lx processors data book security block register descriptions 33234h 6.12.3.3 sb aes interrupt (sb_aes_int) 6.12.3.4 sb source a (sb_source_a) sb memory offset 008h ty p e r / w reset value 00000007h sb_aes_int register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd int_status rsvd int_mask sb_aes_int register bit descriptions bit name description 31:19 rsvd reserved. 18:16 int_status aes interrupt status. 0: int not pending. 1: int pending. writing a 1 to this bit clears the status. 18: eeprom operation complete. 17: aes context b complete. 16: aes context a complete. 15:3 rsvd reserved. 2:0 int_mask aes interrupt mask. 0: enable, unmask the int. 1: disabled, mask the int. 2: when enabled (0), allows eeprom operation complete int. 1: when enabled (0), allows aes context b complete int. 0: when enabled (0), allows aes context a complete int. sb memory offset 010h ty p e r / w reset value 00000000h sb_source_a register map 313029282726252423222120191817161514131211109876543210 source_a rsvd sb_source_a register bit descriptions bit name description 31:4 source_a source a. the source field is a 32-bit pointer to system memory. it points to the start of data to be encrypted or decrypted. the lower four bits must be written as zero and always read zero. this forces the data fetching to begin on a 16-byte boundary. this register should not be chan ged during an aes encr yption or decrypti on operation using the a pointer (i.e., while sta is asserted, sb memory offset 000h[0] = 1). this register can be modified during an operation using the b pointer set (while stb is asserted, sb memory offset 004h[0] = 1). 3:0 rsvd reserved. set to 0.
amd geode? lx processors data book 523 security block register descriptions 33234h 6.12.3.5 sb destination a (sb_dest_a) 6.12.3.6 sb length a (sb_length_a) sb memory offset 014h ty p e r / w reset value 00000000h sb_dest_a register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destination a rsvd sb_dest_a register bit descriptions bit name description 31:4 dest_a destination a. the destination field is a 32-bit pointer to system memory. it points to the start of memory where the results of encryption or decryption operation are to be written. the lower four bits must be written as zero and always read zero. this forces the data writing to begin on a 16-byte boundary. this register should not be changed during an aes encryption or dec ryption operation using the a pointer set (i.e., while sta is asserted, sb memory offset 000h[0] = 1). this register can be modified during an operation using the b pointer set (while stb is asserted, sb memory offset 004h[0] = 1). 3:0 rsvd reserved. set to 0. sb memory offset 018h ty p e r / w reset value 00000000h sb_length_a register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 length_a rsvd sb_length_a register bit descriptions bit name description 31:4 length_a length a. the length field is a 32-bit value that describes the number of bytes to be encrypted or decrypted in the next operati on using pointer set a. the lower four bits must be written as zero and always read zero. this forces the data length to be an inte- ger number of 16-byte blocks. this re gister should not be changed during an aes encryption or decryption operation using the a pointer set (i.e., while sta is asserted, sb memory offset 000h[0] = 1). this register can be modified during an operation using the b pointer set (while stb is asse rted, sb memory offset 004h[0] = 1). 3:0 rsvd reserved.
524 amd geode? lx processors data book security block register descriptions 33234h 6.12.3.7 sb source b (sb_source_b) 6.12.3.8 sb destination b (sb_dest_b) sb memory offset 020h ty p e r / w reset value 00000000h sb_source_b register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 source_b rsvd sb_source_b register bit descriptions bit name description 31:4 source_b source b. the source field is a 32-bit pointer to system memory. it points to the start of data to be encrypted or decrypted. the lower four bits must be written as zero and always read zero. this forces the data fetching to begin on a 16-byte boundary. this register should not be chan ged during an aes encr yption or decrypti on operation using the a pointer set (i.e., while sta is asserted, sb memory offset 000h[0] = 1). this regis- ter can be modified during an operation using the b pointer set (while stb is asserted, sb memory offset 004h[0] = 1). 3:0 rsvd reserved. set to 0. sb memory offset 024h ty p e r / w reset value 00000000h sb_dest_b register map 313029282726252423222120191817161514131211109876543210 dest_b rsvd sb_dest_b register bit descriptions bit name description 31:4 dest_b destination b. the destination field is a 32-bit pointer to system memory. it points to the start of memory where the results of en cryption or decryption operation are to be written. the lower four bits must be written as zero and always read zero. this forces the data writing to begin on a 16-byte boundary. this register should not be changed during an aes encryption or decryption operation using the a pointer set (i.e., while sta is asserted, sb memory offset 000h[0] = 1). th is register can be modified during an oper- ation using the b pointer set (while stb is asserted, sb memory offset 004h[0] = 1). 3:0 rsvd reserved. set to 0.
amd geode? lx processors data book 525 security block register descriptions 33234h 6.12.3.9 sb length b (sb_length_b) 6.12.3.10 sb writable key 0 (sb_wkey_0) sb memory offset 028h ty p e r / w reset value 00000000h sb_length_b register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 length_b rsvd sb_length_b register bit descriptions bit name description 31:4 length_b length b. the length field is a 32-bit value that describes the number of bytes to be encrypted or decrypted in the next operati on using pointer set b. the lower four bits must be written as zero and always read zero. this forces the data length to be an inte- ger number of 16-byte blocks. this register should not be changed during an aes encryption or decryption operation using the a pointer set (i.e., while sta is asserted, sb memory offset 000h[0] = 1). this register can be modified during an operation using the b pointer set (while stb is asserted, sb memory offset 004h[0] = 1). 3:0 rsvd reserved. set to 0. sb memory offset 030h ty p e w o reset value 00000000h sb_w_key0 register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w_ey_0[31:0] sb_wkey_0 bit descriptions bit name description 31:0 wkey_ 0 writable key 0. bits [31:0] of the writable key fo r the security block. this register should not be changed during an aes encrypti on or decryption operation. to prevent one process from reading the key written by a nother process, this register is not read- able.
526 amd geode? lx processors data book security block register descriptions 33234h 6.12.3.11 sb writable key 1 (sb_wkey_1) 6.12.3.12 sb writable key 2 (sb_wkey_2) sb memory offset 034h ty p e w o reset value 00000000h sb_wkey_1 register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wkey_1[63:32] sb_wkey_1 bit descriptions bit name description 31:0 wkey_1 writable key 1. bits [63:32] of the writable key fo r the security block. this register should not be changed during an aes encrypti on or decryption operation. to prevent one process from reading the key written by a nother process, this register is not read- able. sb memory offset 038h ty p e w o reset value 00000000h sb_wkey_2 register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wkey_2[95:64] sb_wkey_2 bit descriptions bit name description 31:0 wkey_2 writable key 2. bits [95:64] of the writable key fo r the security block. this register should not be changed during an aes encryption or decryption operation. to prevent one process from reading the key written by a nother process, this register is not read- able.
amd geode? lx processors data book 527 security block register descriptions 33234h 6.12.3.13 sb writable key 3 (sb_wkey_3) 6.12.3.14 sb cbc initializatio n vector 0 (sb_cbc_iv_0) sb memory offset 03ch ty p e w o reset value 00000000h sb_wkey_3 register map 313029282726252423222120191817161514131211109876543210 wkey_3[127:96] sb_wkey_3 bit descriptions bit name description 31:0 writable key 3 writable key 3. bits [127:96] of the writable key fo r the security block. this register should not be changed during an aes encryption or decryption operation. to prevent one process from reading the key written by a nother process, this register is not read- able. sb memory offset 040h ty p e r / w reset value 00000000h sb_cbc_iv_0 register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cbc_iv_0[31:0] sb_cbc_iv_0 bit descriptions bit name description 31:0 cbc_iv_0 [31:0] cbc initialization vector 0 [31:0]. bits [31:0] of the initializa tion vector (iv) for the cbc aes mode (cipher block chaining). change this register only when both a and b chan- nels are idle. (a and b start bits, sb memory offset 000h and 004h, bit 0 = 0). this reg- ister must be programmed with the iv vector prior to starting an aes cbc mode encryption or decryption.
528 amd geode? lx processors data book security block register descriptions 33234h 6.12.3.15 sb cbc initializatio n vector 1 (sb_cbc_iv_1) 6.12.3.16 sb cbc initializatio n vector 2 (sb_cbc_iv_2) 6.12.3.17 sb cbc initializatio n vector 3 (sb_cbc_iv_3) sb memory offset 044h ty p e r / w reset value 00000000h sb_cbc_iv_1 register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cbc_iv_1[63:32] sb_cbc_iv_1 bit descriptions bit name description 31:0 iv[63:32] cbc initialization vector 1 [63:32]. bits [63:32] of the iv for the cbc aes mode. change this register only when both a and b channels are idle. (a and b start bits, sb memory offset 000h and 004h, bit 0 = 0). this register must be pr ogrammed with the iv prior to starting an aes cbc mode encryption or decryption. sb memory offset 048h ty p e r / w reset value 00000000h sb_cbc_iv_2 register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cbc_iv_2[95:64] sb_cbc_iv_2 bit descriptions bit name description 31:0 cbc_iv_2 [95:64] cbc initialization vector 2 [95:64]. bits [95:64] of the iv for the cbc aes mode. change this register only when both a and b channels are idle. (a and b start bits, sb memory offset 000h and 004h, bit 0 = 0). this register must be pro- grammed with the iv prior to starting an aes cbc mode encrypt ion or decryption. sb memory offset 04ch ty p e r / w reset value 00000000h sb_cbc_iv_3 register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cbc_iv_3[127:96] (rev2.0) sb_cbc_iv_3 bit descriptions bit name description 31:0 cbc_iv_3 [127:96] cbc initialization vector 3 [127:96]. bits [127:96] of the iv for the cbc aes mode. change this register only when both a and b channels are idle. (a and b start bits, sb memory offset 000h and 004h, bit 0 = 0). this register must be programmed with the iv prior to starting an aes cbc mode encryption or decryption.
amd geode? lx processors data book 529 security block register descriptions 33234h 6.12.3.18 sb random number (sb_random_num) 6.12.3.19 sb random number status (sb_random_num_status) sb memory offset 050h ty p e r o reset value 00000000h sb_random_num register map 313029282726252423222120191817161514131211109876543210 random_num sb random number bit descriptions bit name description 31:0 random_ num random number. returns a 32-bit random number. check the trng_valid bit (sb memory offset 054h[0]) before reading this register. if the status bit (trng_valid) is 1, the value in this register is ready for use. a 0 in the status bit indicates that the ran- dom number is in the process of being generated. sb memory offset 054h ty p e r o reset value 00000001h sb_random_num_status register map 313029282726252423222120191817161514131211109876543210 rsvd trng_valid sb_random_num_status bit descriptions bit name description 31:1 rsvd reserved. returns 0. 0 trng_valid random number valid. when 1, the random number is valid. when 0, the random number is in the process of being generated.
530 amd geode? lx processors data book security block register descriptions 33234h 6.12.3.20 sb eeprom co mmand (sb_eeprom_comm) sb memory offset 800h ty p e r / w reset value 00000000h sb_eeprom_comm register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd rsvd hkd sl kv ex wr st sb_eeprom_comm bit descriptions bit name description 31:8 rsvd reserved. 7:6 rsvd reserved. these bits are implemented but reserved for future use. when writing to this register, software should set these bits to 0 and ignore them on read. 5hkd hidden key disable. reset to 0. when set, this bit disables the hidden key by forcing all of the bits to zero. this bit can be written to a 1 by software, but once set, it can only be cleared by reset. setting this bit also forces the key valid bit (bit 3) to 0. 4sd soft lock. reset to 0. when set, this bit locks the same debug functions locked by the dbl bit (sb memory offset 80ch[10:8]), and is displayed in the access control register. this bit can be written to a 1 by software, but once set, it can only be cleared by reset. 3kv key valid. reset to 0. after reset, this bit is set automatically by the state machine to indicate that the automatic load of the hidden key into the aes key register has com- pleted and the key is now ready for use. no aes operations using the hidden key regis- ter should be initiated before this bit is set. this bit is cleared by reset or by asserting the hidden key disable bit (bit 5). 2ex exception. the current access operation did not co mplete successfully. note that this bit may also be set after a reset if the init ial read of the eeprom control bytes or hidden key did not complete successfully . this bit should only be set on a fatal hardware access error. write 1 to clear. if the exception occu rs on the initial eeprom read after reset, it is assumed that no eeprom is preset and the eeprom interface is disabled. when the interface is disabled, this bit is not clearable. 1wr write. when set, the eeprom interface initia tes a write operation to the eeprom when the start bit (bit 0) is set. when reset, the eeprom interface initiates a read operation when the start bit is set. 0st start. when set, this bit commands the eeprom interface to start a new operation based on the current control register setting and the settings in the address and data registers. this bit is reset automatically when the operation completes. setting this bit also clears the eeprom complete flag in th e aes interrupt register (sb memory offset 008h[18]) and in the smi msr register (msr 58002002h[34]).
amd geode? lx processors data book 531 security block register descriptions 33234h 6.12.3.21 sb eeprom address (sb_eeprom_addr) 6.12.3.22 sb eeprom data (sb_eeprom_data) this register co ntains the data bits for writing to or reading from the eeprom. sb memory offset 804h ty p e r / w reset value 000000ffh sb_eeprom_addr register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd rsvd ee_addr sb_eeprom_addr bit descriptions bit name description 31:11 rsvd reserved. 10:8 rsvd reserved. these bits are reserved for future expansion of the eeprom size and must be written to 0. 7:0 ee_addr eeprom address . this is the 8-bit address for accessing one of the 256 bytes within the eeprom array. sb memory offset 808h ty p e r / w reset value 00000000h sb_eeprom_data register map 313029282726252423222120191817161514131211109876543210 rsvd ee_data sb_eeprom_data bit descriptions bit name description 31:8 rsvd reserved. 7:0 ee_data eeprom data. this register holds the 8-bit data value to be written the eeprom array or the data most recently read from the array. note that when reading a hidden location, this register will return the previous read or write data with no indication of an error. writes to locked locations are ignored with no indication of an error.
532 amd geode? lx processors data book security block register descriptions 33234h 6.12.3.23 sb eeprom security state (sb_eeprom_sec_state) this read only register contains the curr ent state of the access control bits for controlling reads and writes from/to the eeprom. it is reloaded from the eeprom arra y after every reset. the in itial state of the eeprom is all ones. therefore the unlocked state of the control bits must be one. the user loc ks the part by programming zeroes into the protect bits of the access control bytes. each lock control is a 3-bit field. the us er normally programs all three bits to a zero. the multi-bit fields are used to prevent a single bit dist urb of the eeprom array from unlocking the part. sb memory offset 80ch ty p e r o reset value 00000000h sb_eeprom_sec_state register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eeprom byte 1 eeprom byte 0 rsvd wpe dbl rsvd wpu wpl sb_eeprom_sec_state bit descriptions bit name description 31:14 rsvd reserved. 13:11 wpe write protect extended. reserved for future use. this register holds the 3-bit value of the access control bits used to block write access to any address above the 2 kbit range (byte address greater than 255). this is in cluded for possible future support of larger eeprom memories. with the currently specif ied 2 kbit memory, these bits have no effect. if any of these bits are reset, wr ite operations are blocked to addresses above 255. these bits correspond to the state of bits [5:3] of byte 1of the eeprom array as read after the last reset. to change these bits, the user must program the access con- trol byte 1 (address 1 of the eepr om), and the part must be reset. 10:8 dbl debug lock. this register holds the 3-bit value of the access control bits used to dis- able certain debug features of the amd geode lx processor. if any of these bits are reset, debug operations are blocked. these bi ts correspond to the st ate of bits [2:0] of byte 1 of the eeprom array as read after the last reset. to change these bits, the user must program the access cont rol byte 1 (address 1 of the eeprom), and the part must be reset. although reset to the locked state (000), these bits will revert to the unlocked state (111), if no eeprom is detected after reset. this unlocking will occur approxi- mately 17 ms after the release from reset with no eeprom present. 7:6 rsvd reserved. 5:3 wpu write protect upper. this register holds the 3-bit val ue of the access control bits used to block write access to the upper half of the eeprom array, (address 120 through 255). if any of these bits are reset, write o perations are blocked. these bits correspond to the state of bits [5 :3] of byte 0 of the eeprom array as read after the last reset. to change these bits, the user must program t he access control byte 0 (address 0 of the eeprom), and the par t must be reset. 2:0 wpl write protect lower. this register holds the 3-bit value of the access control bits used to block write access to the lower half of the eeprom array, (address 0 through 127). (note, these addresses include these access cont rol bits as well as the hidden key bits.) if any of these bits are rese t, write operations are blocked forever. these bits correspond to the state of bits [2 :0] of byte 0 of the eeprom array as read after the last reset. to change these bits, the user must program t he access control byte 0 (address 0 of the eeprom), and the par t must be reset.
amd geode? lx processors data book 533 geodelink? control processor 33234h 6.13 geodelink? control processor the geodelink control processor (glcp) functionality covers these areas (see figure 6-55): ? scan chain control ? jtag interface to boundary scan, bist, gliu1, and debug logic ? power (clock) control ? reset logic ? pll control ? internal logic analyzer/debugger ? 1kb fifo/sram ? compliant with gliu system architecture specification v1.07 ? supports amd geode? cs5536 companion device interface ? supports physical pins for suspa# and irq13 ? supports muxed pin for susp# 6.13.1 tap controller the tap controller is ieee 1149.1 compliant. tms, tdi, tclk, and tdo are directly supported (trst is available as a bootstrap pin during reset, but is always inactive if the system reset is inactive). the instruction register (ir) is 25 bits wide. the meanings of the various instructions are shown in table 6-81 on page 534 along with the length of the data register that can be accessed once the instruction is entered. all data registers shift in and out data, lsb first. the instruction and all data registers are shift registers, so if more bits are shifted in than the register can hold, only the last bits shifted in (the msbs) are used. the tap controller has specific pre-assigned meanings to the bits in the 25-bit ir. the meanings are summarized in table 6-82 on page 534. note that the bits only affect the chip once the ?update-ir? jtag state occurs in the jtag controller. shifting through these bits does not change the state of internal signals (for example test_mode). for details on jtag controller st ates, refer to the ieee stan- dard 1149.1-1990. figure 6-55. glcp block diagram debug debug action decode gliu interface debug control diagnostic bus scan, bist, clock, reset, suspend signals tclk tms tdi tdo rqin, rqout, dain, daout off-chip diagnostic pins gliu clock frequency debug clock frequency (varies) tclk clock frequency data and control buses control only event generator ieee 1149.1 interface comparators clock, reset, acpi control scan and bist control serial-to-gliu conversion 128 word 64-bit fifo tdbgi, tdbgo irq13 inta# susp# suspa# gio_ignne va_ferr gio_nmi gio_init gio_intr pci clock frequency gio synchronizing amd geode? companion device interface (gio)
534 amd geode? lx processors data book geodelink? control processor 33234h table 6-81. tap control instructions (25-bit ir) instruction dr length ir name description 123fffah 8 bypass_modes this register is read/write. 127fffah 8 revid should be 10h for initial amd geode? lx processor (upper nibble is major rev, lower nibble is minor) changes for each metal spin 1fffeb0h 441 multiscan parallel scan (muxes scan outputs onto many chip pins) 1ffffdfh 1 tristate put chip into tri-state and comparison mode 1fffffdh 29 bistdr parallel ram bist - inte rnal data register (for chip test) 1fffffeh 32 idcode id code = 0d5a1003h 1ffffffh 1 bypass bypass; ieee 1149.1 spec requir es all 1s to be bypass table 6-82. tap instruction bits bit name description 24 tapscan# also user[6] in the design. this is a user bit added by amd; low indicates that an inter- nal scan chain is accessed by the tap. 23:18 user[5:0] user bits used to identify an internal scan chain or, if bit 24 is high, to access a special internal dr, as shown in table 6-81. 17:16 bistenable[4:3] bits 4 and 3 of the bist enable for individual bist chain access. 15:13 clkratio[2:0]# not used in the amd geode? lx pr ocessor (bits should always be high); clock ratio controls for logicbist. 12 freezemode not used in the amd geode lx processor (should always be high); another clock con- trol signal. 11:10 setupmode[1:0]# not used in t he amd geode lx processor (should always be high); these are special bist controller bits. 9:7 bistenable[2:0] bist[2:0] of bist enable . works in conjunction with bits [17:16]. 6 testmode# active low test_mode for entire chip. puts internal logic into scan test mode. 5 forcedis# active low bit tri-states all output pins. 4 selectjtagout# active low bit that allows boundary scan cells to control pads. 3 selectjtagin# active low bit that allows boundary scan cells to drive data into core logic of chip. 2:0 op[2:0] opcode that se lects how the jtag chains are wired together.
amd geode? lx processors data book 535 geodelink? control processor 33234h extest jtag instruction the extest instruction a ccesses the boundary scan chain around the chip and controls the pin logic such that the boundary scan data controls the data and enable sig- nals for the pins. ieee 1149.1 requires that an all-zero instruction access the boundar y scan chain; the controller actually catches the all-zero condition during the ?update- ir? state and loads 1ffffe8h into the internal instruction register. as seen by table 6-82, this select op = 000 (access boundary scan chain) and selectjtagout# is set active so that the boundary cells control the pads. delay_controls this chain controls the delay timing for the inputs and out- puts. this register can be overridden with an msr write to glcp_delay_controls (glcp msr 4c00000fh) if bit 63 of the msr is set high. bits [62:0] of this register have the same meaning as in the msr description for glcp_delay_controls (see section 6.14.2.8 on page 549). revid this 8-bit jtag register can be reprogrammed with any metal layer change to identify silicon changes. this register has the same value as the glcp rev_id bits (msr 4c002000h[7:0]). multiscan during manufacturing test, multiple scan chains are avail- able on the signal pins. table 6-81 on page 534 identifies the specific scan behaviors of various pins when in this mode. the data register asso ciated with this tap instruc- tion is the boundary scan chain and the instruction bits configure the pads such that the boundary scan ring is pro- viding data into the core and the captured data on the boundary scan chain is the data coming from the core. tri-state this instruction tri-states all of the signals. the data register accessed is the bypass register. bypass according to ieee 1149.1, shifti ng all 1s into the ir must connect the 1-bit bypass register . the register has no func- tion except as a storage flip-flop. 6.13.2 reset logic one of the major functions of the glcp is to control the resetting of the amd geode lx processor. there are two methods to reset the processor: either by a hard reset using the input signal reset#, or by a soft reset by writing to an internal msr in the glcp. reset# is used for power-on reset. during power-on reset, all internal blocks are reset until the release of the reset# signal. soft reset is activated by writing to glcp_sys_rstpll (msr 4c000014h). soft reset resets all the internal blocks to their initial status except the tap controller. tap reset is achieved by holding irq13 low during power-on reset. 6.13.3 clock control the clock control function controls the generation of the amd geode lx processor internal clocks. for this pur- pose, there are two msrs: glcp_sys_rstpll and glcp_dotpll (msr 4c000014h and 4c000015h). as shown in figure 6-56 on page 536, the internal clocks are generated by syspll and dotpll. in normal opera- tion mode msr 4c000014h[12, 11] = 0 and msr 4c000015h[15] = 0. the syspll output clock drives the internal clocks of the cpu core, the geodelink modules, and sdram. the output of dotpll drives the dotclk, that in turn, drives the video processor and display con- troller modules. in bypass mode, when msr 4c000014h[12] = 1, the dot- ref input clock drives the clocks of the gliu and sdram, and when msr 4c000014h[11] = 1 the dotref input clock drives the clocks of the cpu core. also, when glcp_dotpll[15] = 1, the dotref input drives the dotclk. 6.13.3.1 power management the glcp controls the chip-wide power management by controlling when to activate and deactivate the pll clocks of the amd geode lx processor. selection of module-level hardware clock gating is done by programming the gld_msr_pm (msr 4c002004h) of each module. when hardware clock gating is activated, each module enters into power save mode when it is not busy, and leaves power save mode if a new geodelink request or external event is received. each module has a power management module called clock control. gliu1 power management support the glcp msrs directly involved in power management are: ? glcp clock disable delay value (glcp_clk_dis_delay) ? glcp global power management controls (glcp_glb_pm) ? glcp clock mask for sleep request (glcp_pmclkdisable) ? glcp clock active mask for suspend acknowledge (glcp_clk4ack) ? glcp control (glcp_cnt) ? glcp level 2 (glcp_lvl2) ? glcp throttle or c2 start delay (glcp_th_sd) ? glcp scale factor (glcp_th_sf) ? glcp processor throttle off delay (glcp_th_od)
536 amd geode? lx processors data book geodelink? control processor 33234h figure 6-56. processor clock generation 6.13.4 companion device interface the amd geode companion device interface for i/o con- nections (gio) provides the system interface between the amd geode cs5536 companion device and the amd geode lx processor. the gio supports companion device modes for current and future companion device needs. the major blocks (shown in figure 6-57 on page 537) of the gio are: ? gio_gliu ? gio_sync ? gio_pci features ? cs5536 companion device support: ? supports cpu interface serial (cis) that mux'es signals: input_disable , output_disable and legacy (lgcy) signals: a20m, init, susp, nmi, intr, smi. ? system interface signals clocked on raw pci input clock. ? no master capabilities. 6.13.4.1 gio_gliu the gio_gliu interface module is responsible for all the gliu slave functionality. the gio_gliu slave implements a large msr space consisting of the required standard gliu device msrs and the msr controls for the i/o com- panion modes and the legacy signals. the gio_gliu must properly decode all possible gliu transaction types including the unexpected addresses, request types and sizes, and must return the proper number of responses. in addition, it provides error logic to detect unexpected addresses and types and implements the processor float- ing point exception handling logic. 6.13.4.2 gio_sync the gio synchronization module, gio_sync, handles synchronization of all signals that cross from the gliu to pci domain or pci to gliu domain. 6.13.4.3 gio_pci the gio_pci module drives the values of the system inter- face signals. table 6-83 on page 537 shows the source of each output signal in each of the amd geode companion device modes. syspll dotpll dotref sysref glcp_dotpll[15] glcp_sys_rstpll[12] sdram clocks gl clocks dotclk pci cpu core glcp_sys_rstpll[11] dividers
amd geode? lx processors data book 537 geodelink? control processor 33234h figure 6-57. gio interface block diagram gio_gliu gio_sync gio_pci gio_a20m gio_nmi gio_susp gio_init gio_input_dis gio_output_dis gio_intr glcp_suspa rq13 suspa# gliu slave i/f ignne# ferr irq13_gl smi_gl lgcy_gl gl clock pci_raw_clk clk control susp# / cis table 6-83. gio_pci outputs gio output mode a mode b gio_susp susp# pin in serial mode susp# pin in serial mode gio_suspa suspa# pin suspa# pin gio_irq13 irq13 pin irq13 pin
538 amd geode? lx processors data book geodelink? control processor 33234h gio_pci serial protocol the gio can override the func tionality of its susp# pin to create a serial bus called cpu interface serial (cis). the reset mode for this pin is the susp# function. to properly operate as the cis interface, the cism bit in msr 51000010h[4:3] in the companion device must be pro- grammed for mode c. notice that all the input signals are active low. they are all inverted inside the gio and con- verted to active high signals. the protocol is shown in table 6-84. the susp# pin must always be parked as inactive or 1. serial packets are expected whenever the companion device signals transitions. back to back serial packets can occur once the entire serial packet has completed. the amd geode lx processor decoded signals are guaran- teed to transition only after t he entire completion of the packet, although they may transition during the transmis- sion of the packet. susp#/cis pin initialization the susp# function must not be active until the initializa- tion code can set the cism bits in the companion device to set the correct companion device mode. gio_smi synchronization if the companion device generates a synchronous smi in response to a specific cpu initiated instruction (i/o), the smi# signal is transmitted to the processor before the com- pletion of the pci cycle. therefore, the companion device must not complete read or wr ite cycles until it has transmit- ted the smi. the design guara ntees that if the pci cycle completes on the pciclk after the smi transmission, the smi will reach the processor before the i/o completion response. therefore, the processor can handle the smi before completing the instruction. gio_a20m gio_a20m is emulated with an smi. the processor receives an smi from the companion device on i/os that modify the state of a20m. t he smi handler must then write to msr_a20m (msr 4c000031h) in the gio to trigger a real a20m signal back to the processor. when the instruc- tion completes, a20m is asserted. gio_nmi the gio_nmi signal is the real nmi from the companion device. gio_input_dis, gio_output_dis gio_input_dis and gio_output_dis are part of the gliu power management. see the amd geode? cs5536 companion device data book (publication id 33238) for details. gio_init gio_init is triggered via msr 4c000033h in the glcp for all companion device modes. init is used to reset the cpu. it is not a cpu soft reset. table 6-84. cis signaling protocol phase bit definition (gio cis mode c) 0 (start) 0 1 (start) 0 2 rsvd 3 rsvd 4 susp# 5nmi# 6 input_dis# 7 output_dis# 8smi# 9 intr# 10 1 11 1 12 1 13 1 14 1 15 1 16 1 17 1 18 (end) 1 19 (end) 1
amd geode? lx processors data book 539 geodelink? control processor register descriptions 33234h 6.14 geodelink? control pr ocessor register descriptions all geodelink control processor registers are model spe- cific registers (msrs) and are accessed via the rdmsr and wrmsr instructions. the registers associated wit h the glcp are the standard geodelink? device (gld) msrs and glcp specific msrs. table 6-85 and table 6-86 are register summary tables that include reset values and page references where the bit descriptions are provided. note: the msr address is derived from the perspective of the cpu core. see section 4.1 "msr set" on page 45 for more details on msr addressing. table 6-85. standard geodelink? device msrs summary msr address type register name reset value reference 4c002000h ro gld capabilities msr (gld_msr_cap) 00000000_00002400h page 541 4c002001h r/w gld master configuration msr (gld_msr_config) 00000000_00000000h page 541 4c002002h r/w gld smi msr (gld_msr_smi) 00000000_0000001fh page 542 4c002003h r/w gld error msr (gld_msr_error) 00000000_00000000h page 543 4c002004h r/w gld power management msr (gld_msr_pm) 00000000_00000015h page 544 4c002005h r/w gld diagnostic msr (gld_msr_diag) 00000000_00000000h page 544 table 6-86. glcp specific msrs summary msr address type register name reset value reference glcp control msrs 4c000008h r/w glcp clock disable delay value (glcp_clk_dis_delay) 00000000_00000000h page 545 4c000009h r/w glcp clock mask for sleep request (glcp_pmclkdisable) 00000000_00000000h page 545 4c00000ah ro chip fabrication information (glcp_fab) 00000000_00000001h page 547 4c00000bh r/w glcp global power management controls (glcp_glb_pm) 00000000_00000000h page 547 4c00000ch r/w glcp debug output from chip (glcp_dbgout) 00000000 00000000h page 548 4c00000dh r/w glcp processor status (glcp_procstat) bootstrap dependant page 548 4c00000eh r/w glcp dowser (glcp_dowser) 00000000_00000000h page 549 4c00000fh r/w glcp i/o delay controls (glcp_delay_controls) 00000000_00000000h page 549 4c000010h r/w glcp clock control (glcp_clkoff) 00000000_00000000h page 551 4c000011h ro glcp clock active (glcp_clkactive) input determined page 552 4c000012h r/w glcp clock mask for debug clock stop action (glcp_clkdisable) 00000000_00000000h page 553 4c000013h r/w glcp clock active mask for suspend acknowledge (glcp_clk4ack) 00000000_00000000h page 553 4c000014h r/w glcp system reset and pll control (glcp_sys_rstpll) bootstrap specific page 554
540 amd geode? lx processors data book geodelink? control processor register descriptions 33234h 4c000015h r/w glcp dot clock pll control (glcp_dotpll) 000000d7_02000000h page 557 4c000016h r/w glcp debug clock control (glcp_dbgclkctl) 00000000_00000002h page 559 4c000017h ro chip revision id (glcp_chip_revid) 00000000_000000xxh page 559 glcp i/o address msrs 4c000018h r/w - i/o offset 00h glcp control (glcp_cnt) 00000000_000000fh page 560 4c000019h r/w - i/o offset 04h glcp level 2 (glcp_lvl2) 00000000_00000000h page 560 4c00001ah -- reserved -- -- 4c00001bh -- reserved -- -- 4c00001ch r/w - i/o offset 10h glcp throttle or c2 start delay (glcp_th_sd) 00000000_00000000h page 561 4c00001dh r/w - i/o offset 14h glcp scale factor (glcp_th_sf) 00000000_00000000h page 561 4c00001eh r/w - i/o offset 18h glcp processor throttle off delay (glcp_th_od) 00000000_00000000h page 562 4c00001eh r/w - i/o offset 18h glcp processor throttle off delay (glcp_th_od) 00000000_00000000h page 562 4c00001fh -- reserved -- -- glcp debug interface msrs 4c000023h r/w glcp dac (glcp_dac) 00000000_00000000h page 563 glcp ignne i/os f0h, f1h w glcp ignne i/os na page 562 glcp i/o companion interface msrs 4c000031h r/w cpu a20m signal (msr_a20m) 00000000_00000000h page 564 4c000033h r/w cpu init signal (msr_init) 00000000_00000000h page 564 4c000036h ro gliu device interrupt status (msr_intax) 00000000_00000000h page 565 table 6-86. glcp specific msrs summary (continued) msr address type register name reset value reference
amd geode? lx processors data book 541 geodelink? control processor register descriptions 33234h 6.14.1 standard geodelink? device msrs 6.14.1.1 gld capabilities msr (gld_msr_cap) 6.14.1.2 gld master configur ation msr (gld_msr_config) msr address 4c002000h ty p e r o reset value 00000000_00002400h gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. reads as 0. 23:8 dev_id device id. identifies device (0024h). 7:0 rev_id revision id. identifies device revision. see amd geode? lx proce ssors specification update document for value. msr address 4c002001h ty p e r / w reset value 00000000_00000000h gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pid gld_msr_config bit descriptions bit name description 63:3 rsvd reserved. write as read. 2:0 pid assigned priority domain. unused by the glcp.
542 amd geode? lx processors data book geodelink? control processor register descriptions 33234h 6.14.1.3 gld smi msr (gld_msr_smi) msr address 4c002002h ty p e r / w reset value 00000000_0000001fh gld_msr_smi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd smi_ext smi_pml2 smi_pmcnt smi_dbg smi_err rsvd smi_ext_mask smi_pml2_mask smi_pmcnt_mask smi_dbg_mask smi_err_mask gld_msr_smi bit descriptions bit name description 63:21 rsvd reserved. 20 smi_ext smi from i/o companion. asmi generated when most recent serial packet had smi bit set. this bit always represents the state of the smi bit in the last serial packet received. it cannot be written. to clear external smi sources, proper external controls must be sent (i.e., via the pci bus). 19 smi_pml2 smi power management glcp_lvl2. ssmi generated when glcp_lvl2 (msr 4c000019h) i/o register was read. write 1 to clear, 0 has no effect. 18 smi_pmcnt smi power management glcp_cnt mask. ssmi generated when glcp_cnt (msr 4c000018h) i/o register was written. write 1 to clear, 0 has no effect. 17 smi_dbg smi debug. asmi generated due to debug event or procstat access. write 1 to clear, 0 has no effect. 16 smi_err smi error. asmi generated due to error signal. write 1 to clear, 0 has no effect. 15:5 rsvd reserved. 4 smi_ext_mask smi from i/o companion mask. if clear, enables serial packets from external device to generate an asmi. 3 smi_pml2_mask smi power management glcp_lvl2 mask. if clear, enables power management logic to generate an ssmi when glcp_lvl2 i/o register (msr 4c000019h) is read. 2 smi_pmcnt_mask smi power management glcp_cnt mask. if clear, enables power management logic to generate an ssmi when glcp_cnt (msr 4c000018h) i/o register is writ- ten. 1 smi_dbg_mask smi debug mask. if clear, enables debug logic to generate an asmi. 0 smi_err_mask smi error mask. if clear, then any gliu device error signal (including glcp) causes an asmi.
amd geode? lx processors data book 543 geodelink? control processor register descriptions 33234h 6.14.1.4 gld error msr (gld_msr_error) msr address 4c002003h ty p e r / w reset value 00000000_00000000h gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd err_syspll err_dotpll err_size err_type 313029282726252423222120191817161514131211109876543210 rsvd err_syspll_mask err_dotpll_mask err_size_mask err_type_mask gld_msr_error bit descriptions bit name description 63:36 rsvd reserved. 35 err_syspll error system pll. system pll lock signal was active when por was inactive. writing 1 clears error; 0 leaves unchanged. 34 err_dotpll error dot clock pll. dot clock pll lock signal was active when por was inac- tive. writing 1 clears error; 0 leaves unchanged. 33 err_size error size. the gliu interface detected a read or write of more than 1 data packet (size = 16 bytes or 32 bytes). if a response packet is expected, the excep- tion bit will be set, in all cases the asynchronous error signal will be set. writing 1 clears error; 0 leaves unchanged. 32 err_type error type. an unexpected type was sent to the glcp gliu interface (start request with bex type, snoop, peek_write, debug_req, or null type). if a response packet is expected, the exception bit will be set, in all cases the asyn- chronous error signal will be set. writing a 1 clears the error, writing a 0 leaves unchanged. 31:4 rsvd reserved. 3 err_syspll_mask error system pll mask. when set to 1, disables error signaling based on the state of the err_sysp ll flag (bit 35). 2 err_dotpll_mask error dot clock pll mask. when set to 1, disables error signaling based on the state of the err_dotpll flag (bit 34). 1 err_size_mask error size mask. when set to 1, disables error signaling based on the state of the err_size flag (bit 33). 0 err_type_mask error type mask. wh.en set to 1, disables error signaling based on the state of the err_type flag (bit 32).
544 amd geode? lx processors data book geodelink? control processor register descriptions 33234h 6.14.1.5 gld power management msr (gld_msr_pm) the debug logic powers up selecting gliu1 for its cloc k. debug clock select is in glcp_dbgclkctl (msr 4c000016h[2:0]). 6.14.1.6 gld diagnostic msr (gld_msr_diag) this register is reserved for internal use by amd and should not be written to. msr address 4c002004h ty p e r / w reset value 00000000_00000015h gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pm_pci pm_dbg pm_gliu gld_msr_pm bit descriptions bit name description 63:32 rsvd reserved. write as read. 31:6 rsvd reserved. write as 0. 5:4 pm_pci glcp pci clock power mode. 00: clock always on. 01: hardware clock gating (gio interface will wake instantly when susp goes low). 1x: reserved. 3:2 pm_dbg glcp debug clock power mode. 00: clock always on. 01: hardware clock gating if debug inactive (if glcp_dbgclkctl = 0). 1x: reserved. 1:0 pm_gliu glcp gliu clock power mode . 00: clock always on. 01: hardware clock gating if glcp inactive. 1x: reserved. msr address 4c002005h ty p e r / w reset value 00000000_00000000h
amd geode? lx processors data book 545 geodelink? control processor register descriptions 33234h 6.14.2 glcp specific msrs - glcp control msrs 6.14.2.1 glcp clock disable dela y value (glcp_clk_dis_delay) 6.14.2.2 glcp clock mask for sl eep request (glcp_pmclkdisable) msr address 4c000008h ty p e r / w reset value 00000000_00000000h glcp_clk_dis_delay register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd clk_delay glcp_clk_dis_delay bit descriptions bit name description 63:24 rsvd reserved. write as read. 23:0 clk_delay clock disable delay. if enabled in glcp_glb_pm (clk_dly_en bit, msr 4c00000bh[4] = 1), indicates the period to wait from sleep_req before gating off clocks specified in glcp_pmclkdisable (msr 4c000009h). if this delay is enabled, it overrides or disables the function of glcp_clk4ack (msr 4c000013h). if the clk_dly_en bit is not set, but this register is non-zero, then this register serves as a timeout for the clk4ack behavior. msr address 4c000009h ty p e r / w reset value 00000000_00000000h glcp_pmclkdisable register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd vipvip vipgliu 313029282726252423222120191817161514131211109876543210 aes aesgliu aesee glcpdbg glcpgliu glcppci vpvop vpdot_2 vpdot_1 vpdot_0 vpgliu_1 vpgliu_0 pcipcif pcipci pcigliu gliu1_1 gliu1_0 dcgliu_1 dcgliu_0 rsvd dcdot_0 gliu0_1 gliu0_0 gp glmc dram bc_gliu bc_va mss ipipe fpufast fpuslow glcp_pmclkdisable bit descriptions bit name description 63:34 rsvd reserved. 33 vipvip vip vipclk off. when set, disables vip vipclk. 32 vipgliu vip gliu clock off. when set, disables vip gliu clock. 31 aes aes core functional clock off. when set, disables aes encryption/decryption clock. 30 aesgliu aes gliu clock off. when set, disables aes gliu interface clock. 29 aesee aes eeprom clock off. when set, disables aes eeprom clock.
546 amd geode? lx processors data book geodelink? control processor register descriptions 33234h 28 glcpdbg glcp debug clock off. when set, disables glcp dbg logic clock. 27 glcpgliu glcp gliu clock off. when set, disables glcp gliu clock. 26 glcppci glcp gio pci clock off. when set, disables glcp?s gio pci clock. 25 vpvop vp vop clock off. when set, disables vop logic clock. 24 vpdot_2 vp dot clock 2 off. when set, disables vp dot clock 2 (vp_vid). 23 vpdot_1 vp dot clock 1 off. when set, disables vp dot clock 1 (lcd_pix). 22 vpdot_0 vp dot clock 0 off. when set, disables vp dot clock 0 (vp_pix). 21 vpgliu_1 vp gliu clock 1 off. when set, disables vp gliu clock 1 (lcd). 20 vpgliu_0 vp gliu clock 0 off. when set, disables vp gliu clock 0 (vp). 19 pcipcif fast pci clock off. when set, disables fast pci clock inside glpci block. 18 pcipci pci clock off. when set, disables normal pci clock inside glpci block. 17 pcigliu glpci clock off. when set, disables clock entering glpci block. 16 gliu1_1 gliu1 clock off. when set, disables main clock to secondary gliu. 15 gliu1_0 gliu1 timer logic clock off. when set, disables clock to timer logic of secondary gliu. 14 dcgliu_1 dc gliu clock 1 off. when set, disables dc gliu clock 1 (vga). 13 dcgliu_0 dc gliu clock 0 off. when set, disables dc gliu clock 0 (dc). 12 rsvd reserved. unused bit, reads what was written, value written has no effect. 11 dcdot_0 dc dot clock off. when set, disables dc dot clock 0 (dc). 10 gliu0_1 gliu0 clock off. when set, disables main clock to primary gliu. 9gliu0_0 gliu0 timer logic clock off. when set, disables clock to timer logic of primary gliu. 8gp gp clock off. when set, disables gp clock (gliu). 7glmc glmc clock off. when set, disables gliu clock to glmc. 6 dram dram clocks off. when set, disables external dram clocks (and, hence, feedback clocks). 5 bc_gliu bus controller clock off. when set, disables clock to cpu bus controller block. 4bc_va cpu to bus controller clock off. when set, disables cpu clock to bus controller block. 3mss cpu to mss clock off. when set, disables cpu clock to memory subsystem block. 2 ipipe cpu to ipipe clock off. when set, disable cpu clock to ipipe block. 1 fpufast fpu fast clock off. when set, disables the fast fpu clock. 0 fpuslow fpu clock off. when set, disables the slow cpu clock to fpu. glcp_pmclkdisable bit de scriptions (continued) bit name description
amd geode? lx processors data book 547 geodelink? control processor register descriptions 33234h 6.14.2.3 chip fabrication information (glcp_fab) this read only register is used to track various fab, process, and product family parameters. it is meant for amd internal use only. reads return reset value. 6.14.2.4 glcp global power manage ment controls (glcp_glb_pm) msr address 4c00000ah ty p e r o reset value 00000000_00000001h msr address 4c00000bh ty p e r / w reset value 00000000_00000000h glcp_glb_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dotpll_en syspll_en rsvd out_vp out_gio out_glmc out_pci out_other rsvd clk_dly_en clk_dis_en rsvd rsvd tht_en glcp_glb_pm bit descriptions bit name description 63:18 rsvd reserved. 17 dotpll_en dotpll enable. enables turning off the dot clock pll during sleep when high. 16 syspll_en syspll enable. enables turning off the system plls during sleep when high. 15:13 rsvd reserved. 12 out_vp vp outputs. when set, enables vp outputs to tri_state during a sleep sequence. 11 out_gio gio outputs. when set, enables amd geode? i/o companion (gio) to tri_state device outputs during a sleep sequence. 10 out_glmc glmc outputs. when set, enables glmc to tri_state outputs during a sleep sequence. 9out_pci glpci outputs. when set, enables glpci to tri_state outputs during a sleep sequence. 8out_other other outputs. when set, enables tdbgo and suspa# to tri_state during a sleep sequence. 7:5 rsvd reserved. 4 clk_dly_en clock delay enable. enables gating off clock enables from a delay rather than glcp_clk4ack (msr 4c000013h) when high. 3 clk_dis_en clock display enable. enables the assertion of internal signal, mb_clk_dis_req, during a sleep sequence when high. 2:1 rsvd reserved. 0tht_en throttle enable. enables processor throttling functions. if this bit is low, all the functions related to throttling are disabled (glcp_th_od, glcp_cnt, etc.).
548 amd geode? lx processors data book geodelink? control processor register descriptions 33234h 6.14.2.5 glcp debug output from chip (glcp_dbgout) this register is reserved for internal use by amd and should not be written to. 6.14.2.6 glcp processor status (glcp_procstat) note that the names of these bits have the read stat us data before the "_" and the write behavior after it. msr address 4c00000ch ty p e r / w reset value 00000000 00000000h msr address 4c00000dh ty p e r / w reset value bootstrap dependant glcp_procstat register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd reset_none stopclk_none glact_unstall glcpstall_dmi stall_smi susp_stopclk dmi_stall glcp_procstat bit descriptions bit name description 63:7 rsvd reserved. writing these bits has no effect. 6 reset_none reset status. when read, this bit is high if a hard or soft reset to the amd geode? lx processor has occurred since this register was last read. writing this bit has no effect. 5 stopclk_ none stop clock status. when read, this bit is high if a glcp stop clock action has occurred since this register was last read. writing this bit has no effect. 4 glact_unstall gliu1 debug action status. when read, this bit is high if the glcp has triggered a gliu1 debug action since this register was last read. writing this bit high unstalls the processor. 3 glcpstall_ dmi glcp stall status. when read, this bit is high if the glcp is stalling the cpu. writing this bit high causes a glcp dmi to the processor. 2 stall_ smi cpu stall status. when read, this bit is high if the cpu is stalled for any reason. writing this bit high causes a glcp smi to the processor. bit 1 of gld_msr_smi (msr 4c000002h) gets set by this smi and an smi is triggered, assuming appro- priate smi enable settings. 1 susp_ stopclk cpu suspended stop clock status. when read, this bit is high if the cpu has suspended execution for any reason since th is register was last read. writing this bit high causes the glcp to stop all clocks iden tified in glcp_clkdisable (msr 4c000012h). 0dmi_stall cpu dmi stall status. when read, this bit is high if the cpu is in dmi mode. writ- ing this bit high causes the glcp to ?debug_stall? the processor.
amd geode? lx processors data book 549 geodelink? control processor register descriptions 33234h 6.14.2.7 glcp dowser (glcp_dowser) 6.14.2.8 glcp i/o delay controls (glcp_delay_controls) msr address 4c00000eh ty p e r / w reset value 00000000_00000000h glcp_dowser register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 sw defined 313029282726252423222120191817161514131211109876543210 sw defined glcp_dowser bit descriptions bit name description 63:0 --- software defined. this 64-bit scratchpad register was specifically added for sw debugger use (dowser). the register resets to zero with both hard and soft resets. msr address 4c00000fh ty p e r / w reset value 00000000_00000000h glcp_delay_controls register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 en b_dq b_cmd b_ma sdclk_set ddr_rle sdclk_dis tla1_oa d_tla1 d_tla0 d_dq_e d_dq_o rsvd d_sdclk d_cmd_o d_cmd_e d_ma_o d_ma_e 313029282726252423222120191817161514131211109876543210 d_pci_o d_pci_e d_dotclk d_drgb_o d_drgb_e d_pci_in d_tdbgi d_vip d_vipclk h_sdclk pll_fd_del rsvd dll_ov dll_ovs/rsda glcp_delay_controls bit definition bit name description 63 en 0: use default values. 1: use value in bits [62:0]. 62 b_dq buffer control for dq [63:0], dqs[7:0], dqm[7:0] , tla[1:0] drive select. 1: half power. 0: quarter power. 61 b_cmd buffer control for ras[1: 0]#, cas[1:0]#, cke[ 1:0], cs[3:0]#, we[1 :0]# drive select. 1: half power. 0: quarter power. 60 b_ma buffer control fo r ma[13:0] and ba[1:0]. 0: half power. 1: full power.
550 amd geode? lx processors data book geodelink? control processor register descriptions 33234h 59 sdclk_set sdclk setup. 0: full sdclk setup. 1: half sdclk setup for control signals. 58:56 ddr_rle ddr read latch enable position. 55 sdclk_dis sdclk disable [1,3,5]. 0: all sdclk output. 1: sdclk[4,2,0] output only. 54:52 tla1_oa tla hint pin output adjust. 51:50 d_tla1 output delay for tla1. 49:48 d_tla0 output delay for tla0. 47:46 d_dq_e output delay for dq, dqm - even byte lanes. 45:44 d_dq_o output delay for dq, dqm - odd byte lanes. 43:42 rsvd reserved. 41:40 d_sdclk output delay for sdclk. 39:38 d_cmd_o output delay for cke, cs, ras, cas, we - odd bits. 37:36 d_cms_e output delay for cke, cs, ras, cas, we - even bits. 35:34 d_ma_o output delay for ba and ma - odd bits. 33:32 d_ma_e output delay for ba and ma - even bits. 31:30 d_pci_o output delay for pci_ad, irq13, suspa#, inta# - odd bits. 29:28 d_pci_e output delay for pci_ad, cbe#, pa r, stop#, frame#, irdy#, trdy#, devsel#, req#, gnt# - even bits. 27:26 d_dotclk output delay for dotclk. 25:24 d_drbg_o output delay for drgb[31:0] - odd bits. 23:22 d_drgb_e outp ut delay for drgb[31:0], hsync, vsyn c, dispen, vdden, lde_mod - even bits. 21:20 d_pci_in input delay for ad[31:0], cbe#, pa r, stop#, frame#, irdy#, trdy#, devsel#, req#, gnt#, cis. 19:18 d_tdbgi input delay for tdbgi. 17:16 d_vip input delay for vid[15:0], vip_hsync, vip_vsync. 15:14 d_vipclk input delay for vipclk. 13 h_sdclk half sdclk hold select (for cmd addr). 1: half sdclk setup for ma and ba signals. 0: full sdclk setup. 12:11 pll_fd_del pll feedback delay. 00: no feedback delay. 11: max feedback delay. (01: ~350 ps, 10: ~700 ps, 11: ~1100 ps). 10:6 rsvd reserved. 5 dll_ov dll override (to dll). 4:0 dll_ovs/rsda dll override setting or read strobe delay adjust. when dll override is 1 this is the dqs overide delay. when dll override is 0 this is the offset adjust value. glcp_delay_controls bi t definition (continued) bit name description
amd geode? lx processors data book 551 geodelink? control processor register descriptions 33234h 6.14.2.9 glcp clock control (glcp_clkoff) this register has bits that, when set, force clocks off usin g geodelink? clock control (glcc) logic in the system. this is for debugging only, and should not be used for power management. msr address 4c000010h ty p e r / w reset value 00000000_00000000h glcp_clkoff register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd vipvip vipgliu 313029282726252423222120191817161514131211109876543210 aes aesgliu aesee glcpdbg glcpgliu glcppci vpvop vpdot_2 vpdot_1 vpdot_0 vpgliu_1 vpgliu_0 pcipcif pcipci pcigliu gliu1_1 gliu1_0 dcgliu_1 dcgliu_0 rsvd dcdot_0 gliu0_1 gliu0_0 gp glmc dram bc_glius bc_va mss ipipe fpufast fpuslow glcp_clkoff bit descriptions bit name description 63:34 rsvd reserved. 33 vipvip vip vipclk off. when set, disables vip vipclk. 32 vipgliu vip gliu clock off. when set, disables vip gliu clock. 31 aes aes core functional clock off. when set, disables aes encryption/decryption clock. 30 aesgliu aes gliu clock off. when set, disables aes gliu interface clock. 29 aesee aes eeprom clock off. when set, disables aes eeprom clock. 28 glcpdbg glcp debug clock off. when set, disables glcp dbg logic clock. 27 glcpgliu glcp gliu clock off. when set, disables glcp gliu clock. 26 glcppci glcp gio pci clock off. when set, disables glcp?s gio pci clock. 25 vpvop vp vop clock off. when set, disables vop logic clock. 24 vpdot_2 vp dot clock 2 off. when set, disables vp dot clock 2 (vp_vid). 23 vpdot_1 vp dot clock 1 off. when set, disables vp dot clock 1 (lcd_pix). 22 vpdot_0 vp dot clock 0 off. when set, disables vp dot clock 0 (vp_pix). 21 vpgliu_1 vp gliu clock 1 off. when set, disables vp gliu clock 1 (lcd). 20 vpgliu_0 vp gliu clock 0 off. when set, disables vp gliu clock 0 (vp). 19 pcipcif fast pci clock off. when set, disables fast pci clock inside glpci block. 18 pcipci pci clock off. when set, disables normal pci clock inside glpci block. 17 pcigliu glpci clock off. when set, disables clock entering glpci block. 16 gliu1_1 gliu1 clock off. when set, disables main clock to secondary gliu. 15 gliu1_0 gliu1 timer logic clock off. when set, disables clock to timer logic of secondary gliu. 14 dcgliu_1 dc gliu clock 1 off. when set, disables dc gliu clock 1 (vga). 13 dcgliu_0 dc gliu clock 0 off. when set, disables dc gliu clock 0 (dc). 12 rsvd reserved. unused bit, reads what was written, value written has no effect.
552 amd geode? lx processors data book geodelink? control processor register descriptions 33234h 6.14.2.10 glcp clock ac tive (glcp_clkactive) see "glcp_clkoff bit descriptions" on page 551 for bit descriptions. 11 dcdot_0 dc dot clock off. when set, disables dc dot clock 0 (dc). 10 gliu0_1 gliu0clock off. when set, disables main clock to primary gliu. 9gliu0_0 gliu0 timer logic clock off. when set, disables clock to timer logic of primary gliu. 8gp gp clock off. when set, disables gp clock (gliu). 7glmc glmc clock off. when set, disables gliu clock to memory controller. 6 dram dram clocks off. when set, disables external dram clocks (and, hence, feedback clocks). 5 bc_gliu bus controller clock off. when set, disables clock to cpu bus controller block. 4bc_va cpu to bus controller clock off. when set, disables cpu clock to bus controller block. 3mss cpu to mss clock off. when set, disables cpu clock to mss block. 2 ipipe cpu to ipipe clock off. when set, disable cpu clock to ipipe block. 1 fpufast fpu fast clock off. when set, disables the fast fpu clock. 0 fpuslow fpu clock off. when set, disables the slow cpu clock to fpu. msr address 4c000011h ty p e r o reset value input determined glcp_clkoff bit descriptions (continued) bit name description glcp_clkactive register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd vipvip vipgliu 313029282726252423222120191817161514131211109876543210 aes aesgliu aesee glcpdbg glcpgliu glcppci vpvop vpdot_2 vpdot_1 vpdot_0 vpgliu_1 vpgliu_0 pcipcif pcipci pcigliu gliu1_1 gliu1_0 dcgliu_1 dcgliu_0 rsvd dcdot_0 gliu0_1 gliu0_0 gp glmc dram bc_gliu bc_va mss ipipe fpufast fpuslow
amd geode? lx processors data book 553 geodelink? control processor register descriptions 33234h 6.14.2.11 glcp clock mask for debug clock stop action (glcp_clkdisable) see "glcp_clkoff bit descriptions" on page 551 for bit descriptions. 6.14.2.12 glcp clock active mask for suspend acknowledge (glcp_clk4ack) see "glcp_clkoff bit descriptions" on page 551 for bit descriptions. msr address 4c000012h ty p e r / w reset value 00000000_00000000h glcp_clkdisable register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd vipvip vipgliu 313029282726252423222120191817161514131211109876543210 aes aesgliu aesee glcpdbg glcpgliu glcppci vpvop vpdot_2 vpdot_1 vpdot_0 vpgliu_1 vpgliu_0 pcipcif pcipci pcigliu gliu1_1 gliu1_0 dcgliu_1 dcgliu_0 rsvd dcdot_0 gliu0_1 gliu0_0 gp glmc dram bc_gliu bc_va mss ipipe fpufast fpuslow msr address 4c000013h ty p e r / w reset value 00000000_00000000h glcp_clk4ack register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd vipvip vipgliu 313029282726252423222120191817161514131211109876543210 aes aesgliu aesee glcpdbg glcpgliu glcppci vpvop vpdot_2 vpdot_1 vpdot_0 vpgliu_1 vpgliu_0 pcipcif pcipci pcigliu gliu1_1 gliu1_0 dcgliu_1 dcgliu_0 rsvd dcdot_0 gliu0_1 gliu0_0 gp glmc dram bc_gliu bc_va mss ipipe fpufast fpuslow
554 amd geode? lx processors data book geodelink? control processor register descriptions 33234h 6.14.2.13 glcp system reset an d pll control (glcp_sys_rstpll) this register is initialized during por, bu t otherwise is not itself reset by any ?sof t-reset? features. note that writing this reg- ister always has immediate effect, so read-modify-writes mu st be done to avoid corrupting the pll timing settings. when using this register functionally to change pll frequencies, th e chip_reset bit (bit 0) should be set. writing this register with the chip_reset bit set will never send a write-response over the gliu (this allows halting bus traffic before the reset occurs). msr address 4c000014h ty p e r / w reset value bootstrap specific glcp_sys_rstpll register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd gliumult mbdiv coremult corediv 313029282726252423222120191817161514131211109876543210 swflags gliulock corelock hold_count rsvd gliupd corepd gliubypass corebypass lpfen va_semi_sync_mode pci_semi_sync_mode bootstraps chip_reset glcp_sys_rstpll bit descriptions bit name description 63:44 rsvd reserved. 43:39 gliumult gliu multiplier (bootstrap dependent, see table 6-87). 00000: multiply by 1,.... 11111: multiply by 32. 38 gliudiv gliu divide. when set, predivide the gliu pll input frequency by 2. 0: do not predivide input. (default) 1: divide by 2. 37:33 coremult cpu core multiplier (boo tstrap dependent, see table 6-87 on page 556). 00000: multiply by 1,.... 11111: multiply by 32. 32 corediv cpu core divide. when set, predivide the gliu pll input frequency by 2. 0: do not predivide input. (default) 1: divide by 2. 31:26 swflags flags. flags that are rese t only by the por# signal, no t the chip_reset (bit 0). they are reset to 0 and can be us ed as flags in the boot code that survive chip_reset. 25 gliulock (ro) lock (read only). lock signal from the system pll. the worst-case lock time for a amd geode? lx processor pll is 100 s. 24 corelock (ro) lock (read only). lock signal from the system pll. the worst-case lock time for a amd geode lx processor pll is 100 s.
amd geode? lx processors data book 555 geodelink? control processor register descriptions 33234h 23:16 hold_count hold count. the number of pll reference clock cycl es (divided by 16 ) that the pll is powered down for, and also the nu mber before releasing chip_reset. 0: wait 0 cycles. (default) 1: wait 16 clock cycles, etc. 15 rsvd reserved. always write 0. 14 gliupd gliu power down. this signal controls the power do wn mode of the gliu pll. it is active high. this bit is always cleared by a chip_reset (bit 0). 13 corepd core power down. this signal controls the power do wn mode of the cpu core pll. it is active high. this bit is always cleared by a chip_reset (bit 0). 12 gliubypass gliu bypass. this signal controls the bypass mode of the gliu clocking. if this bit is high, the dotpll is configured for bypass and the dotref input clock directly drives the gliu clock spines. (for sysref bypass through the gliu pll, the clksel jtag register must be used). 11 corebypass core bypass. this signal controls the bypass mode of the core clock. if this bit is high, the dotpll is configured for bypass and the dotreff input clock directly drives the core clock. (for sysref bypass through t he core pll, the clksel jtag register must be used). 10 lpfen loop filter enable . this bit is tied to both the gliu and core pll loop filter enables. this pll control enables the use of an external resistor. it should be clear for normal operation. 9 va_semi_ sync_mode cpu sync mode. this bit controls whether the cpu uses a fifo for interfacing with the gliu. if the bit is high, the cpu will not use t he fifo. it behaves as if the cpu and gliu domains are synchronous. this bit can be set high as long as the cpu and gliu fre- quencies are multiples of each othe r. the bit is always reset low. 8 pci_semi_ sync_mode pci sync mode. this bit controls whether the pci uses the falling edges of mb_func_clk and pci_func_clk for interfacing with gliu or not. if the bit is high, pci does not use fall- ing clock edges. it behaves as if the pci and gliu domains are synchronous. this bit can be set high as long as the pci and gliu frequencies are multiples of each other. the bit always resets low. 7:1 bootstraps (ro) bootstraps (read only). these bits are copies of th e state of bootstraps when power- on reset (pci reset) is released. bit 7: pw1 pad - active high when the pci clock is 66 mhz, low for 33 mhz. bit 6: irq13 pad - active high for stall-on-reset debug feature, otherwise low. bit 5: pw0 pad - part of cpu/gliu frequency selects. bit 4: suspa# pad - part of cpu/gliu frequency selects. bit 3: gnt2# pad - part of cpu/gliu frequency selects. bit 2: gnt1# pad - part of cpu/gliu frequency selects. bit 1: gnt0# pad - part of cpu/gliu frequency selects. 0 chip_reset chip reset. when written to a 1, the chip enters reset and does not come out until the hold_count (bits [23:16]) is reached. this register and the jtag logic are not reset by chip_reset, but otherwise the enti re chip is reset. (default = 0) glcp_sys_rstpll bit descriptions (continued) bit name description
556 amd geode? lx processors data book geodelink? control processor register descriptions 33234h the pw1 pin (66 mhz pci) is wired directly to the coredi v and gldiv signals during rese t. the irq13 pin (stall after reset) has no effect on the pll controls but is still st ored in the bootstrap bits (msr 4c000018h[7:1]). table 6-87 shows examples of reset values when pw1 and/or irq13 are hi gh during reset. the hard reset state of this register always leaves the pll in bypass mode. the bios must clear t he bypass bits in order to achieve the desired frequency. table 6-87. bootstrap bit sett ings and reset state of glcp _sys_rstpll (pw1 and irq13 = 0) {pw1,irq13,pw0,suspa#, gnt#[2:0]} same as glcp_sys_rstpll[7:1] cpu core speed (mhz) cpu core mult gliu speed (mhz) gliu mult glcp_sys_rstpll reset value 0000000 bypass 11 bypass 7 00000396_00001800h 0000001 166 4 166 4 00000208_03001802h 0000010 200 5 200 5 0000028a_03001804h 0000011 266 7 200 5 0000028e_03001806h 0000100 266 7 266 7 0000038e_03001808h 0000101 333 9 200 5 00000292_0300180ah 0000110 333 9 266 7 00000392_0300180ch 0000111 333 9 333 9 00000492_0300180eh 0001000 366 10 200 5 00000294_03001810h 0001001 366 10 266 7 00000394_03001812h 0001010 366 10 333 9 00000494_03001814h 0001011 400 11 200 5 00000296_03001816h 0001100 400 11 266 7 00000396_03001818h 0001101 400 11 333 9 00000496_0300181ah 0001110 400 11 400 11 00000596_0300181ch 0001111 433 12 266 7 00000398_0300181eh 0010000 433 12 333 9 00000498_03001820h 0010001 433 12 400 11 00000598_03001822h 0010010 466 13 266 7 0000039a_03001824h 0010011 466 13 333 9 0000049a_03001826h 0010100 466 13 400 11 0000059a_03001828h 0010101 500 14 266 7 0000039c_0300182ah 0010110 500 14 333 9 0000049c_0300182ch 0010111 500 14 400 11 0000059c_0300182eh 0011000 533 15 266 7 0000039e_03001830h 0011001 533 15 333 9 0000049e_03001832h 0011010 533 15 400 11 0000059e_030001834h 0011011 600 17 200 5 000002a2_03001836h 0011100 566 16 333 9 000004a0_03001838h 0011101 566 16 400 11 000005a0_0300183ah 0011110 600 17 333 9 000004a2_0300003ch 0011111 600 17 400 11 000005a2_0300183eh
amd geode? lx processors data book 557 geodelink? control processor register descriptions 33234h 6.14.2.14 glcp dot clock pll control (glcp_dotpll) this register does not include hardw are handshake controls like the glcp_sys_rstpll register (msr 4c000014h), so care should be taken when changing the settings. for example, to change the div settings: wr ite the register with the dot- reset bit (bit 0) set and either in the same write or anothe r write change the div settings; read the register until the lock bit (bit 25) goes active (or until a timeout occurs, if desired) ; write the register with the same div settings and with the do t- reset bit clear. the mdiv, ndiv, and pdiv (bits [46:32]) settings work in conjunction to create the internal dotclk using this equation: for example, with bits [46:32] in the glcp_dotpll register se t to 0x00d7 (reset), the dot clock frequency that the dc and vp would run with would be: however, not all mdiv, ndiv, and pdiv settings lock and not all that lock have good long-term jitter characteristics. the pll resets to 25.0565 mhz for vga monitors assuming a 14.31818 mh z input. a 27 mhz input will successfully lock at about 47 mhz, and should then be changed to the desired pixel rate. table 6-88. bootstrap bit setti ngs and reset state of glcp_sys_rstpll (pw1 and irq13 vary) {pw1,irq13,pw0,s uspa#,gnt#[2:0]} same as glcp_sys_rstpll[7:1] cpu speed core mult gliu speed gliu mult glcp_sys_rstpll reset value 0100000 bypass 11 bypass 7 00000396_00001840h 1000001 166 4 166 4 00000249_03000082h 1110111 500 14 400 11 000005dd_030000eeh msr address 4c000015h ty p e r / w reset value 000000d7_02000000h fout fin ndiv 1 + () mdiv 1 + () pdiv 1 + () ? ---------------- ------------------ ----------------- ------------ ? = fout 14.318mhz 13 1 + () 01 + () 71 + () ------------------- --------------- ? 25.0565 mhz == glcp_dotpll register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd div4 rsvd mdiv ndiv pdiv 313029282726252423222120191817161514131211109876543210 swflags lock halfpix rsvd bypass pd capen rsvd rsvd dotreset
558 amd geode? lx processors data book geodelink? control processor register descriptions 33234h glcp_dotpll bit descriptions bit name description 63:49 rsvd reserved. write as read. 48 div4 divide by 4. when set, the pll output is divided by 4 before clocking the logic. this bit is intended for generating frequencies below the pll spec limit of 15 mhz. 47 rsvd reserved. 46:44 mdiv input clock divisor. the dotpll m setting (resets to vga timing). 43:36 ndiv dot clock pll divisor. the dotpll n setting (resets to vga timing). 35:32 pdiv post scaler divisor. the dotpll p setting (resets to vga timing). 31:26 swflags software flags. unlike in the glcp_sys_rstpll register (msr 4c 000014h), these bits are reset to 0 by a soft reset to the chip. these bits are otherwise read/writable by software. they are not reset by a dotreset (bit 0 of this register). 25 lock (ro) lock (read only). lock signal from the dotclk pll. 24 halfpix half pixel. the dc and vp receive a half-frequency dot clock while the vop logic receives the normal frequency determined by the mdiv, ndiv, pdiv settings. this fea- ture enables 8-bit vop of sd data at 27 mhz vop clock (pixel rate only 13.5 mhz). 23:16 rsvd reserved. write as read. 15 bypass dot pll bypass. this signal controls the bypass mode of the dotclk pll. if this bit is high, the dotref input clock directly drives the raw dotclk, bypassing the mdiv, ndiv, and pdiv logic. 14 pd power down. this bit controls the power down mode of the dotclk pll. it is active high. 13 capen capacitor enable. the capen signal to th e dotpll enables an external capacitor for the loop filter. 0: an external capacitor is not used. internal circuitry is used to stabilize the loop opera- tion. 1: enables the use of an external capacitor for the loop filter. 12:10 rsvd reserved. 9:1 rsvd reserved. read/writable bits not currently used. 0 dotreset dot clock reset. the reset pin to the dot clock time blocks. the dot reset is held active when chip_reset (msr 4c000014h[0]) is high, but this bit resets to 0. it is recom- mended that software set this bit when changing pll settings and observe lock before releasing this reset. unlike the sys_rstpll regi ster, this bit is not required to be set before the other bits in this register affect the pll.
amd geode? lx processors data book 559 geodelink? control processor register descriptions 33234h 6.14.2.15 glcp debug clock control (glcp_dbgclkctl) note that after the mux to select the clock, a standard cloc k control gate exists. this regi ster should never be changed from one non-zero value to another. always write this register to 0 when moving to an alternative debug clock. 6.14.2.16 chip revision id (glcp_chip_revid) msr address 4c000016h ty p e r / w reset value 00000000_00000002h glcp_dbgclkctl register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd clksel glcp_dbgclkctl bit descriptions bit name description 63:3 rsvd reserved. write as read. 2:0 clksel clock select. selects the clock to drive into the debug logic. 000: none. 001: cpu core clock. 010: gliu1 clock. 011: dotclk. 100: pci clock. 101-111: reserved. msr address 4c000017h ty p e r o reset value 00000000_000000xxh glcp_chip_revid register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd maj min glcp_chip_revid bit descriptions bit name description 63:8 rsvd reserved. reads as 0. 7:4 maj major revision. identifies major silicon revision. see amd geode? lx processors specification update document for value. 3:0 min minor revision . identifies minor silicon revision. see amd geode? lx processors specification update document for value.
560 amd geode? lx processors data book geodelink? control processor register descriptions 33234h 6.14.2.17 glcp control (glcp_cnt) this register is used in conjunction wit h gliu1 power management. i/o writes, which include the lowest byte of this regis- ter, may trigger an smi if gld_msr_smi (msr 4c002002h) is configured appropriately. msr writes do not cause smis. the throttle sequence starts after the delay specified by glcp_th_sd (msr 4c00001ch), which can allow for smi han- dling time or any other pre parations. throttling is tempor arily stopped in irq, ssmi, asmi, or dmi. nmi and system sleep (c2) always clear tht_en (bit 4). 6.14.2.18 glcp level 2 (glcp_lvl2) this register has no writable bits. i/o reads to the lower byte of this register (with or without reading the other three bytes ) return 0 and cause the system to enter ?c 2 processor state? as defined by the gl iu1 power management spec; that is, sus- pend the processor. i/o reads to the lower byte of this register may trigger an smi if gld_msr_smi (msr 4c002002h) is configured appropriately. note that the suspend starts af ter a delay specified by glcp_th_sd (msr 4c00001ch), which can allow for smi handling or any other preparations. p_ lvl2_in (msr 4c00001ch[12]) can abort the suspend operation. msr reads to this register return 0, but perform no further action. msr address 4c000018h type r/w - i/o offset 00h reset value 00000000_000000fh glcp_cnt register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd tht_en clk_val glcp_cnt bit descriptions bit name description 63:5 rsvd reserved. write as read. 4tht_en throttle enable. when high, enables throttling of processor for power management. this bit is always cleared by an nmi to the processor or when system sleep initiates, it may clear from an smi or irq depending on glcp_th_od (msr 4c00001eh) settings. 3:0 clk_val clock throttling value. the value 0000 is reserved and should not be used. the value 0001 yields the most throttling while the value 11 11 has the effect of no throttling (1111 is the reset value). reads return value written. tht_en (bit 4) must be low to change the value of clk_val. see also glcp_th_sf (msr 4c00001dh). during processor throt- tling, processor suspend is applied the amou nt of time of ?(15-clk_val)*glcp_th_sf? and then removed the amount of time of ?clk_val*glcp_th_sf?. msr address 4c000019h type r/w - i/o offset 04h reset value 00000000_00000000h
amd geode? lx processors data book 561 geodelink? control processor register descriptions 33234h 6.14.2.19 glcp thro ttle or c2 start delay (glcp_th_sd) 6.14.2.20 glcp scale factor (glcp_th_sf) msr address 4c00001ch type r/w - i/o offset 10h reset value 00000000_00000000h glcp_th_sd register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd p_lvl2_in tht_delay glcp_th_sd bit descriptions bit name description 63:13 rsvd reserved. by convention, always write zero. 12 p_lvl2_in enable indicator. if p_lvl2 (in msr 4c000019h) was read, then this bit reads high. if this bit is written to a one, the suspend is aborted. this bit is always cleared and suspend de-asserted on nmi, irq, ssmi, asmi, dmi, or system sleep. 11:0 tht_delay throttle delay. indicates how long to wait before beginning the processor throttling pro- cess as defined by msr 4c000018h. the delay setting is multiplied by 16 to get the number of pci clock cycles to wait, thus se tting tht_delay = 3 causes a wait of 48 pci clock cycles. msr address 4c00001dh type r/w - i/o offset 14h reset value 00000000_00000000h glcp_th_sf register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd scale glcp_th_sf bit descriptions bit name description 63:8 rsvd reserved. by convention, always write 0. 7:0 scale scale factor. this value is used in conjunction with clk_val in the glcp_cnt msr (4c000018h[3:0]). this value times clk_val (or 15-clk_val) indicates the number of pci clock cycles to wait during processor acti ve (or suspend) periods . the setting is mul- tiplied by 16 to get the number of pci cl ock cycles per period, thus scale = 3 and clk_val = 5 will have the processor active for 240 pci clocks and suspended for 480 pci clocks.
562 amd geode? lx processors data book geodelink? control processor register descriptions 33234h 6.14.2.21 glcp proc essor throttle off delay (glcp_th_od) 6.14.3 glcp ignne i/os the glcp?s gliu is responsible for all the gliu functionalit y. the glcp?s gliu implements a large msr space consisting of the required standard gliu device msrs, msr controls for clock and pll interfacing, the msr controls for the i/o com- panion modes and mvpi signals, and msr controls for the debu g logic. the glcp?s gliu must properly decode all possi- ble gliu transaction types including the unexpected addresses, request types and sizes. it must respond with the proper number of response packets. in addition, it provides error logic to detect unexpected addresses and types. the glcp?s gliu also implements the proc essor floating point exception handling logic. always @(va_ferr or irq13 or write_to_f0f1 or ignee) if (!va_ferr) nxt_ignne = 0; else if (irq13 && write_to_f0f1) nxt_ignne = 1; else nxt_ignne = ignne; always @(posege ck) ignee <= nxt_ignne; irq13 <= va_ferr & !nxt_ignne; the glcp?s gliu maintains msrs that co ntrol the source and value of the companion device syst em outputs. it also con- trols the current companion device mode. read data returns gld_msr_cap data. msr address 4c00001eh type r/w - i/o offset 18h reset value 00000000_00000000h glcp_th_od register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd irq_en smi_en off_delay glcp_th_od bit descriptions bit name description 63:16 rsvd reserved. by convention, always write 0. 15 irq_en enable throttling restart after irq. if this bit is set and throttling is not disabled during the irq handling, throttling restarts afte r the period specified by off_delay (bits [13:0]). if this bit is clear, then an irq clears tht_en (msr 4c000018h[4]). 14 smi_en enable throttling restart after smi. if this bit is set and thro ttling is not disabled during the smi handling, throttling restarts afte r the period specified by off_delay (bits [13:0])if this bit is clear, then an asmi clears tht_en (msr 4c000018h[4]). 13:0 off_delay throttle off delay. indicates the period to wait from receipt of irq_en (bit 15) or smi_en (bit 14) before restarting throttle operat ion. this setting is multiplied by 16 to get the number of pci clock cycles to wait. if the off_delay has not expired and another irq or smi occurs, the off_delay timer is cleared again and the wait begins again. setting off_delay to 0 result s in only one pci clock cycle of throttling being disabled after an irq or smi. glcp i/o offset f0h, f1h ty p e w reset value na
amd geode? lx processors data book 563 geodelink? control processor register descriptions 33234h 6.14.4 glcp specific msrs - glcp debug interface msrs 6.14.4.1 glcp dac (glcp_dac) this register has dac diagnostic controls and status. it ties directly to inputs and outputs on the dac module. bits [13:11] of this register are only valid after the dac is enabled. msr address 4c000023h ty p e r / w reset value 00000000_00000000h glcp_dac register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd sb sg sr inrefen ol ab ag ar glcp_dac bit descriptions bit name description 64:14 rsvd reserved. 13 sb (ro) status blue (read only). a logic level 1 means the blue dac output is above 0.35v. 12 sg (ro) status green (read only). a logic level 1 means the green dac output is above 0.35v. 11 sr (ro) status red (read only). a logic level 1 means the red dac output is above 0.35v. 10 inrefen internal reference enable. internal reference enable to the dac. 9ol output level. 0: rgb. 1: tv - for testing only, analog tv out is not supported). 8:6 ab adjust for blue dac. 000: 0%. 011: 7.5%. 100: -10%. 111: -2.5%. 5:3 ag adjust for green dac. 000: 0%. 011: 7.5%. 100: -10%. 111: -2.5%. 2:0 ar adjust for red dac. 000: 0%. 011: 7.5%. 100: -10%. 111: -2.5%.
564 amd geode? lx processors data book geodelink? control processor register descriptions 33234h 6.14.5 glcp specific msrs - glcp companion device interface msrs 6.14.5.1 cpu a20m signal (msr_a20m) 6.14.5.2 cpu init signal (msr_init) msr address 4c000031h ty p e r / w reset value 00000000_00000000h msr_a20m register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd msr_a20m msr_a20m bit descriptions bit name description 63:1 rsvd reserved. 0 msr_a20m a20m. value of a20m driven to cpu logic. msr address 4c000033h ty p e r / w reset value 00000000_00000000h msr_init register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd msr_init msr_init bit descriptions bit name description 63:1 rsvd reserved. 0msr_init msr_init. value of init signal driven to cpu.
amd geode? lx processors data book 565 geodelink? control processor register descriptions 33234h 6.14.5.3 gliu device inte rrupt status (msr_intax) this is a read only msr with the status of interrupt signals fr om the various blocks. this register is intended for debug pur- poses. for functional interrupt handlers, t he block-specific interrupt registers are memory-mapped. for devices that do not support interrupts, the associated bit is 0. msr address 4c000036h ty p e r o reset value 00000000_00000000h msr_intax register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd gliu1_int6 gliu1_int5 gliu1_int4 gliu1_int3 gliu1_int2 gliu1_int1 gliu1_int0 rsvd rsvd gliu0_int5 gliu0_int4 gliu0_int3 gliu0_int2 gliu0_int1 gliu0_int0 msr_intax bit descriptions bit name description 63:15 rsvd reserved. 14 gliu1_int6 value of intr signal from gliu 1, port 6 (security block (aes)). 13 gliu1_int5 value of intr signal from gliu1, port 5 (vip). 12 gliu1_int4 value of intr signal from gliu1, port 4 (glpci). 11 gliu1_int3 value of intr signal from gliu1, port 3 (glcp). 10 gliu1_int2 value of intr signal from gliu1, port 2 (vp). 9 gliu1_int1 value of intr signal from gliu1, port 1 (gliu). 8 gliu1_int0 value of intr signal from gliu1, port 0 (gliu). 7 rsvd reserved. 6 rsvd reserved. 5 gliu0_int5 value of intr signal from gliu0, port 5 (gp). 4 gliu0_int4 value of intr signal from gliu0, port 4 (dc). 3 gliu0_int3 value of intr signal fr om gliu0, port 3 (cpu). 2 gliu0_int2 value of intr signal from gliu0, port 2 (gliu) 1 gliu0_int1 value of intr signal from gliu0, port 1 (glmc). 0 gliu0_int0 value of intr signal from gliu0, port 0 (gliu).
566 amd geode? lx processors data book geodelink? pci bridge 33234h 6.15 geodelink? pci bridge the geodelink? pci bridge (glpci) module provides a pci interface for geodelink interface unit-based designs. the glpci module is composed of five major blocks: ? geodelink interface ? fifo/synchronization ? transaction forwarding ? pci bus interface ? pci arbiter the geodelink and pci bus interface blocks provide adaptation to the respective buses. the transaction for- warding block provides bridging logic. features ? pci version 2.2 compliance ? 32-bit, 66 mhz pci bus operation ? target support for fast back-to-back transactions ? arbiter support for three external pci bus masters ? write gathering and write posting for in-bound write requests ? virtual pci header support ? delayed transactions for in-bound read requests ? zero wait state operation within a pci burst ? dynamic clock stop/start support for gliu and pci clock domains (this is not clkrun support) ? capable of handling out of bound transactions immedi- ately after reset figure 6-58. glpci block diagram pci bus interface pci bus request request data pci arbiter req#/gnt# msr transaction forwarding fifos/synchronization geodelink? interface geodelink? interface unit 1 (gliu1) clock control clock control clock control
amd geode? lx processors data book 567 geodelink? pci bridge 33234h 6.15.1 geodelink? interface block the geodelink interface block provides a thin protocol conversion layer between the transaction forwarding block and geodelink interface unit 1 (gliu1). it is responsible for multiplexing in-bound write request data with out-bound read response data on the single gliu1 data out bus. 6.15.2 fifo/synchronization block the fifo module consists of a collection of in-bound and out-bound fifos. each fifo provides simple, synchro- nous interfaces to read and write requests. 6.15.3 transaction forwarding block the transaction forwarding block receives, processes, and forwards transaction reques ts and responses between the geodelink interface and pci bus interface blocks. it imple- ments the transaction ordering rules and performs write gathering and read prefetching as needed. it also performs the necessary translation between gliu1 and pci com- mands; except for the creation of pci configuration cycles in response to i/o accesses of address 0cfch. the trans- action forwarding block also handles the conversion between 64-bit gliu1 data paths and 32-bit pci data paths. out-bound transactions are handled in a strongly ordered fashion. some out-bound burst writes may be combined into a larger pci transaction. this is accomplished by dynamically concatenating t ogether contiguous bursts as they are streamed out in a pci bus transaction. single 32- bit word accesses are not gat hered. it is anticipated that the processor generates the majority of out-bound requests. out-bound memory writes will not be posted. thus, any queued out-bound requests need not be flushed prior to handling an in-bound read request. dynamic concatenation of c ontiguous bursts may occur when reading the penultimate (next to last) data word from the out-bound write data fi fo. on that cycle, if a suit- able request is available at the head of the out-bound request fifo, the pci burst will be extended. in-bound requests are handled using slightly relaxed order- ing. all in-bound writes are gathered as much as possible. any partially gathered in-bound writes are flushed when a cache line boundary is reached. all in-bound writes are posted. thus, any queued in-bound write data must be written to system memory prio r to the processor receiving data for an out-bound read request. this is accomplished by sorting out-bound read response data amongst in- bound write data. thus, a pending out-bound read request need not be deferred while posted in-bound write data is flushed. the out-bound read request may be performed on the pci bus at the same time that the in-bound write data is flowing through gliu1. when handling an in-bound read request, the intended size of the transfer is unknown. in-bound read requests for non- prefetchable addresses only fetch the data explicitly indi- cated in the pci transaction. thus, all in-bound read requests made to non-prefetchable addresses return at most a single 32-bit word. in-bound read requests made to prefetchable memory may cause more than a 32-bit word to be prefetched. the am ount of data prefetched is configured via the read threshold fields of the ctrl model specific register of glpci_ctrl (msr 50002010h). multi- ple read requests may be generated to satisfy the read threshold value. in-bound read requests may pass posted in-bound write data when there is no address collision between the read request and the address range of the posted write data (dif- ferent cache lines) and the read address is marked as being prefetchable. 6.15.3.1 atomic external msr access the companion device implements a mailbox scheme simi- lar to the amd geode lx processor. to access internal model specific registers on the amd geode companion device?s gliu it is necessary to perform multiple pci con- figuration cycles. the glpci module provides a mecha- nism to give software atomic, transparent access to the companion device?s gliu re sident msrs. it translates msr read/writes received from the amd geode lx pro- cessor?s glius into the multiple pci configuration needed to access the companion device?s internal msr. from soft- ware?s point of view, the glpci module routes msr read/ write requests like a gliu. the glpci module terminates msr accesses where the three most significant bits are zero. otherwise it uses the same three msbs as an index to look up a pci device number and a pci function number in glpci_ext (msr 5000201eh). this device number is then further mapped onto ad[31:11] pins using the same mapping as with software generated pci configuration cycles. next the glpci module performs three pci config- uration bus cycles. ? write msr address to offset f4h ? read/write msr data to/from offset f8h ? read/write msr data to/from offset fch note: the glpci module attempts to do a burst pci con- figuration read or write. it is expected that the tar- get pci device will typically cause this burst to get broken up into two by performing a slave termina- tion after each dword of data is transferred. the glpci module can address up to seven external pci devices in this manner.
568 amd geode? lx processors data book geodelink? pci bridge 33234h figure 6-59. atomic msr accesses across the pci bus gliu1 device-a device-b device-c pci-device = 1 pci-device = 15 pci-device = 25 pci-device = 30 2 4 3 6 5 1 2 7 3 amd geode? lx processor 2.4.1.3.6.x 2.4.2.5.1.x 2.4.3.2.7.3 glpci_ext (msr 5000201eh) configuration: gliu-port1 -> pci-device-15 gliu-port2 -> pci-device-25 gliu-port3 -> pci-device-30 gliu-port4 -> pci-device-1 glpci gliu0 gliu1 glpci gliu0 gliu1 glpci gliu0 gliu1 gliu2 glpci gliu0 cpu core
amd geode? lx processors data book 569 geodelink? pci bridge 33234h 6.15.4 pci bus interface block the pci bus interface block is compliant to the pci 2.2 specification, except in t he handling of serr#/perr# sig- nals. these signals are not available. the pci bus interface block provides a protocol conversion layer between the transaction forwarding block and the pci bus. the master and target portions of this block oper- ate independently. thus, out-bound write requests and in- bound read responses are effectively multiplexed onto the pci bus. it generates configuration cycles and software generated special cycles using the standard 0cf8h/0cfch i/o address scheme. it includes address decoding logic to recognize distinct address regions for slave operation. each address region is defined by a base address, a size, and some attached attributes (i.e., prefetchable, coherent). this block is responsible for retrying out-bound requests when a slave termination without data is seen on the pci bus. it must restart transactions on the pci bus that are prematurely ended with a slave termination. this block always slave terminates in-bound read transactions issued to non-prefetchable regions after a single dword has been transferred. the maximum inbound write throughput is only limited by the pci latency timer (see register glpci_ctrl bits [39:35]), which will interrupt an inbound transaction after the specified number of cycles. with this latency timer dis- abled (glpci_ctrl bit 9), the maximum throughput is achieved the maximum inbound read throughput is also affected by the pci latency timer in a similar fashion to the inbound write throughput. it is also affected by the inbound read prefetch threshold setting (g lpci_ctrl bits [59:56]). with the latency timer disabled and the read prefetch set to 0ah to 0fh, the maximum throughput is achieved. with the read prefetch threshold set to the default of 04h, the throughput is not optimal. 6.15.4.1 pci config uration and virtual pci header support the pci bus interface block implements the logic to gener- ate pci configuration cycles. the standard mechanism for generating pci configuration cycles (as described in the pci 2.2 specification) is used. to access the internal pci configuration registers of the amd geode lx processor, the configuration address reg- ister (config_address) must be written as a dword using the format shown in table 6-89. any other size will be interpreted as an i/o write to port 0cf8h. also, when entering the configuration index, only the six most signifi- cant bits of the offset are us ed, and the two least significant bits must be 00. byte and word sized i/o accesses to 0cf8h pass through the pci bus interface block onto the pci bus. writes to the config_data register are translated into pci configuration write bus cycles. reads to the config_data register are tr anslated into pci configura- tion read bus cycles. bit 31 of the config_address register gates the translation of i/o accesses to 0cfch into pci configuration cycles. idsel assertions are realized where device numbers 1 through 21 are mapped to the ad[11] through ad[31] pins. in addition, support is included for virtualization of pci buses and secondary bus devices. when a device or bus is virtualized, the pci bus interface block generates a syn- chronous smi for access to the config_data register instead of generati ng a configuration cycle on the pci bus. see glpci_pbus (msr register (msr 50002012h[31:0]) for details on virtual pci header support. the pci bus interface block can be configured to accept in-bound pci configur ation cycles. this is used as a debug method for indirectly accessing the internal model specific register from the pci bus. when this capability is enabled, the pci bus interface block responds to in-bound pci con- figuration cycles that make the pci bus interface block?s idsel signal become asserted (expected to be device 1). in this case, the pci bus interface block ignores writes and returns ffffffffh for accesse s to locations 00h through efh of the pci configuration space. this makes the pci bus interface block invisible to pci plug&play software. table 6-89. format for accessing the internal pci configuration registers 313029282726252423222120191817161514131211109876543210 1 reserved 0000000000000000 configuration index 00
570 amd geode? lx processors data book geodelink? pci bridge 33234h 6.15.5 pci arbiter the pci arbiter implements a fair arbitration scheme with special support for the companion device. by default it operates as a simple round-robin arbiter that rotates prior- ity in circular fashion (see figure 6-60). there are three external req#/gnt# pairs, numbered 0 through 2, and an internal req#/gnt# pair for the cpu. req2#/gnt2# is reserved for the amd geode companion device (i.e., southbridge). each requestor can be configured to be preemptable/non- preemptable (figure 6-61), given a repeat-count attribute and given a grant-hold timeout attribute. the repeat-count and grant-hold attributes ar e present to help balance the fairness of the pci bus when mixing bus masters of differ- ent bursting characteristics. for example, the companion device drops its req# signal after each grant and issues relatively small bursts, while some other bus masters present very long bursts on the pci bus. when both bus masters are concurrently active, the companion device gets a very small share of th e pci bus. the repeat-count allows a bus master to retain control of the pci bus across multiple bus tenures and the grant-hold keeps the grant asserted with an idle bus for a configurable number of clock cycles, giving the bus master a chance to reassert req# again. together they allow a small bursting bus master, like the companion device, to repeatedly issue a sequence of bursts before being preempted, giving it fair access to pci bandwidth even in the presence of a large bursting bus master (e.g., a modern network adapter). use of the repeat-count attribute has an impact on the preemptability of the bus master. that master can only be preempted when working on its last repeated access to the bus. for example, if a bus master has a repeat-count of 2 it may only be preempted on its third access to the bus. the arbi- ter can be configured to temporarily override this non-pre- emptability, particular master s that are requesting access to the pci bus. figure 6-60. simple round-robin figure 6-61. weighted round-robin table 6-90. pci device to ad bus mapping pci device ad pin pci device ad pin pci device ad pin pci device ad pin 0n/a8 18162624n/a 111919172725n/a 2 121020182826n/a 3 131121192927n/a 4 141222203028n/a 5 151323213129n/a 6 16142422n/a30n/a 7 17152523n/a31n/a cpu 0 2 1 cpu 0 2 1
amd geode? lx processors data book 571 geodelink? pci bridge 33234h 6.15.6 exception handling 6.15.6.1 out-bound write exceptions when performing an out-bound write on the pci bus, two errors may occur: target abort and perr# assertion. when a target abort occurs, the pci bus interface block must flush any stored write data. it must then report the error. the assertion of perr# is handled generically. the failed transaction will not be retried. 6.15.6.2 out-bound read exceptions when performing an out-bound read on the pci bus, two errors may occur: target abort and parity error. when a tar- get abort occurs, the pci bus interface block must return the expected amount of data with sufficient error signals. 6.15.6.3 in-bound write exceptions when performing an in-bound write from the pci bus, two errors may occur: a detected parity error and a gliu exception. a gliu exception cannot be relayed back to the originating pci bus master because in-bound pci writes are always posted. when a parity error is detected, the perr# signal must be asserted by the pci bus interface block. however, the corrupted write data will be passed along to the gliu. 6.15.6.4 in-bound read exceptions when performing an in-bound read from the gliu, the excep flag may be set on any received bus-word of data. this may be due to an address configuration error caused by software or by an error reported by the source of data. the asynchronous err and/or smi bit will be set by the pci bus interface block and the read data, valid or not, will be passed to the pci interface block along with the associated exceptions. the pc i bus interface block should simply pass the read response data along to the pci bus.
572 amd geode? lx processors data book geodelink? pci bridge register descriptions 33234h 6.16 geodelink? pci bridge register descriptions all geodelink? pci bridge (g lpci) registers are model specific registers (msrs) and are accessed via the rdmsr and wrmsr instructions. the registers associated with the glpci are the standard geodelink device (gld) msrs and glpci specific msrs. table 6-91 and table 6-92 are register summary tables that include reset values and page references where the bit descriptions are provided. the msr address is derived from the perspective of the cpu core. see section 4.1 "msr set" on page 45 for more detail on msr addressing. table 6-91. standard geodelink? device msrs summary msr address type register name reset value reference 50002000h ro gld capabilities msr (gld_msr_cap) 00000000_001054xxh page 574 50002001h r/w gld master configuration msr (gld_msr_config) 00000000_00000000h page 574 50002002h r/w gld smi msr (gld_msr_smi) 00000000_0000003fh page 575 50002003h r/w gld error msr (gld_msr_error) 00000000_0000003fh page 576 50002004h r/w gld power management msr (gld_msr_pm) 00000000_00000015h page 577 50002005h r/w gld diagnostic msr (gld_msr_diag) 00000000_00000000h page 577 table 6-92. glpci specific registers summary msr address type register name reset value reference 50002010h r/w glpci global control (glpci_ctrl) 44000000_00000000h page 578 50002011h r/w glpci arbiter control (glpci_arb) 00000000_00000000h page 581 50002012h r/w glpci vph / pci configuration cycle con- trol (glpci_pbus) 00ff0000_00000000h page 584 50002013h r/w glpci debug packet configuration (glpci_debug) 00000000_00000000h page 584 50002014h r/w glpci fixed region enables (glpci_ren) 00000000_00000000h page 584 50002015h r/w glpci fixed region configuration a0-bf (glpci_a0) 00000000_00000000h page 585 50002016h r/w glpci fixed region configuration c0-df (glpci_c0) 00000000_00000000h page 586 50002017h r/w glpci fixed region configuration e0-ff (glpci_e0) 00000000_00000000h page 587 50002018h r/w glpci memory region 0 configuration (glpci_r0) 00000000_00000000h page 588 50002019h r/w glpci memory region 1 configuration (glpci_r1) 00000000_00000000h page 589 5000201ah r/w glpci memory region 2 configuration (glpci_r2) 00000000_00000000h page 590 5000201bh r/w glcpi memory region 3 configuration (glpci_r3) 00000000_00000000h page 591 5000201ch r/w glcpi memory region 4 configuration (glpci_r4) 00000000_00000000h page 592
amd geode? lx processors data book 573 geodelink? pci bridge register descriptions 33234h 5000201dh r/w glpci memory region 5 configuration (glpci_r5) 00000000_00000000h page 593 5000201eh r/w glpci external msr access configuration (glpci ext_msr) 00000000_00000000h page 594 5000201fh r/w glpci spare 00000000_00000000h page 595 50002020h r/w glpci general purpose i/ o (glpci_gpio) 00000000_00000000h page 596 table 6-92. glpci specific registers summary msr address type register name reset value reference
574 amd geode? lx processors data book geodelink? pci bridge register descriptions 33234h 6.16.1 standard geodelink? device (gld) msrs 6.16.1.1 gld capabilities msr (gld_msr_cap) 6.16.1.2 gld master configur ation msr (gld_msr_config) msr address 50002000h ty p e r o reset value 00000000_001054xxh gld_msr_cap register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd dev_id rev_id gld_msr_cap bit descriptions bit name description 63:24 rsvd reserved. reserved for future use. 23:8 dev_id device id. identifies device (1054h). 7:0 rev_id revision id. identifies device revision. see amd geode? lx processors specification update document for value. msr address 50002001h ty p e r / w reset value 00000000_00000000h gld_msr_config register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd pri rsvd pid gld_msr_config bit descriptions bit name description 63:7 rsvd (ro) reserved (read only). reserved for future use. 6:4 pri priority. default priority. 3 rsvd (ro) reserved (read only). reserved for future use. 2:0 pid priority id. assigned priority domain.
amd geode? lx processors data book 575 geodelink? pci bridge register descriptions 33234h 6.16.1.3 gld smi msr (gld_msr_smi) msr address 50002002h ty p e r / w reset value 00000000_0000003fh gld_msr_smi register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pa r e syse vphe bme ta r e mare rsvd pa r m sysm vphm bmm ta r m marm gld_msr_smi bit descriptions bit name description 63:22 rsvd (ro) reserved (read only). reserved for future use. 21 pare parity error event (r ead/write-1-to-clear). this bit is asserted due to detection of a pci bus parity error. write 1 to clear. ps (msr 50002010h[27]) must be set to enable this event. the event causes an asmi if parm (bit 5) is cleared. 20 syse system error event (r ead/write-1-to-clear). this bit is asserted due to the detection of a pci bus system error. write 1 to cl ear. ps (msr 50002010h[27]) must be set to enable this event. the event causes an asmi if sysm (bit 4) is cleared. 19 vphe virtual pci header event (read/write-1-to-clear). this bit is set by virtual pci header support logic, write 1 to clear. the event c auses an ssmi if vphm (bit 3) is cleared. 18 bme broken master event (read/write-1-to-clear). this bit is asserted due to detection of a broken pci bus master. write 1 to clear. bms (msr 50002010h[26]) must be set to enable this event. the event causes an asmi if bmm (bit 2) is cleared. 17 tare target abort received event (read/write-1-to-clear). this bit is asserted due to reception of target abort on pci. write 1 to clear. tars (msr50002010h[25]) must be set to enable this event. the event causes an asmi if tarm (bit 1) is cleared. 16 mare master abort received even t (read/write-1-to-clear). this bit is asserted due to reception of master abort on pci. write 1 to clear. mars (msr 50002010h[24]) must be set to enable this event. the event causes an asmi if marm (bit 0) is cleared. 15:6 rsvd reserved. reserved for future use. 5parm parity error mask. clear to allow pare (bit 21) to generate an asmi. 4 sysm system error mask. clear to allow syse (bit 20) to generate an asmi. 3 vphm virtual pci header mask. clear to allow ssmi flag to be set in selected gliu response packets. i/o reads and writes to location 0cfch may cause an ssmi depending upon the configuration of this bit and the glpci_ pbus (msr 50002012h) model specific reg- isters. 2bmm broken master mask. clear to allow bme (bit 18) to generate an asmi. 1tarm target abort received mask. clear to allow tare (bit 17) to generate an asmi. 0marm master abort received mask. clear to allow mare (bit 16) to generate an asmi.
576 amd geode? lx processors data book geodelink? pci bridge register descriptions 33234h 6.16.1.4 gld error msr (gld_msr_error) msr address 50002003h ty p e r / w reset value 00000000_0000003fh gld_msr_error register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pa r e syse rsvd bme ta r e mare rsvd pa r m sysm rsvd bmm ta r m marm gld_msr_error bit descriptions bit name description 63:22 rsvd (ro) reserved (read only). reserved for future use. 21 pare parity error event (r ead/write-1-to-clear). this bit is asserted due to detection of a pci bus parity error. write 1 to clear. pe (msr 50002010h[31]) must be set to enable this event. the event causes an err if parm (bit 5) is cleared. 20 syse system error event (r ead/write-1-to-clear). this bit is asserted due to the detection of a pci bus system error. write 1 to cl ear. pe (msr 50002010h[31]) must be set to enable this event. the event causes an err if sysm (bit 4) is cleared. 19 rsvd (ro) reserved (read only). reserved for future use. 18 bme broken master event (read/write-1-to-clear). this bit is asserted due to detection of a broken pci bus master. write 1 to clear. bme (msr 50002010h[30]) must be set to enable this event. the event causes an err if bmm (bit 2) is cleared. 17 tare target abort received event (read/write-1-to-clear). this bit is asserted due to the reception of a target abort on pci. write 1 to clear. tare (msr 50002010h[29]) must be set to enable this event. the event causes an err if tarm (bit 1) is cleared. 16 mare master abort received even t (read/write-1-to-clear). this bit is asserted due to the reception of a master abort on pci. write 1 to clear. mare (msr 50002010h[28]) must be set to enable this event. the event causes an err if marm (bit 0) is cleared. 15:6 rsvd (ro) reserved (read only). reserved for future use. 5parm parity error mask. clear to allow pare (bit 21) to generate an err. 4 sysm system error mask. clear to allow syse (bit 20) to generate an err. 3 rsvd (ro) reserved (read only). reserved for future use. 2bmm broken master mask. clear to allow bme (bit 18) to generate an err. 1tarm target abort received mask. clear to allow tare (bit 17) to assert err. 0marm master abort received mask. clear to allow mare (bit 16) to assert err.
amd geode? lx processors data book 577 geodelink? pci bridge register descriptions 33234h 6.16.1.5 gld power management msr (gld_msr_pm) 6.16.1.6 gld diagnostic msr (gld_msr_diag) this register is for amd use only and should not be written to. msr address 50002004h ty p e r / w reset value 00000000_00000015h gld_msr_pm register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd 313029282726252423222120191817161514131211109876543210 rsvd pm2 rsvd pm1 rsvd pm0 gld_msr_pm bit descriptions bit name description 63:5 rsvd (ro) reserved (read only). reserved for future use. 4pm2 power mode 2. power mode for pci-fast clock domain. 0: disable clock gating. clocks are always on. 1: enable active hardware clock gating. 3 rsvd (ro) reserved (read only). reserved for future use. 2pm1 power mode 1. power mode for pci clock domain. 0: disable clock gating. clocks are always on. 1: enable active hardware clock gating. 1 rsvd (ro) reserved (read only). reserved for future use. 0pm0 power mode 0. power mode for gliu clock domain. 0: disable clock gating. clocks are always on. 1: enable active hardware clock gating. msr address 50002005h ty p e r / w reset value 00000000_00000000h
578 amd geode? lx processors data book geodelink? pci bridge register descriptions 33234h 6.16.2 glpci specific registers 6.16.2.1 glpci global control (glpci_ctrl) msr address 50002010h ty p e r / w reset value 44000000_00000000h glpci_ctrl register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 fth rth sbrth rtl dtl wto slto ilto lat 0 313029282726252423222120191817161514131211109876543210 pe bme ta r e mare ps bms ta r s mars sus irft irfc iod st er rhe lde rupo bz ni iso owc iwc pcd ie me glpci_ctrl bit descriptions bit name description 63:60 fth in-bound flush threshold. controls the timing for requesting new read data while con- currently flushing previously prefetched, stal e read data. if the numb er of prefetched 64- bit words reaches this level then a pending request will be made. 59:56 rth in-bound read threshold. controls the timing for prefet ching read data. if the number of prefetched 32-bit words reaches this threshold, a subsequent gliu request will be generated to fetch the next cache line of read data. 55:52 sbrth southbridge in-bound read threshold. controls the timing for prefetching read data for the amd geode? companion device. if the number of prefetched 32-bit words reaches this threshold, a subsequent gliu request will be generated to fetch the next cache line of read data. the status of the co mpanion device?s gnt# pin (gnt2#) is sam- pled to determine when the companion de vice is generating an in-bound request. 51:49 rtl retry transaction limit. limits the number of out-bound retries. if a target signals retry indefinitely, the pci interface may be configured to abort the failing out-bound request. 000: no limit 100: 64 retries 001: 8 retries 101: 128 retries 010: 16 retries 110: 256 retries 011: 32 retries 111: 512 retries 48:46 dtl delayed transaction limit. limits the duration of delayed transactions. once a read transaction is delayed (retried before the first data phase has completed) all other in- bound transactions are rejected until the original request is satisfied. if the original master stops retrying, a live-lock condition may occur. if the number of rejected transactions reaches the limit defined by this field, then the delayed transaction is forgotten. 000: no limit 100: 16 rejections 001: 2 rejections 101: 32 rejections 010: 4 rejections 110: 64 rejections 011: 8 rejections 111: 128 rejections 45:43 wto in-bound write timeout. controls the flushing of in-bound posted write data. when an in-bound write has completed on the pci bus, an internal counter is loaded with a value derived from this field. it will then count do wn on each pci clock edge. when the counter reaches 0, the posted write data is flushed to memory. 000: 4 pci clock edge 100: 64 pci clock edges 001: 8 pci clock edge 101: 128 pci clock edges 010: 16 pci clock edge 110: 256 pci clock edges 011: 32 pci clock edges 111: no timeout
amd geode? lx processors data book 579 geodelink? pci bridge register descriptions 33234h 42 slto subsequent latency timeout select. specifies the subsequent target latency timeout limit. if within a burst, the glpci module does not respond with the configured number of clock ticks, the pci interface will terminate the pci bus cycle. 0: 8 pci clock edges 1: 4 pci clock edges 41:40 ilto initial latency timeout select. specifies the initial target latency timeout limit for the pci interface. if the glpci module does not respond with the first data phase within the configured number of clock edges, the pci interface will terminate the pci bus cycle. if ailto (msr 5000201fh[6]) = 0 00: 32 pci clock edges 10: 8 pci clock edges 01: 16 pci clock edges 11: 4 pci clock edges if ailto = 1 00: 64 pci clock edges 10: 256 pci clock edges 01: 128 pci clock edges 11: no timeout 39:35 lat pci latency timer. latency timeout value for limiting bus tenure. 34:32 0 (ro) constant 0 (read only). the three least significant bits of the pci latency timer field are fixed as zeros. these bits are not used as part of the pci latency timer comparison. 31 pe pci error. allow detection of either a parity error or a system error to be reported in the pare bit (msr 50002003h[21]). 0: disable. 1: enable. 30 bme broken master error. allow detection of a broken pci bus master to be reported in the bme bit (msr 50002003h[18]). 0: disable. 1: enable. 29 tare target abort received error. allow reception of a pci bus target abort to be reported in the tare bit (msr 50002003h[17]). 0: disable. 1: enable. 28 mare master abort received error. allow reception of a pci bus master abort to be reported in the mare bit (msr 50002003h[16]). 0: disable. 1: enable. 27 ps pci asmi. allow detection of either a parity error or a system error to be reported in the pare bit (msr 50002002h[21]). 0: disable. 1: enable. 26 bms broken master asmi. allow detection of a broken pci bus master to be reported in the bme bit (msr 50002002h[18]). 0: disable. 1: enable. 25 tars target abort received asmi. allow reception of a pci bus target abort to be reported in the tare bit (msr 50002002h[17]). 0: disable. 1: enable. glpci_ctrl bit descriptions (continued) bit name description
580 amd geode? lx processors data book geodelink? pci bridge register descriptions 33234h 24 mars master abort receive asmi. allow reception of a pci bus master abort to be reported in the tare bit (msr 50002002h[17]). 0: disable. 1: enable. 23:21 sus busy sustain. controls the sustain time for keeping the clocks running after the internal busy signals indicate that the clocks may be gated. 000: no sustain 100: 32 clock cycles 001: 4 clock cycles 10 1: 64 clock cycles 010: 8 clock cycles 110: 128 clock cycles 011: 16 clock cycles 11 1: 256 clock cycles 20:18 irft in-bound read flush timeout. controls the flushing of in -bound prefetch read data. when an in-bound read has completed on the pci bus, an internal counter is loaded with a value derived from this field. it then counts down on each pci clock edge. when the counter reaches 0, any remaining prefetched data is flushed. the c ounter stops counting down if a subsequent in-bound read is received. it continues to count down through an in-bound write and through any out-bound traffic. 000: 4 pci clock edge 100: 64 pci clock edges 001: 8 pci clock edges 101: 128 pci clock edges 010: 16 pci clock edges 110: 256 pci clock edges 011: 32 pci clock edges 111: no timeout 17:16 irfc in-bound read flush control. controls the policy for discarding stale data from in- bound read data fifo. 00: discard at end of in-bound read pci transaction. 01: discard upon timeout. 10: discard at start of out-bound write or upon timeout. 11: discard at start of out-bound write, at start of out-bound read or upon timeout. in addition to these policies, in-bound read data will be discarded whenever a non-contig- uous in-bound read is accepted, or when an in-b ound write is received that will affect the prefetched memory. 15:13 iod i/o delay. delay completion of out-bound i/o transactions for a configurable number of pci clock cycles. 000: 0 pci clock cycles 001: 1 pci clock cycles 010: 2 pci clock cycles 011: 4 pci clock cycles 100: 8 pci clock cycles 101: 16 pci clock cycles 110: 32 pci clock cycles 111: 64 pci clock cycles 12 st short timer. when cleared to 0, delayed transactions are discarded after 2 15 pci clock cycles. when set to 1, delayed transactions are discarded after 2 5 pci clock cycles. for normal operation. this bit should be cleared. 11 er early read. when cleared to 0, out-bound reads ar e stalled until there is enough fifo space in the out-bound read fifo to hold data for the entire transaction. when set to 1, out-bound reads will start as soon as possible. 10 rhe read hints enable. when cleared to 0, all out-bound reads use pci cmd = 6. when set to 1, the pci cmd provides a hint about the size of the read request. 6: 1, 2 or 4 dwords e: 8 dwords glpci_ctrl bit descriptions (continued) bit name description
amd geode? lx processors data book 581 geodelink? pci bridge register descriptions 33234h 6.16.2.2 glpci arbite r control (glpci_arb) 9lde latency disconnect enable. writing 1, causes the pci interface to disconnect from a pci bus master when a latency timer expirati on occurs. this enforces the configured min- imum latency upon pci bus masters where the glpci module is a target on the pci bus. the latency timer must be greater than 0 when using this feature. 8rupo relax up-stream ordering. removes ordering restrictions for out-bound read response data with respect to in-bound write data. setti ng this bit also causes the glpci to clear the send_response flag for in-bound gliu request packe ts. this bit should be cleared for normal operation. 7bz bizarro flag. bizarro flag configuration to use on in-bound i/o reads and writes. 6ni no invalidate flag. force the invalidate flag to be cleared for all in-bound writes. 5iso in-bound strong ordering. disables the ability of in-bound reads to coherently pass posted in-bound writes. when set to 1, a pci read request received by the host bridge target is not forwarded to gliu until all posted write data has been flushed to memory. this bit should be cleared for normal operation. 4owc out-bound write combining. enables concatenation of out-bound write bursts into a larger pci burst. setting this bit does not add any additional latency to out-bound writes. 3iwc in-bound write combining. enables combining of different in-bound pci write transac- tions into a single gliu host write transaction. when cleared to 0, pci write data received from the host bridge target is not he ld in the posted write buffer; a gliu transac- tion is generated immediately. 2pcd in-bound pci configuration disable. disables the handling of in-bound pci configura- tion cycles. when set to 1, pci configuration cycles are not accepted by this pci inter- face. after reset, the glpci module accepts in-bound pci co nfiguration cycles to provide a means of generating msr transactions onto the internal gliu. for normal operation this capability should be disabled. 1ie i/o enable. enable handling of in-bound i/o transac tions from pci. when set to 1, the pci interface accepts all in-bound i/o transactions from pci. this mode is only intended for design verification purposes. when cleared to 0, no in-bound i/o transactions are accepted. 0me memory enable. enable handling of in-bound memo ry access transaction from pci. when cleared to 0 the pci interface does not accept any in-bound memory transactions from the pci bus. when set to 1, the pci interface accepts in-bound memory transac- tions for those address ranges defined in the region configuration registers. msr address 50002011h ty p e r / w reset value 00000000_00000000h glpci_ctrl bit descriptions (continued) bit name description glpci_arb register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 cr r2 r1 r0 ch h2 h1 h0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd cov ov2 ov1 ov0 rsvd msk2 msk1 msk0 rsvd cpre pre2 pre1 pre0 bm1 bm0 rsvd ea bmd pa r k
582 amd geode? lx processors data book geodelink? pci bridge register descriptions 33234h glpci_arb bit definitions bit name description 63:60 cr cpu repeat. controls the number of consecutive grants given to the cpu before rotat- ing to the next requestor. this is only valid if there is a non-zero value for the cpu hold- grant control (ch, bits [47:44]). this may be overidden by either ov2, ov1 or ov0 (bits [22:20]). it is also ignored if the cpre (bit 11) is cleared. 59:56 r2 request repeat 2. controls the number of consecutive grants given to pci requestor 2 before rotating to the next requestor. this is only valid if there is a non-zero value for the request hold-grant2 control (h2, bits [43:40] ). this may be overidden by either cov, ov1, or ov0 (bits [23,21,20]. it is also ignored if the arb.pre2 bit is cleared. 55:52 r1 request repeat 1. controls the number of consecutive grants given to pci requestor 1 before rotating to the next requestor. this is only valid if there is a non-zero value for the request hold-grant1 control (h1, bits [39:36] ). this may be overidden by either cov, ov2, or ov1 (bits [23,22,21]. it is also i gnored if the pre1 (bit 9) is cleared. 51:48 r0 request repeat 0. controls the number of consecutive grants given to pci requestor 0 before rotating to the next requestor. this is only valid if there is a non-zero value for the request hold-grant0 control (h0, bits [35: 32]). this may be overidden by either the arb.cov, arb.ov2 or arb.ov1 controls. it is also ignored if pre0 (bit 8) is cleared. 47:44 ch cpu hold-grant controls. controls the number of pci clock edges that the pci bus must be idle after a cpu transaction before ar bitration continues. this is only valid if there is a non-zero value for the cpu repeat field (cr, bits [63:60]). this may be overid- den by either ov2, ov1, or ov0 (bits [22,21,20 ]). it is also ignored if cpre (bit 11) is cleared. 43:40 h2 request hold-grant 2. controls the number of pci clock edges that the pci bus must be idle after a requestor 2 transaction before arbitration continues. this is only valid if there is a non-zero value for the request repeat 2 field (r2, bits [59:56]). this may be overidden by either cov, ov1, or ov0 (bits [23, 21,20]). it is also ignored if pre2 (bit 10) is cleared. 39:36 h1 request hold-grant 1. controls the number of pci clock edges that the pci bus must be idle after a requestor 1 transaction before arbitration continues. this is only valid if there is a non-zero value for the request repeat 1 field (r1, bits [55:52]). this may be overidden by either cov, ov1, or ov0 (bits [23, 21,20]). it is also ignored if the if pre2 (bit 10) is cleared. 35:32 h0 request hold-grant 0. controls the number of pci cloc k ticks that the pci bus must be idle after a requestor 0 transaction before arbitr ation continues. this is only valid if there is a non-zero value for the request repeat 0 field (r0, bits [51:48]). this may be overid- den by either cov, ov1, or ov0 (bits [23,21,20 ]). it is also ignored if pre2 (bit 10) is cleared. 31:24 rsvd (ro) reserved (read only). reserved for future use. 23 cov cpu override. enables the cpu to override the repeat-count and grant-hold for other requestors. when cov is set and the cpu is requesting access to pci, repeat-count and grant-hold mechanisms for other masters ar e temporarily disabled. this bit does not change the round robin arbitration cycle, it on ly overrides repeat-count and grant-hold for other requestors. 22 ov2 override 2. enables requester2 to override the repeat-count and grant-hold for other requestors. when ov2 is set and req2# is asserted, repeat-count and grant-hold mech- anisms for other masters are temporarily disabled. this bit does not change the round robin arbitration cycle, it only overrides r epeat-count and grant-hold for other requestors. 21 ov1 override 1. enables requester1 to override the repeat-count and grant-hold for other requestors. when ov1 is set and req1# is asserted, repeat-count and grant-hold mech- anisms for other masters are temporarily disabled. this bit does not change the round robin arbitration cycle, it only overrides r epeat-count and grant-hold for other requestors.
amd geode? lx processors data book 583 geodelink? pci bridge register descriptions 33234h 20 ov0 override 0. enables requester0 to override the repeat-count and grant-hold for other requestors. when ov0 is set and req0# is asserted, repeat-count and grant-hold mech- anisms for other masters are temporarily disabled. this bit does not change the round robin arbitration cycle, it only overrides r epeat-count and grant-hold for other requestors. 19 rsvd (ro) reserved (read only). reserved for future use. 18 msk2 request mask 2. disables req2# when set to 1. resets to 0. 17 msk1 request mask 1. disables req1# when set to 1. resets to 0. 16 msk0 request mask 0. disables req0# when set to 1. resets to 0. 15:12 rsvd (ro) reserved (read only). reserved for future use. 11 cpre cpu preemption enable. when set to 1, the cpu?s pci grant may be de-asserted before the cpu?s request is de-asserted. if this bit is cleared, the arbiter ignores ch and cr, bits [47:44] and [63:60]. 10 pre2 preemption enable 2. when set to 1, gnt2# may be de-asserted before req2# is de- asserted. if this bit is cleared, the arbite r ignores r2 and h2, bits [59:56] and [43:40]. 9pre1 preemption enable 1. when set to 1, gnt1# may be de-asserted before req1# is de- asserted. if this bit is cleared, the arbiter ignores the r1 and h1, bits [55:52] and [39:36]. 8pre0 preemption enable 0. when set to 1, gnt0# may be de-asserted before req0# is de- asserted. if this bit is cleared, the arbite r ignores r0 and h0, bits [51:48] and [35:32]. 7 bm1 (ro) broken master 1 (read only). indicates when a broken master is attached to req1#. this bit is set when the arbiter detects that the pci bus master attached to req1# has not asserted frame# within 16 pci clock edges after being granted the pci bus. this bit is cleared by setting bmd (bit 1) to 1. 6 bm0 (ro) broken master 0 (read only). indicates when a broken master is attached to req0#. this bit is set when the arbiter detects that the pci bus master attached to req[0]# has not asserted frame# within 16 pci clock edges after being granted the pci bus. this bit is cleared by setting the bmd (bit 1) to 1. 5:2 rsvd (ro) reserved (read only). reserved for future use. 1bmd broken master timer disable. controls the operation of th e broken master detector in the pci arbiter. when set to 1, the arbiter does not recognize a broken master condition on the pci bus. when cleared to 0, the arbite r detects a broken master condition when a granted pci bus master take s 16 or more clock cycles before asserting frame#. the broken master is not allowed to gain access to the pci bus. software may restore any broken master?s permission to use the pci bus by clearing this bit, and optionally, setting it again. 0park parking policy. when cleared to 0, the arbiter always parks the pci bus on the amd geode? lx processor. when set to 1, the arbiter parks the pci bus on the last granted bus master. if this bit is set, the clock for the pci-fast clock domain should not be gated. glpci_arb bit definitions (continued) bit name description
584 amd geode? lx processors data book geodelink? pci bridge register descriptions 33234h 6.16.2.3 glpci vph / pci configur ation cycle control (glpci_pbus) the pbus model specific register is us ed to control the way that the glpci module generates (or does not generate) pci configuration cycles onto the pci bus. sec (bits [39:32]) should be configured with the pci bus number for the locally attached pci bus. sub (bits [55:48]) should be configured wit h the pci bus number for the highest numbered pci bus that is accessible via the pci interface. dev (bits [31:0]) should be configured to indicate which device numbers will not gener- ate pci configuration cycles on the pci bus. 6.16.2.4 glpci debug packet configuration (glpci_debug) control relay of debug packets to pci. the functionality that this register controls has bee n removed from the gliu. there- fore this register is obsolete. 6.16.2.5 glpci fixed region enables (glpci_ren) msr address 50002012h ty p e r / w reset value 00ff0000_00000000h glpci_pbus register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd sub rsvd sec 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dev glpci_pbus bit descriptions bit name description 63:56 rsvd (ro) reserved (read only). reserved for future use. 55:48 sub subordinate bus number. specifies the subordinate pci bus number for all pci buses reachable via the pci interface. 47:40 rsvd (ro) reserved (read only). reserved for future use. 39:32 sec secondary bus number. specifies the secondary pci bus number for the pci interface. 31:0 dev device bitmap. specifies the virtualized pci devices. each bit position corresponds to a device number. a 0 instructs the glpci to al low pci configuration cycles for the device to be generated on the pci bus. a 1 tells the glpci to virtualize the device by generating an ssmi instead of a pc i configuration cycle. msr address 50002013h ty p e r / w reset value 00000000_00000000h msr address 50002014h ty p e r / w reset value 00000000_00000000h glpci_ren register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 spare 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd fc f8 f4 f0 ec e8 e4 e0 dc d8 d4 d0 cc c8 c4 c0 bc b8 b4 b0 ac a8 a4 a0
amd geode? lx processors data book 585 geodelink? pci bridge register descriptions 33234h 6.16.2.6 glpci fixed region configuration a0-bf (glpci_a0) glpci_ren bit descriptions bit name description 63:32 spare spare bits. extra bits available for future use. these bits may be set and cleared, but do not control anything. 31:24 rsvd (ro) reserved (read only). reserved for future use 23 fc fc enable. enables memory access to fc000 through fffff from pci. 22 f8 f8 enable. enables memory access to f8000 through fbfff from pci. 21 f4 f4 enable. enables memory access to f4000 through f7fff from pci. 20 f0 f0 enable. enables memory access to f0000 through f3fff from pci. 19 ec ec enable. enables memory access to ec000 through effff from pci. 18 e8 e8 enable. enables memory access to e8000 through ebfff from pci. 17 e4 e4 enable. enables memory access to e4000 through e7fff from pci. 16 e0 e0 enable. enables memory access to e0000 through e3fff from pci. 15 dc dc enable. enables memory access to dc000 through dffff from pci. 14 d8 d8 enable. enables memory access to d8000 through dbfff from pci. 13 d4 d4 enable. enables memory access to d4000 through d7fff from pci. 12 d0 d0 enable. enables memory access to d0000 through d3fff from pci. 11 cc cc enable. enables memory access to cc000 through cffff from pci. 10 c8 c8 enable. enables memory access to c8000 through cbfff from pci. 9c4 c4 enable. enables memory access to c4000 through c7fff from pci. 8c0 c0 enable. enables memory access to c0000 through c3fff from pci. 7bc bc enable. enables memory access to bc000 through bffff from pci. 6b8 b8 enable. enables memory access to b8000 through bbfff from pci. 5b4 b4 enable. enables memory access to b4000 through b7fff from pci. 4b0 b0 enable. enables memory access to b0000 through b3fff from pci. 3ac ac enable. enables memory access to ac000 through affff from pci. 2a8 a8 enable. enables memory access to a8000 through abfff from pci. 1a4 a4 enable. enables memory access to a4000 through a7fff from pci. 0a0 a0 enable. enables memory access to a0000 through a3fff from pci. msr address 50002015h ty p e r / w reset value 00000000_00000000h glpci_a0 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 bc b8 b4 b0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ac a8 a4 a0
586 amd geode? lx processors data book geodelink? pci bridge register descriptions 33234h 6.16.2.7 glpci fixed region configuration c0-df (glpci_c0) glpci_a0 bit descriptions bit name description (note 1) 63:56 bc bc properties. region properties for bc000 through bffff. 55:48 b8 b8 properties. region properties for b8000 through bbfff. 47:40 b4 b4 properties. region properties for b4000 through b7fff. 39:32 b0 b0 properties. region properties for b0000 through b3fff. 31:24 ac ac properties. region properties for ac000 through affff. 23:16 a8 a8 properties. region properties for a8000 through abfff. 15:8 a4 a4 properties. region properties for a4000 through a7fff. 7:0 a0 a0 properties. region properties for a0000 through a3fff. note 1. see table 6-93 for region properties bit decodes. table 6-93. region properties bit name description 7:6 rsvd (ro) reserved (read only). reserved for future use. 5pf prefetchable. reads to this region have no side-effects. 4wc write combine. writes to this region may be combined. 3 rsvd (ro) reserved (read only). reserved for future use. 2wp write protect. when set to 1, only read accesse s are allowed. write accesses are ignored (master abort). 1dd discard data. when set to 1, write access are accepted and discarded. read accesses are ignored (master abort). 0cd cache disable. when set to 1, accesses are marked as non-coherent. when cleared to 0, accesses are marked as coherent. msr address 50002016h ty p e r / w reset value 00000000_00000000h glpci_c0 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dc d8 d4 d0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cc c8 c4 c0 glpci_c0 bit descriptions bit name description (note 1) 63:56 dc dc properties. region properties for dc000 through dffff. 55:48 d8 d8 properties. region properties for d8000 through dbfff. 47:40 d4 d4 properties. region properties for d4000 through d7fff.
amd geode? lx processors data book 587 geodelink? pci bridge register descriptions 33234h 6.16.2.8 glpci fixed region configuration e0-ff (glpci_e0) 39:32 d0 d0 properties. region properties for d0000 through d3fff. 31:24 cc cc properties. region properties for cc000 through cffff. 23:16 c8 c4 properties. region properties for c8000 through cbfff. 15:8 c4 c4 properties. region properties for c4000 through c3fff. 7:0 c0 c0 properties. region properties for c0000 through c3fff. note 1. see table 6-93 on page 586 for region properties bit decodes. msr address 50002017h ty p e r / w reset value 00000000_00000000h glpci_c0 bit descriptions (continued) bit name description (note 1) glpci_e0 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 fc f8 f4 f0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ec e8 e4 e0 glpci_e0 bit descriptions bit name description (note 1) 63:56 fc fc properties. region properties for fc000 through fffff. 55:48 f8 f8 properties. region properties for f8000 through fbfff. 47:40 f4 f4 properties. region properties for f4000 through f7fff. 39:32 f0 f0 properties. region properties for f0000 through f3fff. 31:24 ec ec properties. region properties for ec000 through effff. 23:16 e8 e4 properties. region properties for e8000 through ebfff. 15:8 e4 e4 properties. region properties for e4000 through e3fff. 7:0 e0 e0 properties. region properties for e0000 through e3fff. note 1. see table 6-93 on page 586 for region properties bit decodes.
588 amd geode? lx processors data book geodelink? pci bridge register descriptions 33234h 6.16.2.9 glpci memory region 0 configuration (glpci_r0) msr address 50002018h ty p e r / w reset value 00000000_00000000h glpci_r0 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 top rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base rsvd en rsvd pf wc rsvd wp dd cd glpci_r0 bit descriptions bit name description 63:44 top top of region. 4 kb granularity, inclusive. 43:32 rsvd (ro) reserved (read only). reserved for future use. 31:12 base base of region. 4 kb granularity, inclusive. 11:9 rsvd (ro) reserved (read only). reserved for future use. 8en region enable. set to 1 to enable access to this region. 7:6 rsvd (ro) reserved (read only). reserved for future use. 5pf prefetchable. reads to this region have no side-effects. 4wc write combine. writes to this region may be combined. 3 rsvd (ro) reserved (read only). reserved for future use. 2wp write protect. when set to 1, only read accesse s are allowed. write accesses are ignored (master abort). 1dd discard data. when set to 1, write access are accepted and discarded. read accesses are ignored (master abort). 0cd cache disable. when set to 1, accesses are marked as non-coherent. when cleared to 0 accesses are marked as coherent.
amd geode? lx processors data book 589 geodelink? pci bridge register descriptions 33234h 6.16.2.10 glpci memory region 1 configuration (glpci_r1) msr address 50002019h ty p e r / w reset value 00000000_00000000h glpci_r1 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 top rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base rsvd en rsvd pf wc rsvd wp dd cd glpci_r1 bit descriptions bit name description 63:44 top top of region. 4 kb granularity, inclusive. 43:32 rsvd (ro) reserved (read only). reserved for future use. 31:12 base base of region. 4 kb granularity, inclusive. 11:9 rsvd (ro) reserved (read only). reserved for future use. 8en region enable. set to 1 to enable access to this region. 7:6 rsvd (ro) reserved (read only). reserved for future use. 5pf prefetchable. reads to this region have no side-effects. 4wc write combine. writes to this region may be combined. 3 rsvd (ro) reserved (read only). reserved for future use. 2wp write protect. when set to 1, only read accesse s are allowed. write accesses are ignored (master abort). 1dd discard data. when set to 1, write access are accepted and discarded. read accesses are ignored (master abort). 0cd cache disable. when set to 1, accesses are marked as non-coherent. when cleared to 0, accesses are marked as coherent.
590 amd geode? lx processors data book geodelink? pci bridge register descriptions 33234h 6.16.2.11 glpci memory region 2 configuration (glpci_r2) msr address 5000201ah ty p e r / w reset value 00000000_00000000h glpci_r2 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 top rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base rsvd en rsvd pf wc rsvd wp dd cd glpci_r2 bit descriptions bit name description 63:44 top top of region. 4 kb granularity, inclusive. 43:32 rsvd (ro) reserved (read only). reserved for future use. 31:12 base base of region. 4 kb granularity, inclusive. 11:9 rsvd (ro) reserved (read only). reserved for future use. 8en region enable. set to 1 to enable access to this region. 7:6 rsvd (ro) reserved (read only). reserved for future use. 5pf prefetchable. reads to this region have no side-effects. 4wc write combine. writes to this region may be combined. 3 rsvd (ro) reserved (read only). reserved for future use. 2wp write protect. when set to 1, only read accesse s are allowed. write accesses are ignored (master abort). 1dd discard data. when set to 1, write access are accepted and discarded. read accesses are ignored (master abort). 0cd cache disable. when set to 1, accesses are marked as non-coherent. when cleared to 0, accesses are marked as coherent.
amd geode? lx processors data book 591 geodelink? pci bridge register descriptions 33234h 6.16.2.12 glcpi memory region 3 configuration (glpci_r3) msr address 5000201bh ty p e r / w reset value 00000000_00000000h glpci_r3 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 top rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base rsvd en rsvd pf wc rsvd wp dd cd glpci_r3 bit descriptions bit name description 63:44 top top of region. 4 kb granularity, inclusive. 43:32 rsvd (ro) reserved (read only). reserved for future use. 31:12 base base of region. 4 kb granularity, inclusive. 11:9 rsvd (ro) reserved (read only). reserved for future use. 8en region enable. set to 1 to enable access to this region. 7:6 rsvd (ro) reserved (read only). reserved for future use. 5pf prefetchable. reads to this region have no side-effects. 4wc write combine. writes to this region may be combined. 3 rsvd (ro) reserved (read only). reserved for future use. 2wp write protect. when set to 1, only read accesse s are allowed. write accesses are ignored (master abort). 1dd discard data. when set to 1, write access are accepted and discarded. read accesses are ignored (master abort). 0cd cache disable. when set to 1, accesses are marked as non-coherent. when cleared to 0, accesses are marked as coherent.
592 amd geode? lx processors data book geodelink? pci bridge register descriptions 33234h 6.16.2.13 glcpi memory region 4 configuration (glpci_r4) msr address 5000201ch ty p e r / w reset value 00000000_00000000h glpci_r4 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 top rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base rsvd en rsvd pf wc rsvd wp dd cd glpci_r4 bit descriptions bit name description 63:44 top top of region. 4 kb granularity, inclusive. 43:32 rsvd (ro) reserved (read only). reserved for future use. 31:12 base base of region. 4 kb granularity, inclusive. 11:9 rsvd (ro) reserved (read only). reserved for future use. 8en region enable. set to 1 to enable access to this region. 7:6 rsvd (ro) reserved (read only). reserved for future use. 5pf prefetchable. reads to this region have no side-effects. 4wc write combine. writes to this region may be combined. 3 rsvd (ro) reserved (read only). reserved for future use. 2wp write protect. when set to 1, only read accesse s are allowed. write accesses are ignored (master abort). 1dd discard data. when set to 1, write access are accepted and discarded. read accesses are ignored (master abort). 0cd cache disable. when set to 1, accesses are marked as non-coherent. when cleared to 0, accesses are marked as coherent.
amd geode? lx processors data book 593 geodelink? pci bridge register descriptions 33234h 6.16.2.14 glpci memory region 5 configuration (glpci_r5) msr address 5000201dh ty p e r / w reset value 00000000_00000000h glpci_r5 register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 top rsvd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base rsvd en rsvd pf wc rsvd wp dd cd glpci_r5 bit descriptions bit name description 63:44 top top of region. 4 kb granularity, inclusive. 43:32 rsvd (ro) reserved (read only). reserved for future use. 31:12 base base of region. 4 kb granularity, inclusive. 11:9 rsvd (ro) reserved (read only). reserved for future use. 8en region enable. set to 1 to enable access to this region. 7:6 rsvd (ro) reserved (read only). reserved for future use. 5pf prefetchable. reads to this region have no side-effects. 4wc write combine. writes to this region may be combined. 3 rsvd (ro) reserved (read only). reserved for future use. 2wp write protect. when set to 1, only read accesse s are allowed. write accesses are ignored (master abort). 1dd discard data. when set to 1, write access are accepted and discarded. read accesses are ignored (master abort). 0cd cache disable. when set to 1, accesses are marked as non-coherent. when cleared to 0, accesses are marked as coherent.
594 amd geode? lx processors data book geodelink? pci bridge register descriptions 33234h 6.16.2.15 glpci external msr access configuration (glpci ext_msr) note: msr accesses addressed to port 0 are handled directly by the glpci module. msr address 5000201eh ty p e r / w reset value 00000000_00000000h glpci_ext_msr register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 rsvd func-7 device-7 func-6 device-6 func-5 device-5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 func-4 device-4 func-3 device-3 func-2 device-2 func-1 device-1 glpci_ext_msr bit descriptions bit name description 63:56 rsvd (ro) reserved (read only). reserved for future use. 55:53 func-7 function number 7. pci function number to use for msr accesses addressed to port 7. 52:48 device-7 device number 7. pci device number to use for msr accesses addressed to port 7. 47:45 func-6 function number 6. pci function number to use for msr accesses addressed to port 6. 44:40 device-6 device number 6. pci device number to use for msr accesses addressed to port 6. 39:37 func-5 function number 5. pci function number to use for msr accesses addressed to port 5. 36:32 device-5 device number 5. pci device number to use for msr accesses addressed to port 5. 31:29 func-4 function number 4. pci function number to use for msr accesses addressed to port 4. 28:24 device-4 device number 4. pci device number to use for msr accesses addressed to port 4. 23:21 func-3 function number 3. pci function number to use for msr accesses addressed to port 3. 20:16 device-3 device number 3. pci device number to use for msr accesses addressed to port 3. 15:13 func-2 function number 2. pci function number to use for msr accesses addressed to port 2. 12:8 device-2 device number 2. pci device number to use for msr accesses addressed to port 2. 7:5 func-1 function number 1. pci function number to use for msr accesses addressed to port 1. 4:0 device-1 device number 1. pci device number to use for msr accesses addressed to port 1.
amd geode? lx processors data book 595 geodelink? pci bridge register descriptions 33234h 6.16.2.16 glpci spare msr address 5000201fh ty p e r / w reset value 00000000_00000003h glpci spare 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 spare 313029282726252423222120191817161514131211109876543210 spare rsvd ailto ppd ppc mpc mme nse supo glpci spare bit descriptions bit name description 63:10 spare spare bits. extra bits available for future use. these bits may be set and cleared, but do not control anything. 9:7 rsvd reserved. write as read. 6ailto alternate initial latency timeout. enables alternate initial latency timeout values to be configured via ilto (msr 50002010h[41:40]). 5 ppd post pio data. enables posting of i/o writes to addresses: 170h and 1f0h. 4 ppc post pio control. enables posting of i/o writes to addresses: 171h, 172h, 173h, 174h, 175h, 176h, 177h, 1f 1h, 1f2h, 1f3h, 1f4h , 1f5h, 1f6h and 1f7h. 3mpc maximum posted count. controls the maximum number of pio i/o writes that may be posted in the glpci. when cleared, one i/o write may be posted. when set, two i/o writes may be posted. 2mme mask external msr exceptions. set to 1 to force the gliu synchronous exception flag to be cleared for all external msr transactions. 1nse no synchronous exceptions. controls when out-bound read data is written into the obrd fifo. when this bit is cleared. the glpci pipelines the writing of all out-bound read data into the fifo. this allows pci transaction status to be sampled and included synchronously with the read data. when this bi t is cleared, the glpci only pipelines read data for external msr accesses and i/o read of the configuration data port (0cfch). 0supo strict up-stream ordering. controls how out-bound reads get sorted with in-bound writes. when this bit is set the ordering rules are strictly applied; meaning that all gliu write responses associated with a in-bound pci write transaction must complete before data from a subsequent out-bound pci read ma y be placed onto the gliu. when this bit is cleared the out-bound read data may be plac ed onto the gliu after the in-bound write data has been placed onto the gliu.
596 amd geode? lx processors data book geodelink? pci bridge register descriptions 33234h 6.16.2.17 glpci general pu rpose i/o (glpci_gpio) msr address 50002020h ty p e r / w reset value 00000000_00000000h glpci_gpio register map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 msw rsvd sampdiv 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd oe2 oe1 oe0 rsvd out2 out1 out0 rsvd in2 in1 in0 glpci_gpio register bit descriptions bit name description 63 msw most significant word enable. must be set on writes to alter sampdiv (bits [47:32]). when cleared, the sampdiv field will not be updated. when set, the sampdiv field will be written. 62:48 rsvd (ro) reserved (read only). reserved for future use. 47:32 sampdiv sample divider. controls the frequency of sampling input data fed into each filter. with a value of zero, each input is sampled on every pci clock edge. with a value of 1, each input is sampled every other clock edge. with a value of 2, it is sampled every third clock edge, and so on. 31:19 rsvd (ro) reserved (read only). reserved for future use. 18 oe2 output enable 2. output enable for gnt2# pin. 17 oe1 output enable 1. output enable for req1# pin. 16 oe0 output enable 0. output enable for gnt1# pin. 15:11 rsvd (ro) reserved (read only). reserved for future use. 10 out2 output 2. output for gnt2# pin. 9out1 output 1. output for req1# pin. 8out0 output 0. output for gnt1# pin. 7:3 rsvd (ro) reserved (read only). reserved for future use. 2in2 (ro) input 2 (read only). filtered input from gnt2# pin. 1in1 (ro) input 1 (read only). filtered input from req1# pin. 0in0 (ro) input 0 (read only). filtered input from gnt1# pin.
amd geode? lx processors data book 597 7 electrical specifications 33234h 7.0 electrical specifications this section provides information on electrical connections, absolute maximum ratings, operating conditions, and dc/ac characteristics for the amd geode? lx processor. all voltage values in the elec trical specifications are with respect to v ss unless otherwise noted. 7.1 electrical connections 7.1.1 pwr/gnd connections and decoupling testing and operating the amd geode lx processor requires the use of standard high frequency techniques to reduce parasitic effects. when using this device, the effects can be minimized by filtering the dc power leads with low- inductance decoupling capacitors, using low-impedance wiring, and by connecting all v core, v io , v mem , and ana- log balls to the appropriate voltage levels. 7.1.2 nc-design ated balls balls designated as nc (no connection) should be left dis- connected. connecting an nc ball to a pull-up/-down resis- tor, or an active signal could cause unexpected results and possible circuit malfunctions. 7.1.3 unused inputs all inputs not used by the system designer should be kept at either ground or v io . to prevent possible spurious opera- tion. for active-high inputs to ground through a 20-k (10%) pull-down resistor and active-low inputs to v io through a 20-k (10%) pull-up resistor can be used if desired. 7.2 absolute maximum ratings table 7-1 lists absolute maximum ratings for the amd geode lx processor. stresses beyond the listed ratings may cause permanent damage to the device. exposure to conditions beyond these limits may (1) reduce device reliability and (2) result in premature failure even when there is no immedi- ately apparent sign of failure. prolonged exposure to condi- tions at or near the absolute maximum ratings may also result in reduced useful life and reliability. these are stress ratings only and do not imply t hat operation under any con- ditions other than those listed in table 7-2 "operating con- ditions" on page 598 is possible. table 7-1. absolute maximum ratings symbol parameter min max unit comments t storage storage temperature -65 150 c no bias v core core supply voltage 1.5 v v io i/o supply voltage 3.0 3.6 v also applies to v ca , v ma , v va , and v dac v mem memory voltage 3.6 v v max voltage on any pin -0.5 3.8 v except hsync, vsync voltage on hsync, vsync -0.5 5.5 v esd - human body model 2000 v esd - machine model 200 v
598 amd geode? lx processors data book electrical specifications 33234h 7.3 operating conditions table 7-2 lists the operating conditions for the amd geode lx processor. table 7-2. operating conditions symbol parameter (note 1) note 1. the amd geode lx 900@1.5w processor operates at 600 mhz, the amd geode lx 800@0.9w processor oper- ates at 500 mhz, the amd geod e lx 700@0.8w processor operates at 433 mhz and the amd geode lx 600@.07w processor operates at 366 mhz. model numbers reflect performance as described here: http://www.amd.com/connectivi tysolutions/geodelxbenchmark . min typ max unit comments tc operating case temperature lx 900@1.5w 080c operating case temperature lx 800@0.9w 0 85 c see section a.1 "order infor- mation" for applicable opn. -40 85 c operating case temperature lx 700@0.8w lx 600@0.7w 085c vcore core supply voltage lx 900@1.5w 1.36 1.40 1.44 v filtered version of this supply also supplies pll power. note 2 note 2. this parameter is calculated as nominal 3%. core supply voltage lx 800@0.9w 1.21 1.25 1.29 v core supply voltage lx 700@0.8w lx 600@0.7w 1.16 1.20 1.24 v vio i/o supply voltage 3.14 3.3 3.46 v filtered version of this supply also supplies dac power. note 3 vva video pll supply voltage 3.14 3.30 3.46 v filtered version of vio. note 3 vma memory pll supply voltage 3.14 3.30 3.46 v vca cpu pll supply voltage 3.14 3.30 3.46 v vdac dac pll supply voltage 3.14 3.30 3.46 v vmem ddr (2.6v sstl) lx 900@1.5w, lx 800@0.9w 2.47 2.60 2.73 v note 3 ddr (2.5v sstl) lx 700@0.8w 2.38 2.50 2.63 v ddr2 (1.9v) lx 900@1.5w, lx 800@0.9w lx 700@0.8w 1.81 1.90 2.00 v ddr2 (1.8v) lx 600@0.7w 1.71 1.80 1.89 v mvref ddr lx 900@1.5w, lx 800@0.9w 1.23 1.30 1.37 v note 3, note 4 note 3. this parameter is calculated as nominal 5%. note 4. mvref = 1/2 v mem . ddr lx 700@0.8w 1.19 1.25 1.31 v ddr2 lx 900@1.5w, lx 800@0.9w lx 700@0.8w 0.90 0.95 1.0 ddr2 (1.8v) lx 600@0.7w 0.86 0.90 0.95
amd geode? lx processors data book 599 electrical specifications 33234h 7.4 dc current dc current is not a simple measurement. three of the amd geode lx processor?s power states (on, active idle, and sleep) were selected for measurement. for the on power state measured, two functional characteristics (typi- cal average and absolute maximum) are used to deter- mine how much current the processor requires. 7.4.1 power state parameter definitions the dc current tables in this section list core and i/o cur- rent for three of the power states. ?on (s0/c0) : all internal and external clocks with respect to the amd geode lx processor are running and all functional blocks (cpu core, memory controller, display controller, etc.) are actively generating cycles. this is equivalent to the acpi specification?s ?s0/c0? state. ? active idle (s0/c1) : the cpu core has been halted and all other functional blocks (including the display controller for refreshing the display) are actively gener- ating cycles. this state is entered when a hlt instruc- tion is executed by the cpu core. from a user?s perspective, this state is indistinguishable from the on state and is equivalent to the acpi specification?s ?s0/c1? state. ? sleep (s1) : this is the lowest power state the amd geode lx processor can be in with voltage still applied to the device?s core and i/o supply pins. this is equivalent to the acpi s pecification?s ?s1? state. all measurements were taken at 25c ambient air. 7.4.2 definition and measurement techniques of current parameters the following two parameters describe the amd geode lx processor current while in the on state: typical average typical average (typ avg) indicates the average current used by the amd geode lx processor while in the on state, with no active power management. this measure- ment is comprised of two components: winbench ? 99 business graphics test and active idle power measure- ments. winbench 99 represents a maximum typical state as it simulates a knowledgeable worker?s typical day com- pressed into the shortest period of time possible. since it is not possible for someone to operate as fast as the bench- mark, the resulting power from the benchmark is averaged with active idle in an 80/20 ratio, with 80% of the time being in the windows ? xp idle state and 20% of the time running applications. this results in a typical average power result. for each voltage, power is measured at one second inter- vals. the measurements are then averaged together to produce the final number. the crt resolution is 1024x768x32 bpp, at 85 hz refresh and the tft resolution is 1024x768 x16 bpp at 60 hz refresh. this number is pro- vided for reference only since it can vary depending on the usage model of the system. thermal design power absolute maximum and thermal design power (tdp) indi- cates the maximum average current used by the amd geode lx processor. this is measured with the volt- ages at maximum. an internally-developed amd applica- tion called pathological power measurement application causes the amd geode lx processor to consume the maximum amount of power for the core and i/o rails, while winbench 99 business graphics test causes the amd geode lx processor to consume maximum power on the memory rail. all tests were run at the maximum sup- ported resolution of 1920x1440x32 bpp at 72 hz refresh for the crt and 1600x1200x16 bpp at 60 hz refresh for tft. this test does not guarantee maximum current. there may be pathological applications that result in higher measured currents. tdp is a function of all power contributors at maximum. applications that do not us e the crt or tft output will have a somewhat lower tdp. operating the memory sub- system at a lower frequency will also lower tdp. specific software applications may place lower compute demands on the cpu, which lowers the tdp as well. if needed, it is up to the system designer to determine tdp for systems that operate with conditions that are different then those specified, however, the tdp specified is the maximum. active idle active idle power is measured at the windows xp idle state when the monitor is still turned on. during this state the ?bliss? background is used. the crt resolution is 1024x768x32 bpp, at 85 hz refresh and 1024x768 x16 bpp at 60 hz refresh is used for tft. this number is provided for reference only since it can vary depending on the back- ground image and processes running on the system. sleep the sleep power state is achieved by forcing the system into a ?s1? state as defined by the acpi specification. 7.4.3 dc current measurements tables 7-3, 7-4, and 7-5 show the dc current measure- ments of the amd geode lx processor family. the proces- sor supports crt or tft displays. the crt dacs require current; while the tft interface, even though it has no dac to power, also draws current while it is active. therefore, the crt dacs and the tft interface currents are specified in separate tables.
600 amd geode? lx processors data book electrical specifications 33234h the data bus on the ddr sdram has a low voltage swing when actively terminated (ter minated topology). the termi- nated topology supports higher data transfer rates and is less constrained, but it consumes more power. many designs should be able to operate reliably without active termination (unterminated topology). the design con- straints are smaller memory subsystems and tight control on routing. see the application note, amd geode? lx processor and cs5535/cs5536 companion device layout recommendations (publication id #32739), for more infor- mation. when series termination resistors are used, as specified in the amd geode? lx processor and cs5535/cs5536 companion device layout recommendations , the actual power provided by the v memlx supply is split between the processor and the series and parallel termination (see fig- ure 7-1). therefore, it is impossible to specify the power used by the processor?s me mory subsystem with one hun- dred percent accuracy. a conservative estimate, is that 32.5% of the power is consumed by the processor and 67.5% by the termination resistors. see the amd geode? lx processor determining memory interface i/o power consumption document (publication id #40554) for the detailed analysis. this number is used for the results in dc current tables (tables 7-3, 7-4, and 7-5). figure 7-1. v memlx power split v memlx v memdimm v tt connector or device mem lx r p1 r p2 r s table 7-3. amd geode lx 900@1.5w processor dc currents lx 900@1.5w (600 mhz), no eeprom, v core = 1.4v, tdp t = 5.3w, tdp u = 5.1w (note 1) symbol parameter typ avg max unit comments i cc3on - crt display power state: on (s0/c0) 85 100 ma i cc3on - tft display 37 45 i coreon 1420 3140 i memon - terminated 150 165 note 2, note 3 i memon - unterminated 90 100 note 3 i memddr2on 80 95 i cc3idle - crt display power state: active idle (s0/c1) 85 ma i cc3idle - tft display 37 i coreidle 1250 i memidle - terminated 150 note 2, note 3 i memidle - unterminated 80 note 3 i cc3slp - crt display power state: sleep (s1) 4ma i cc3slp - tft display 4 i coreslp 600 i memslp - terminated 100 note 2, note 3 i memslp - unterminated 35 note 3 note 1. the amd geode lx 900@1.5w processor operates at 600 mhz. model numbers refl ect performance as described here: http://www.amd.com/connectivi tysolutions/geodelxbenchmark . t = terminated and u = unterminated. note 2. calculations are based on a 32.5/67.5 split between v memlx used by the amd geode lx processor and series termination resistors. see section 7.4.3 on page 599 for more details. note 3. v mem is 2.6v for the lx 900@1.5w processor.
amd geode? lx processors data book 601 electrical specifications 33234h table 7-4. amd geode lx 800@0.9w processor dc currents lx 800@0.9w (500 mhz), no eeprom, v core = 1.25v, tdp t = 3.8w, tdp u = 3.6w (note 1) symbol parameter typ avg max unit comments i cc3on - crt display power state: on (s0/c0) 85 100 ma i cc3on - tft display 37 45 i coreon 1010 2290 i memon - terminated 150 165 note 2, note 3 i memon - unterminated 90 100 note 3 i memddr2on 80 95 i cc3idle - crt display power state: active idle (s0/c1) 85 ma i cc3idle - tft display 37 i coreidle 885 i memidle - terminated 150 note 2, note 3 i memidle - unterminated 80 note 3 i cc3slp - crt display power state: sleep (s1) 4ma i cc3slp - tft display 4 i coreslp 225 i memslp - terminated 100 note 2, note 3 i memslp - unterminated 35 note 3 note 1. the amd geode lx 800@0.9w processor operates at 500 mhz. model numbers refl ect performance as described here: http://www.amd.com/connectivi tysolutions/geodelxbenchmark . t = terminated and u = unterminated. note 2. calculations are based on a 32.5/67.5 split between v memlx used by the amd geode lx processor and series termination resistors. see section 7.4.3 on page 599 for more details. note 3. v mem is 2.6v for the lx 800@0.9w processor.
602 amd geode? lx processors data book electrical specifications 33234h table 7-5. amd geode lx 700@0.8w processor dc currents lx 700@0.8w (433 mhz), no eeprom or eeprom, v core = 1.20v, tdp t = 3.2w, tdp u = 3.1w (note 1) symbol parameter typ avg max unit comments i cc3on - crt display power state: on (s0/c0) 85 100 ma i cc3on - tft display 37 45 i coreon 650 1945 i memon - terminated 145 155 note 2, note 3 i memon - unterminated 85 95 note 3 i memddr2on 75 90 i cc3idle - crt display power state: active idle (s0/c1) 85 ma i cc3idle - tft display 37 i coreidle 555 i memidle - terminated 145 note 2, note 3 i memidle - unterminated 75 note 3 i cc3slp - crt display power state: sleep (s1) 4ma i cc3slp - tft display 4 i coreslp 195 i memslp - terminated 95 note 2, note 3 i memslp - unterminated 30 note 3 note 1. the amd geode lx 700@0.8w processor operates at 433 mhz. model numbers refl ect performance as described here: http://www.amd.com/connectivi tysolutions/geodelxbenchmark . t = terminated and u = unterminated. note 2. calculations are based on a 32.5/67.5 split between v memlx used by the amd geode lx processor and series termination resistors. see section 7.4.3 on page 599 for more details. note 3. v mem is 2.5v for the lx 700@0.8w processor.
amd geode? lx processors data book 603 electrical specifications 33234h table 7-6. amd geode lx 600@0.7w processor dc currents lx 600@0.7w (366 mhz), no eeprom, v core = 1.20v, tdp t = 2.9w, tdp u = 2.8w (note 1) symbol parameter typ avg max unit comments i cc3on - crt display power state: on (s0/c0) 85 100 ma i cc3on - tft display 37 45 i coreon 600 1765 i memon - terminated 140 150 note 2, note 3 i memon - unterminated 80 90 note 3 i memddr2on 70 85 i cc3idle - crt display power state: active idle (s0/c1) 85 ma i cc3idle - tft display 37 i coreidle 510 i memidle - terminated 140 note 2, note 3 i memidle - unterminated 70 note 3 i cc3slp - crt display power state: sleep (s1) 4ma i cc3slp - tft display 4 i coreslp 185 i memslp - terminated 90 note 2, note 3 i memslp - unterminated 30 note 3 note 1. the amd geode lx 600@0.7w processor operates at 3 66 mhz. model numbers reflec t performance as described here: http://www.amd.com/connectivi tysolutions/geodelxbenchmark . t = terminated and u = unterminated. note 2. calculations are based on a 32.5/67.5 split between v memlx used by the amd geode lx processor and series termination resistors. see section 7.4.3 on page 599 for more details. note 3. v mem is 2.5v for the lx 600@0.7w processor.
604 amd geode? lx processors data book electrical specifications 33234h 7.5 dc characteristics all dc parameters and current measurements in this section were measured under t he operating conditions listed in table 7-2 "operating conditions", unless otherwise noted. the sig nals associated with the seven signal buffer types on the amd geode lx processor, are shown table 3-5 "ball assignments - sorted by ball number" on page 26. table 7-7. dc characteristics symbol parameter min max units comments v il low level input voltage, note 1 pci -0.5 0.3*v io v 24/q3 -0.5 0.8 v 24/q5 -0.5 0.8 v 24/q7 -0.5 0.8 v 5v -0.5 0.8 v ddr -0.3 mvref-0.2 v ddrclk n/a n/a v ih high level input voltage, note 1 pci 0.5*v io v io +0.5 v 24/q3 2.0 v io +0.5 v 24/q5 2.0 v io +0.5 v 24/q7 2.0 v io +0.5 v 5v 2.0 5.5v v overvoltage tolerant ddr mvref+0.2 v mem +0.3 v ddrclk n/a n/a v ol low level output voltage, note 1 pci 0.1*v io v 24/q3 0.4 v 24/q5 0.4 v 24/q7 0.4 v 5v 0.4 v ddr 0.35 v ddrclk mvref-0.4 v v oh high level output voltage, note 1 pci 0.9*vio v 24/q3 2.4 v 24/q5 2.4 v 24/q7 2.4 v 5v 2.4 v ddr v mem -0.43 v ddrclk mvref+0.4 v
amd geode? lx processors data book 605 electrical specifications 33234h i leak input leakage current including hi-z output leakage, note 1 pci -3.0 3.0 a 24/q3 -3.0 3.0 a 24/q5 -3.0 3.0 a 24/q7 -3.0 3.0 a 5v -3.0 3.0 a if v ih > v io , i leak max = 20 a ddr -3.0 3.0 a ddrclk -5.0 5.0 a i pu/pd weak pull-up/down current, note 1 pci n/a --- 24/q3 50 150 a these pull-downs are only enabled during reset or power sequencing system behaviors. note 2. 24/q5 50 150 a 24/q7 50 150 a 5v 50 150 a ddr n/a --- ddrclk n/a --- i oh output high current, note 1 v o = v oh (min) pci -500 a 24/q3 -24.0 ma 24/q5 -24.0 ma 24/q7 -24.0 ma note 2 5v -16.0 ma ddr (ba[1:0], ma[13:0]) -15.2 ma i oh min = -11 ma with half- drive set for pad ddr (dq[63:0], cke[1:0], cs[3:0]#, ras[1:0]#, cas[1:0]#, we[1:0]#, dqs[7:0], dqm[7:0], tla[1:0] -11 ma i oh min = -8 ma with quar- ter-drive set for pad ddrclk -10.0 ma table 7-7. dc characteristics (continued) symbol parameter min max units comments
606 amd geode? lx processors data book electrical specifications 33234h i ol output low current, note 1 v o = v ol (max) pci 1500 a 24/q3 24.0 ma 24/q5 24.0 ma 24/q7 24.0 ma 5v 16.0 ma ddr (ba[1:0], ma[13:0]) 15.2 ma i ol min = 11 ma with half- drive set for pad ddr (dq[63:0], cke[1:0], cs[3:0]#, ras[1:0]#, cas[1:0]#, we[1:0]#, dqs[7:0], dqm[7:0], tla[1:0] 11 ma i ol min = 8 ma with quarter- drive set for pad ddrclk 10.0 ma c io input and output capacitance, note 1 pci 8.0 pf 24/q3 5.0 pf 24/q5 5.0 pf 24/q7 5.0 pf 5v 5.0 pf ddr 8.0 pf ddrclk 15.0 pf note 1. refer to the table 3-5 "ball assignments - sorted by ball number" on page 26 for package signal names associated with each buffer type. note 2. the sda pad is designed to use a pull-up on-chip functionally, hence i oh is not used to drive high, i leak is instead table 7-7. dc characteristics (continued) symbol parameter min max units comments
amd geode? lx processors data book 607 electrical specifications 33234h 7.6 ac characteristics the following tables list the ac characteristics including output delays, input setup requirements, input hold require- ments, and output float delays. the rising-clock-edge refer- ence level v ref , and other reference levels are shown in figure 7-2. input or output signals must cross these levels dur- ing testing. input setup and hold times are specified minimums that define the smallest acceptable sampling window for which a synchronous input signal must be stable for correct opera- tion. all ac tests are performed at the following parameters using the timing diagram shown in figure 7-2 unless other- wise specified: v core : 1.14v to 1.26v (1.2v nominal) v io : 3.14v to 3.46v (3.3v nominal) v mem: 2.5v sstl mvref: ddr:1.25v t c :0 o c to 85 o c r l :50 c l :50 pf while most minimum, maximum, and typical ac character- istics are only shown as a single value, they are tested and guaranteed across the entire processor core voltage range of 1.14v to 1.26v. ac charac teristics that are affected sig- nificantly by the core voltage or speed grade are docu- mented accordingly. all ac timing measurements are taken at 50% crossing points for both input times and output times. figure 7-2. drive level and measurement points for switching characteristics clk outputs inputs v ihd v ild v ref valid input valid output n+1 valid output n v ref v ref v ild v ihd min max legend: a = maximum output or float delay specification b = minimum output or float delay specification c = minimum input setup specification d = minimum input hold specification t x b a cd
608 amd geode? lx processors data book electrical specifications 33234h figure 7-3. drive level and measurement points for switching characteristics table 7-8. system interface signals symbol parameter min max unit comments t ck sysref cycle time 15.0 inf ns 66 mhz t ch sysref high time 6.0 ns 40% t ck t cl sysref low time 6.0 ns 40% t ck t su1 reset# setup time to sysref 3 ns note 1 t h1 reset# hold time from sysref 1 ns note 1 t su2 cis setup time to sysref 3.0 ns t h2 cis hold time from sysref 0 ns t val1 irq13 valid delay time from sysref 2.0 6.0 ns t val2 suspa# valid delay time from sysref 2.0 6.0 ns t on v io and v mem power on after v core 0100msnote 2 t mvon mvref power on after v mem 0100ms t rstx reset active time after sysref clock stable 100 us for pll lock t z output drive delay after reset# released 20 ns note 1. reset# is asynchronous. the setup/hold times stated are for testing purposes that require sequential repeatabil- ity. note 2. for proper powerup of drgb and flat panel controls, v io must power up after v core . otherwise, v core can be last. sysref outputs inputs 50% valid input valid output n+1 valid output n 50% 50% t val1,2 min t val1,2 max t su1,2 t h1,2 t ck t ch t cl
amd geode? lx processors data book 609 electrical specifications 33234h figure 7-4. power up sequencing figure 7-5. drive level and measurement points for switching characteristics v core v io ,v mem reset# sysref sysref cycle time not to scale with other delays in this figure. outputs t on t rstx t z mvref t mvon table 7-9. pci interface signals symbol parameter min max unit comments t su1 input setup time to sysref (ad[31:0], devsel#,gnt[ 2:0]#, irdy#, par, stop#, trdy#) 3.0 ns t su2 req[2:0]# input setup time to sysref 4.5 ns t h input hold time from sysr ef for all pci inputs (stop#) (devsel#, frame#, gnt[2:0#, irdy#, par, trdy#, req[2:0]#, stop#) 0nsnote 1 t val1 bused signals valid de lay time from sysref (ad[31:0]) 2.0 6.0 ns note 2 t val2 gnt[2:0]# valid delay time from sysref 2.0 5.5 ns note 2 note 1. the gnt[2:0]#, irq13, suspa#, pw0, and pw1 sig nals are only inputs during reset# active. they must be sta- ble between five and two pci cl ocks before reset# inactive. note 2. output delay includes tristate-to-vali d transitions and valid-to-tristate timing. sysref outputs inputs 50% valid input valid output n+1 valid output n 50% 50% t val1,2 min t val1,2 max t su1,2 t h1,2
610 amd geode? lx processors data book electrical specifications 33234h figure 7-6. drive level and measurement points for switching characteristics table 7-10. vip interface signals symbol parameter min max unit comments t ck vipclk period 12.5 ns 80 mhz t ch vipclk high time 3.0 ns 45% t ck t cl vipclk low time 3.0 ns 45% t ck t val vip_sync output valid delay time from vipclk 1.0 4.0 ns t su1 vid[7:0] input setup time to vipclk 2.0 ns t h1 vid[7:0] input hold time from vipclk. 0.2 ns vipclk outputs inputs 50% valid input valid output n+1 valid output n 50% 50% t val1,2 min t val1,2 max t su1,2 t h1,2 t ck t ch t cl
amd geode? lx processors data book 611 electrical specifications 33234h figure 7-7. drive level and measurement points for switching characteristics table 7-11. flat panel interface signals symbol parameter min max unit comments t ck dotclk period 6.0 ns 166 mhz t ch dotclk high time 2.7 ns 45% t ck t cl dotclk low time 2.7 ns 45% t ck dotclk long term output jitter 15% t ck note 1 t val1 drgb[31:0] output valid delay time from rising edge of dotclk 0.5 3.0 ns t val2 dispen, ldemod output valid delay time from rising edge of dotclk 0.5 3.0 ns t val3 hsync, vsync output valid delay time from ris- ing edge of dotclk 0.5 3.0 ns note 1. measured as per vesa requirements. the jitter is ob served at its worst case point on a scan line after hsync triggers up to and including the next hsync trigger. dotclk outputs 50% valid output n+1 valid output n 50% t val1,2,3 min t val1,2,3 max t ck
612 amd geode? lx processors data book electrical specifications 33234h table 7-12. crt interface signals symbol parameter min max unit comments t ck dotclk period 2.8 ns 350 mhz t ch dotclk high time 1.2 ns 45% t ck t cl dotclk low time 1.2 ns 45% t ck dotclk long term output jitter 15% t ck note 1 t skew skew between red, green, blue output valid 0 0.6 ns between any two signals note 2 note 1. measured as per vesa requirements. the jitter is ob served at its worst case point on a scan line after hsync triggers up to and including the next hsync trigger. note 2. hsync and vsync for crt timing are generated from t he same on-chip clock that is used to generate the red, green, and blue signals. table 7-13. crt display recommended operating conditions symbol parameter min typ max units comments v dac power supply connected to dav dd 3.14 3.3 3.46 v r l output load red, green and blue 37.5 note 1 one each signal. i out output current red, green and blue 21 ma one each signal. r set value of the full-scale adjust resistor connected to drset 1.2k this resistor should have a 1% tolerance. vext ref external voltage reference con- nected to the dvref pin 1.235 v note 1. there is a 75 resistor on the motherboard and a 75 resistor in the crt monitor to create the effective 37.5 typical resistance.
amd geode? lx processors data book 613 electrical specifications 33234h table 7-14. crt display analog (dac) characteristics symbol parameter min typ max units comments (note 1) v os output voltage saturation limit 1.25 v i ovar output current 18.67 ma achieves 700 mv on 37.5 inl integral linearity error +/-1 lsb dnl differential linearity error +/-1 lsb t fs full scale settling time 2.5 ns note 2 -- dac-to-dac matching 1 4 % -- analog power supply rejection 45 db @ 1 khz t rise output rise time 0.5 1.25 ns note 3 and note 4 t fall output fall time 0.5 1.25 ns note 3 and note 4 note 1. all tests, unless othe rwise specified, are at v io = 3.14v to 3.46v, t c = 0c to 85c (or -40c to 85c if lx 800@0.9w industrial temperature range part), and c l = 50 pf. note 2. full-scale transition time is measured from 50% of full- scale transition until output remaining within 1lsb of target. note 3. timing measurements are made with a 75 doubly-terminated load, with vext ref = 1.235v and r set = 1.2 k . note 4. 10% to 90% of full-scale transition.
614 amd geode? lx processors data book electrical specifications 33234h table 7-15. memory (ddr) interface signals symbol (note 1) parameter min max unit comments t ck sdclk[5:0]p, sdclk[5: 0]n period 5.0 ns note 2 t ch sdclk[5:0]p, sdclk[5:0] n high time 2.4 ns 48% t ck t cl sdclk[5:0]p, sdclk[5:0] n low time 2.4 ns 48% t ck t skew1 sdclk[n]p to sdclk[n]n skew (n=0..5) 0.1 ns guaranteed by design t del1 sdclk[5:1]p, sdclk[5: 0]n edge delay from sdclk[0]p -0.2 0.2 ns note 2, note 3 dqs[7:0] input and output period 5.0 ns same as t ck t dqsck dqs[7:0] input delay rela tive to sdclk[5:0] -0.5 t ck -2 ns note 4 t del2 dqs[7:0] output edge delay from sdclk[5:0] -0.5 0.5 ns note 3 t rpre dqs input preamble before first dqs rising edge 0.25*t ck ns note 3 t rpst dqs input postamble after la st dqs rising edge 0.25*t ck note 3 t wpre dqs output write preamble valid time before sdclk[5:0] rising edge 0.5*t ck -0.4 0.5*t ck +1 ns t wpst dqs output write postamble after last dqs falling edge 0.75*t ck -0.4 0.75*t ck +1 ns t dqsqs dq[63:0] input setup time from dqs -0.25*t ck +0.5 ns note 3,note 5 t dqsqh dq[63:0] input hold time from dqs 0.25*t ck +0.5 ns note 3, note 5 t val1 dq[63:0], dqm[7:0] output data valid delay time from dqs rising or falling edge 0.25*t ck -0.4 0.25*t ck +0.4 ns note 3, t val2 ma[12:0], ba[1:0], cas[ 1:0]#, ras[1:0]#, cke[1:0], cs[3:0]#, we[1:0] output valid delay time from sdclk[5:0] 1.1 3.0 ns note 3, note 4 note 1. refer to figure 7-8 "ddr write timing measurem ent points" on page 615 and figure 7-9 "ddr read timing mea- surement points" on page 616. note 2. the sdclkp and sdclkn clocks are invers ions of each other (differential clocking). note 3. these parameters guarantee device timing, but they may be tested to a looser value to allow for tester uncertain- ties. devices that meet the loosened tester val ues meet specs when correlated with lab measurements. note 4. t val2 and t dqsck timings are achieved for different dimm lo adings by proper initial settings of the glcp_delay_controls msr. typical tester result s with clock and address loaded equally and no pro- grammed delay for address are 0 ns for t val2 . note 5. the dq timing relative to dqs are on a per-byte basis only. dq[7:0] and dqm[0] should be measured against dqs[0], dq[15:8] and dq m[1] should be measured against dqs[1], etc.
amd geode? lx processors data book 615 electrical specifications 33234h figure 7-8. ddr write timing measurement points sdclk[5:1]p non-dq outputs v ref valid output n+1 valid output n v ref t val2 min t val2 max v ihd v ild v ref dqs outputs dqs v ihd v ild v ref dq outputs dq n+1 dq n v ref dq n+2 sdclk[5:0]n v ref t skew1 t skew1 t del2 sdclk0p v ref t del1 t val1 max t val1 min
616 amd geode? lx processors data book electrical specifications 33234h figure 7-9. ddr read timing measurement points dq inputs v ref dq t v ref dq t-1 sdclk0 dqs ?late? input v ref other dqs input v ref dq t+1 dq t+2 dqs[n] input v ref t skew2 t dqsck max dqs ?early? input v ref t dqsck min t skew2 -t dqsqs t dqsqh associated with dqs[n]
amd geode? lx processors data book 617 electrical specifications 33234h table 7-16. jtag interface signals symbol parameter min max unit comments tclk period 15 ns note 1 tclk high time 4 ns 40% period tclk low time 4 ns 40% period tdi, tms setup time to tclk rising edge 1.5 ns tms hold time from tclk rising edge 3.0 ns tdi hold time from tclk rising edge - boundary scan 3.0 ns tdi hold time from tclk rising edge - functional 2*t glbus ns hold for 2 glbus clocks tdo output valid delay time from tclk falling edge when running boundary scan test 3.0 70.0 ns tdo output valid delay time from tclk falling edge in normal functional mode 3.0 10.0 ns all chip i/o setup time to tclk rise - boundary scan 1.0 ns all chip i/o hold time from tclk rise - boundary scan 3ns all chip i/o output valid delay time from tclk falling edge - boundary scan test 2.0 70.0 ns note 1. tclk limited during functional mode to 100 mhz or 1/4 of the memory data frequency.
618 amd geode? lx processors data book electrical specifications 33234h
amd geode? lx processors data book 619 8 instruction set 33234h 8.0 instruction set this chapter provides the general instruction set format and detailed information on the amd geode? lx processor?s instructions/instruction encodings. the instruction set is divided into three categories: ? cpuid instruction set - listed in section 8.2 on page 627. ? processor core instruction set - listed in section 8.3 on page 633. ? mmx?, fpu, and amd 3dnow!? instruction sets (includi ng extensions) - listed in section 8.4 on page 658. in the above listed sections are tables that provide informat ion on the instruction encoding, and the instruction clock counts for each instruction. the clock count values for these tables are based on the following assumptions: 1) all clock counts refer to the internal processor core clock frequency. 2) the instruction has been prefetched, decoded, and is ready for execution. 3) any needed memory operands are in the cache in the last accessed way (i.e., way0, way1, way2, or way3). add two clocks if not in last accessed way. 4) no exceptions are detected during instruction execution. 5) if an effective address is calculated, it does not use two general register co mponents. one register, scaling, and a dis- placement value can be used within the clock count shown. however, if the effective address calculation uses a base register, an index register, and a displacement value, a cycle must be added to the count. 6) all clock counts assume an 8-byte span of 32-bit memory/io operands. 7) if instructions access a 32-bit operand not within an 8-byte bl ock, add one clock for read or write and add two clocks for read and write. 8) for non-cached memory accesses, add several clocks. cache miss accesses are approximately an additional 25 clocks, the exact number depends upon the cycle/operation running. 9) locked cycles are not cacheable. therefore, using the lock prefix with an instruction adds additional clocks as spec- ified in item 8 above. 8.1 general instr uction set format depending on the instruction, the amd geode lx processor core instructions follow the general instruction format shown in table 8-1. these instructions vary in length and can start at an y byte address. an instruction consists of one or more bytes that can include prefix bytes, at least one opcode byte, a mod r/m byte, an s-i-b byte, address displacement, and immedi- ate data. an instruction can be as short as one byte and as long as 15 bytes. if there are more than 15 bytes in the instruc- tion, a general protection fault (error code 0) is generated. the fields in the general instruction format at the byte leve l are summarized in table 8-2 on page 620 and detailed in the fol- lowing subsections. table 8-1. general instruction set format prefix (optional) opcode register and address mode specifier address displacement immediate data mod r/m byte s-i-b byte mod reg r/m ss index base 0 or more bytes 1 or 2 bytes 7:6 5:3 2:0 7:6 5:3 2 :0 0, 8, 16, or 32 bits 0, 8, 16, or 32 bits
620 amd geode? lx processors data book instruction set 33234h 8.1.1 prefix (optional) prefix bytes can be placed in front of any instruction to modi fy the operation of that instruction. wh en more than one prefix is used, the order is not impo rtant. there are five types of prefixes that can be used: 1) segment override explicitly specifies which segment register the instruction will use for effective address calculation. 2) address size switches between 16-bit and 32-bit addressing by selecting the non-default address size. 3) operand size switches between 16-bit and 32-bit o perand size by selecting the non-default operand size. 4) repeat is used with a string instruct ion to cause the instruction to be re peated for each element of the string. table 8-3 lists the encoding for di fferent types of prefix bytes. table 8-2. instruction fields field name description prefix (optional) prefix field(s): one or more optional fi elds that are used to spec ify segment register over- ride, address and operand size, repeat elements in string instruction, and lock# assertion. opcode opcode field: identifies instruction operation. mod address mode specifier: used with the r/m field to select addressing mode. reg general register specifier: uses reg, sre g3, or sreg2 encoding depending on opcode field. r/m address mode specifier: used with mod field to select addressing mode. ss scale factor: determines scaled-index address mode. index index: determines general register to be used as index register. base base: determines general register to be used as base register. address displacement displacement: determines address displacement. immediate data immediate data: immedi ate data operand used by instruction. table 8-3. instruction prefix summary prefix encoding description es: 26h override segment default, use es for memory operand. cs: 2eh override segment default, use cs for memory operand. ss: 36h override segment default, use ss for memory operand. ds: 3eh override segment default, use ds for memory operand. fs: 64h override segment default, use fs for memory operand. gs: 65h override segment default, use gs for memory operand. operand size 66h make operand size attribute the inverse of the default. address size 67h make address size attribute the inverse of the default. lock f0h assert lock# internal hardware signal. repne f2h repeat the following string instruction. rep/repe f3h repeat the following string instruction.
amd geode? lx processors data book 621 instruction set 33234h 8.1.2 opcode the opcode field specifies the operation to be performed by the instruction. the opcode field is either one or two bytes in length and may be further defined by additional bits in th e mod r/m byte. some operations have more than one opcode, each specifying a different form of the operation. certai n opcodes name instruction groups. for example, opcode 80h names a group of operations that have an immediate oper and and a register or memory operand. the reg field may appear in the second opcode byte or in the mod r/m byte. the opcode may contain w, d, s, and eee opcode fields , for example, as shown in table 8-26 on page 634. 8.1.2.1 w field (operand size) when used, the 1-bit w field selects the operand size during 16-bit and 32-bit data operations. see table 8-4. 8.1.2.2 d field (operand direction) when used, the 1-bit d field determines which operand is taken as the source operand and which operand is taken as the destination. see table 8-5. 8.1.2.3 s field (immedi ate data field size) when used, the 1-bit s field determines the si ze of the immediate data field. if the s bit is set, the immediate field of the opcode is 8 bits wide and is sign-extended to matc h the operand size of the opcode. see table 8-6. table 8-4. w field encoding w field operand size 16-bit data operations 32-bit data operations 0 8 bits 8 bits 1 16 bits 32 bits table 8-5. d field encoding d field direction of operation sou rce operand destination operand 0 register-to-register or register-to-memory reg mod r/m or mod ss-index-base 1 register-to-register or memory-to-register mod r/m or mod ss-index-base reg table 8-6. s field encoding s field immediate field size 8-bit operand size 16-bit oper and size 32-bit operand size 0 (or not present) 8 bits 16 bits 32 bits 1 8 bits 8 bits (sign-extended) 8 bits (sign-extended)
622 amd geode? lx processors data book instruction set 33234h 8.1.2.4 eee field (mov-instr uction register selection) the eee field (bits [5:3]) is used to select the control, debug, and test registers in the mov instructions. the type of regist er and base registers selected by the eee field are listed in table 8-7. the values shown in table 8-7 are the only valid encod- ings for the eee bits. 8.1.3 mod and r/m byte (memory addressing) the mod and r/m fields within the mod r/m byte select the type of memory addressing to be used. some instructions use a fixed addressing mode (e.g., push or pop) and therefore, thes e fields are not present. table 8-8 lists the addressing method when 16-bit addressing is used and a mod r/m byte is presen t. some mod r/m field encodings are dependent on the w field and are shown in table 8-9. table 8-7. eee field encoding eee field register type base register 000 control register cr0 010 control register cr2 011 control register cr3 100 control register cr4 000 debug register dr0 001 debug register dr1 010 debug register dr2 011 debug register dr3 110 debug register dr6 111 debug register dr7 000 test register tr0 001 test register tr1 010 test register tr2 011 test register tr3 100 test register tr4 101 test register tr5 110 test register tr6 111 test register tr7 table 8-8. mod r/m field encoding mod field r/m field 16-bit address mode with mod r/m byte (note 1) 32-bit address mode with mod r/m byte and no s-i-b byte present (note 1) 00 000 ds:[bx+si] ds:[eax] 00 001 ds:[bx+di] ds:[ecx] 00 010 ss:[bp+si] ds:[edx] 00 011 ss:[bp+di] ds:[ebx] 00 100 ds:[si] s-i-b is present (see table 8-15 on page 626) 00 101 ds:[di] ds:[d32] 00 110 ds:[d16] ds:[esi] 00 111 ds:[bx] ds:[edi]
amd geode? lx processors data book 623 instruction set 33234h 01 000 ds:[bx+si+d8] ds:[eax+d8] 01 001 ds:[bx+di+d8] ds:[ecx+d8] 01 010 ss:[bp+si+d8] ds:[edx+d8] 01 011 ss:[bp+di+d8] ds:[ebx+d8] 01 100 ds:[si+d8] s-i-b is present (see table 8-15 on page 626) 01 101 ds:[di+d8] ss:[ebp+d8] 01 110 ss:[bp+d8] ds:[esi+d8] 01 111 ds:[bx+d8] ds:[edi+d8] 10 000 ds:[bx+si+d16] ds:[eax+d32] 10 001 ds:[bx+di+d16] ds:[ecx+d32] 10 010 ss:[bp+si+d16] ds:[edx+d32] 10 011 ss:[bp+di+d16] ds:[ebx+d32] 10 100 ds:[si+d16] s-i-b is present (see table 8-15 on page 626) 10 101 ds:[di+d16] ss:[ebp+d32] 10 110 ss:[bp+d16] ds:[esi+d32] 10 111 ds:[bx+d16] ds:[edi+d32] 11 xxx see table 8-9. see table 8-9 note 1. d8 refers to 8-bit displacement, d16 refers to 16- bit displacement, and d32 refers to a 32-bit displacement. table 8-9. general registers selected by mod r/m fields and w field mod r/m 16-bit operation 32-bit operation w = 0 w = 1 w = 0 w = 1 11 000 al ax al eax 11 001 cl cx cl ecx 11 010 dl dx dl edx 11 011 bl bx bl ebx 11 100 ah sp ah esp 11 101 ch bp ch ebp 11 110 dh si dh esi 11 111 bh di bh edi table 8-8. mod r/m field encoding (continued) mod field r/m field 16-bit address mode with mod r/m byte (note 1) 32-bit address mode with mod r/m byte and no s-i-b byte present (note 1)
624 amd geode? lx processors data book instruction set 33234h 8.1.4 reg field the reg field (table 8-10) determines which general regist ers are to be used. the selected register is dependent on whether a 16-bit or 32-bit operation is current and on the status of the w bit. 8.1.4.1 sreg2 field (es, cs, ss, ds register selection) the sreg2 field (table 8-11) is a 2-bit field that allows one of the four 286-type segment registers to be specified. 8.1.4.2 sreg3 field (fs and gs segment register selection) the sreg3 field (table 8-12) is 3-bit field that is similar to th e sreg2 field, but allows use of the fs and gs segment registe rs. table 8-10. reg field reg 16-bit operation 32-bit operation w = 0 w = 1 w = 0 w = 1 000 al ax al eax 001 cl cx cl ecx 010 dl dx dl edx 011 bl bx bl ebx 100 ah sp ah esp 101 ch bp ch ebp 110 dh si dh esi 111 bh di bh edi table 8-11. sreg2 field encoding sreg2 field segment register selected 00 es 01 cs 10 ss 11 ds table 8-12. sreg3 field (fs and gs segment register selection) sreg3 field segment register selected 000 es 001 cs 010 ss 011 ds 100 fs 101 gs 110 undefined 111 undefined
amd geode? lx processors data book 625 instruction set 33234h 8.1.5 s-i-b byte (scale, indexing, base) the s-i-b fields provide scale factor, indexing, and a base field for address selection. the ss, index, and base fields are described next. 8.1.5.1 ss field (scale selection) the ss field (table 8-13) specifies the scale factor used in the offset mechanism for address calculation. the scale factor multiplies the index value to provide one of the co mponents used to calculate the offset address. 8.1.5.2 index field (index selection) the index field (table 8-14) specifies the index register used by the offset mechanism for of fset address calculation. when no index register is used (index field = 100), the ss value must be 00 or the effective address is undefined. table 8-13. ss field encoding ss field scale factor 00 x1 01 x2 01 x4 11 x8 table 8-14. index field encoding index field index register 000 eax 001 ecx 010 edx 011 ebx 100 none 101 ebp 110 esi 111 edi
626 amd geode? lx processors data book instruction set 33234h 8.1.5.3 base field (s-i-b present) in table 8-8 on page 622, the note ?s-i-b is present? for certain entries forces the use of the mod and base field as listed in table 8-15. the first two digits in the first column of table 8- 15 identify the mod bits in the mod r/m byte. the last three di gits in the second column of this table identify the base fields in the s-i-b byte. table 8-15. mod base field encoding mod field within mod/rm byte (bits[7:6]) base field within s-i-b byte (bits [2:0]) 32-bit address mode with mod r/m and s-i-b bytes present 00 000 ds:[eax+(scaled index)] 00 001 ds:[ecx+(scaled index)] 00 010 ds:[edx+(scaled index)] 00 011 ds:[ebx+(scaled index)] 00 100 ss:[esp+(scaled index)] 00 101 ds:[d32+(scaled index)] 00 110 ds:[esi+(scaled index)] 00 111 ds:[edi+(scaled index)] 01 000 ds:[eax+(scaled index)+d8] 01 001 ds:[ecx+(scaled index)+d8] 01 010 ds:[edx+(scaled index)+d8] 01 011 ds:[ebx+(scaled index)+d8] 01 100 ss:[esp+(scaled index)+d8] 01 101 ss:[ebp+(scaled index)+d8] 01 110 ds:[esi+(scaled index)+d8] 01 111 ds:[edi+(scaled index)+d8] 10 000 ds:[eax+(scaled index)+d32] 10 001 ds:[ecx+(scaled index)+d32] 10 010 ds:[edx+(scaled index)+d32] 10 011 ds:[ebx+(scaled index)+d32] 10 100 ss:[esp+(scaled index)+d32] 10 101 ss:[ebp+(scaled index)+d32] 10 110 ds:[esi+(scaled index)+d32] 10 111 ds:[edi+(scaled index)+d32]
amd geode? lx processors data book 627 instruction set 33234h 8.2 cpuid inst ruction set the cpuid instruction (opcode 0fa2) allows software to make processor inquiries as to the vendor, family, model, step- ping, features, and specific cache organization information. th e presence of support for the cpuid instruction is indicated by the ability to change the value of the id flag, bit 21, in the eflags register. the cpuid level allows the cpuid instruction to return diff erent information in eax, ebx, ecx, and edx registers. the level is determined by the initialized value of the eax register prior to executio n of the cpuid instruction. 8.2.1 standard cpuid levels the standard cpuid levels are part of the standard x86 instruction set. 8.2.1.1 cpuid instruct ion with eax = 00000000h standard function 00000000h (eax = 00000000 h) of the cpuid instru ction returns the maximum standard cpuid levels, as well as the processor vendor string. after the instruction is exec uted, the eax register contains the maximum st andard cpuid levels s upported. the maximum standard cpuid level is the highest acceptable value for the eax register input. this does not include the extended cpuid levels. the ebx through edx registers contain the vendor st ring of the processor as shown in table 8-16. 8.2.1.2 cpuid instruct ion with eax = 00000001h standard function 00000001h (eax = 00000001h) of the cpuid instru ction returns the processor type, family, model, step- ping information in the eax register, and the supported st andard feature flags in the edx register. the ebx and ecx reg- isters are reserved. table 8-17 provides a register map. in the edx register, each flag refers to a specific feature. some of these features have pr otection control in cr4. before using any of these features, the software should check the corre sponding feature flag. attempting to execute an unavailable feature can cause exceptions and unexpected behavior. for exam ple, software must check edx[4] before attempting to use the time stamp counter instruction. table 8-18 on page 628 shows the eax and edx bit field formats when eax = 00000001h and indicates if a feature is not supported. table 8-16. cpuid instruction with eax = 00000000h register (note 1) note 1. the ?register? column is intentionally out of order. returned contents description comment eax 00000001h maximum standard level ebx 68747541h {htua} vendor id string 1 edx 69746e65h {itne} vendor id string 2 ecx 444d4163h {dmac} vendor id string 3 table 8-17. cpuid instruction with eax = 00000001h register returned contents description comment eax 000005axh type/family/model/step ebx 00000400h reserved ecx 00000000h reserved edx 0088a93dh standard feature flags
628 amd geode? lx processors data book instruction set 33234h table 8-18. cpuid instruction codes with eax = 00000000 register reset value description comment eax[31:28] 0x0 reserved eax[27:20] 0x00 extended family eax[19:16] 0x00 extended model eax[15:12] 0x0 reserved eax[11:8] 0x5 processor/ instruction family eax[7:4] 0xa processor model eax[3:0] 0x2 processor stepping may change with cpu revision ebx[31:24] 0x00 initial local apci physical id ebx[23:16] 0x00 reserved ebx[15:08] 0x04 clflush cache line size in qword - 8 byte increments ebx[7:0] 0x00 8-bit brand id edx[31:27] 0000 reserved edx[26] 0 xmm2. streaming simd extensions not supported edx[25] 0 xmm. streaming simd extensions not supported edx[24] 0 fxsr. fast fp save and restore not supported edx[23] 1 mmx?. mmx instruct ion set and architecture edx[22:20] 000 reserved edx[19} 1 clfsh. clflush feature is supported edx[18] 0 pn. 96-bit serial number feature not supported edx[17] 0 pse36. 36-bit page size extensions not supported edx[16] 0 pat. page attribute table not supported edx[15] 1 cmov. conditional move instruction edx[14] 0 mca. machine check architecture not supported edx[13] 1 pge. page global enable feature edx[12] 0 mtrr. memory type range registers not supported edx[11] 1 sep. sysenter/sysexit instruction edx[10] 0 reserved edx[9] 0 apic. advanced programmable interrupt not supported edx[8] 1 cx8. compare exchange (cmpxchg8b) instruction edx[7] 0 mce. machine check exception not supported edx[6] 0 pae. page address extension not supported edx[5] 1 msr. model specific registers via rdmsr/wrmsr instructions edx[4] 1 tsc. time stamp counter and rdtsc instruction edx[3] 1 pse. 4 mb page size extension edx[2] 1 de. debugging extension
amd geode? lx processors data book 629 instruction set 33234h 8.2.2 extended cpuid levels testing for extended cpuid inst ruction support can be accomp lished by executing a cpuid instruction with the eax regis- ter initialized to 80000000h. if a value greater than or eq ual to 80000000h is returned to the eax register by the cpuid instruction, the processor su pports extended cpuid levels. 8.2.2.1 cpuid instruct ion with eax = 80000000h extended function 80000000h (eax = 80000000h) of the cpuid instruction returns the maximum extended cpuid sup- ported levels as well as the processor vendor string. after the instruction is executed, the eax register contains the maximum ext ended cpuid levels supported. the maximum extended standard cpuid level is the highest acceptable value for the eax register input. the ebx through edx registers contain the vendor st ring of the processor as shown in table 8-19. 8.2.2.2 cpuid instruct ion with eax = 80000001h extended function 80000001h (eax = 80000001h) of the cpuid in struction returns the processor type, family, model, step- ping information in the eax register, and the supported extende d feature flags in the edx register. the ebx and ecx reg- isters are reserved. table 8-20 provides a register map. in the edx register, each flag refers to a specific extended f eature. some of these features have protection control in cr4. before using any of these extended features, the software should check the corresponding flag. attempting to execute an unavailable extended feature can cause exceptions and unexpected behavior. table 8-21 on page 630 shows the eax and edx bit field formats when eax = 80000001h and indicates if a feature is not supported. edx[1] 0 vme. virtual interrupt flag in vm86 not supported edx[0] 1 fpu. floating point unit on chip table 8-19. cpuid instruction with eax = 80000000h register (note 1) note 1. the ?register? column is intentionally out of order. returned contents description comment eax 80000006h maximum extended cpuid level ebx 68747541h {htua} vendor id string 1 edx 69746e65h {itne} vendor id string 2 ecx 444d4163h {dmac} vendor id string 3 table 8-20. cpuid instruction with eax = 80000001h register returned contents description comment eax 000005axh type/family/model/step ebx 00000000h reserved ecx 00000000h reserved edx c0c0a13dh feature flags table 8-18. cpuid instruction codes with eax = 00000000 register reset value description comment
630 amd geode? lx processors data book instruction set 33234h table 8-21. cpuid instruction codes with eax = 80000001h register reset value description comment eax[31:28] 0x0 reserved eax[27:20] 0x00 extended family eax[19:16] 0x00 extended model eax[15:12] 0x0 reserved eax[11:8] 0x5 processor/ instruction family eax[7:4] 0x5 processor model eax[3:0] 0x2 processor stepping may change with cpu revision edx[31] 1 3dn. 3dnow! instruction set edx[30] 1 3de. 3dnow! instruction set extension edx[29] 0 lm. long mode not supported edx[28:25] 0000 reserved not supported edx[24] 0 fxsr/fxrstor. fast fp save and restore not supported edx[23] 1 mmx. mmx instruct ion set and architecture edx[22] 1 ammx. amd mmx instruction extension edx[21] 0 reserved edx[20] 0 nx. no-execute page protection not supported edx[19] 0 mp. multiprocessing capability not supported edx[18] 0 reserved edx[17] 0 pse36. 36-bit page size extensions not supported edx[16] 0 pat. page attribute table not supported edx[15] 1 cmov. conditional move instruction (cmov, fcmov, fcomi) edx[14] 0 mca. machine check architecture not supported edx[13] 1 pge. page global enable feature edx[12] 0 mtrr. memory type range registers not supported edx[11] 0 asep. syscall/sysret instruction edx[10] 0 reserved edx[9] 0 apic. advanced programmable interrupt control- ler not supported edx[8] 1 cx8. compare exchange (cmpxchg8b) instruction edx[7] 0 mce. machine check exception not supported edx[6] 0 pae. page address extension not supported edx[5] 1 msr. model specific registers via rdmsr/wrmsr instructions edx[4] 1 tsc. time stamp counter and rdtsc instruction edx[3] 1 pse. 4mb page size extension edx[2] 1 de. debugging extension edx[1] 0 vme. virtual interrupt flag in vm86 not supported edx[0] 1 fpu. floating point unit on chip
amd geode? lx processors data book 631 instruction set 33234h 8.2.2.3 cpuid instruct ion with eax = 80000002h, 80000003h, or 80000004h extended functions 80000002h through 80000004h (eax = 80000002h, eax = 80000003h, and eax = 80000004h) of the cpuid instruction returns an ascii string containing the cp u marketing name, as shown in table 8-22. these functions eliminate the need to look up the processor name in a lookup tabl e. software can simply call these functions to obtain the name of the processor. the string may be 48 ascii characters lo ng, and is returned in little endian format. if the name is shorter than 48 characters long, the remaining by tes are filled with ascii nul characters (00h). table 8-22. cpuid instruction with eax = 80000002h, 80000003h, or 80000004h register returned contents description comment eax = 80000002h eax 646f6547h {doeg} cpu marketing name 1a ebx 4d542865h {mt)e} cpu marketing name 1b ecx 6e492029h {ni (} cpu marketing name 2a edx 72676574h {rget} cpu marketing name 2b eax = 80000003h eax 64657461h {deta} cpu marketing name 3a ebx 6f725020h {orp} cpu marketing name 3b ecx 73736563h {ssec} cpu marketing name 4a edx 6220726fh {b ro} cpu marketing name 4b eax = 80000004h eax 4d412079h {ma y} cpu marketing name 5a ebx 43502044h {cp d} cpu marketing name 5b ecx 00000053h {s} cpu marketing name 6a edx 00000000h cpu marketing name 6b
632 amd geode? lx processors data book instruction set 33234h 8.2.2.4 cpuid instruct ion with eax = 80000005h extended function 80000005h (eax = 80000005h) of the cpuid in struction returns information on the internal l1 cache and tlb structures. they are used for reporting purposes only. see table 8-23 for returned contents. 8.2.2.5 cpuid instruct ion with eax = 80000006h extended function 80000006h (eax = 80000006h) of the cpuid in struction returns information on the internal l2 cache and tlb structures. see table 8-24 on page 632 for returned contents. . table 8-23. cpuid instruction with eax = 80000005h register returned contents description comment eax 00000000h 4 mb l1 tlb information indicates no 4 mb l1 tlb. ebx ff10ff10h 4 kb l1 tlb information decodes to eight fully associative code tlb and eight fully associative data tlb entries. ecx 40100120h l1 data cache information indicates 16 kb four-way associative with 32-byte lines for data cache. these encodings follow the amd report- ing method. edx 40100120h l1 code cache information indicates 16 kb four-way associative with 32-byte lines for code cache. these encodings follow the amd report- ing method. table 8-24. cpuid instruction with eax = 80000006h register returned contents description comment eax 0000f004h l2 tlb information two-way associative 64 entry code and data combined tlb. ebx 00002040h l2 tlb information ecx 00804120h l2 code cache information indicates no l2 cache. edx 00000000h l2 data cache information
amd geode? lx processors data book 633 instruction set 33234h 8.3 processor core instruction set the instruction set for the amd geode lx processor core is summarized in table 8-26. the table uses several symbols and abbreviations that are described next and listed in table 8-25. 8.3.1 opcodes opcodes are given as hex values except when they appear within brackets as binary values. 8.3.2 clock counts the clock counts listed in the instruction set summary tabl e (table 8-26) are grouped by operating mode (real and pro- tected) and whether there is a register/cache hit or a cache mi ss. in some cases, more than one clock count is shown in a column for a given instruction, or a variable is used in the clock count. 8.3.3 flags there are nine flags that are affected by the execution of instructions. the flag names have been abbreviated and various con- ventions used to indicate what effect t he instruction has on the particular flag. table 8-25. processor core instruction set table legend symbol or abbreviation description opcode # immediate 8-bit data. ## immediate 16-bit data. ### full immediate 32-bit data (8, 16, or 32 bits). + 8-bit signed displacement. +++ full signed displacement (16 or 32 bits). clock count / register operand/memory operand. n number of times operation is repeated. l level of the stack frame. | conditional jump taken | conditional jump not taken. (e.g., ?4|1? = four clocks if jump taken, one clock if jump not taken). \cpl iopl \ cpl > iopl (where cpl = current pr ivilege level, iopl = i/o privilege level). flags of overflow flag. df direction flag. if interrupt enable flag. tf trap flag. sf sign flag. zf zero flag. af auxiliary flag. pf parity flag. cf carry flag. x flag is modified by the instruction. - flag is not changed by the instruction. 0 flag is reset to ?0.? 1 flag is set to ?1.? u flag is undefined following ex ecution of the instruction.
634 amd geode? lx processors data book instruction set 33234h table 8-26. processor core instruction set instruction opcode clock count (reg/cache hit) flags notes real mode prot?d mode odi t s z ap c fffffffff real mode prot?d mode aaa ascii adjust al after addition 37 3 3 u -- -uuxux aad ascii adjust ax before divide d5 0a 4 4 u- - - xxuxu aam ascii adjust ax after multiply d4 0a u- - - xxuxu divide by non-zero 15 15 divide by zero 18 18 aas ascii adjust al after subtract 3f 3 3 u- - - uuxux adc add with carry x- - - xxxxx b h register to register 1 [00dw] [11 reg r/m] 1 1 register to memory 1 [000w] [mod reg r/m] 1 1 memory to register 1 [001w] [mod reg r/m] 1 1 immediate to register/memory 8 [00sw] [mod 010 r/m]### 1 1 immediate to accumulator 1 [010w] ### 1 1 add integer add x- - - xxxxx b h register to register 0 [00dw] [11 reg r/m] 1 1 register to memory 0 [000w] [mod reg r/m] 1 1 memory to register 0 [001w] [mod reg r/m] 1 1 immediate to register/memory 8 [00sw] [mod 000 r/m]### 1 1 immediate to accumulator 0 [010w] ### 1 1 and boolean and 0- - - xxux0 b h register to register 2 [00dw] [11 reg r/m] 1 1 register to memory 2 [000w] [mod reg r/m] 1 1 memory to register 2 [001w] [mod reg r/m] 1 1 immediate to register/memory 8 [00sw] [mod 100 r/m]### 1 1 immediate to accumulator 2 [010w] ### 1 1 arpl adjust requested privilege level 63 [mod reg r/m] -----x--- ah to memory dst[1:0] < src[1:0] 6 to memory dst[1:0] >= src[1:0] 4 to register dst[1:0] < src[1:0] 4 to register dst[1:0] >= src[1:0] 4 bound check array boundaries 62 [mod reg r/m] --------- b, e g,h,j,k, r if below range (interrupt #5) 8+int 8+int if above range (interrupt #5) 8+int 8+int if in range 66 bsf scan bit forward 0f bc [mod reg r/m] 2 2 -----x--- b h register, register/memory bsr scan bit reverse 0f bd [mod reg r/m] 2 2 -----x--- b h register, register/memory bswap byte swap 0f c[1 reg] 1 1 --------- bt test bit --------x b h register/memory, immediate 0f ba [mod 100 r/m]# 1 1 register, register 0f a3 [mod reg r/m] 1 1 memory, register 0f a3 [mod reg r/m] 7 7 btc test bit and complement --------x b h register/memory, immediate 0f ba [mod 111 r/m]# 2 2 register, register 0f bb [mod reg r/m] 2 2 memory, register 0f bb [mod reg r/m] 8 8 btr test bit and reset --------x b h register/memory, immediate 0f ba [mod 110 r/m]# 2 2 register, register 0f b3 [mod reg r/m] 2 2 memory, register 0f b3 [mod reg r/m 8 8
amd geode? lx processors data book 635 instruction set 33234h bts test bit and set --------x b h register/memory, immediate 0f ba [mod 101 r/m] # 2 2 register, register 0f ab [mod reg r/m] 2 2 memory, register 0f ab [mod reg r/m] 8 8 call subroutine call --------- b h,j,k,r direct within segment e8 +++ 2 2 register/memory indirect within segment ff [mod 010 r/m] 2/4 2/4 direct intersegment -call gate -task switch 711 24+ 123+ indirect intersegment -call gate -task switch ff [mod 011 r/m] 9 13 25+ 124+ cbw convert byte to word 98 1 1 --------- cdq convert doubleword to quadword 99 1 1 --------- clc clear carry flag f8 1 1 --------0 cld clear direction flag fc 2 2 -0------- clflush 7+ 7+ cli clear interrupt flag fa 1 1 --0------ m clts clear task switched flag 0f 06 3 3 --------- c l cmc complement the carry flag f5 2 2 --------x cmova/cmovnbe move if above/not below or equal 1 1 --------- r register, register/memory 0f 47 [mod reg r/m] cmovbe/cmovna move if below or equal/not above 1 1 --------- r register, register/memory 0f 46 [mod reg r/m] cmovae/cmovnb/cmovnc move if above or equal/not below/not carry 1 1 --------- r register, register/memory 0f 43 [mod reg r/m] cmovb/cmovc/cmovnae move if below/carry/not above or equal 1 1 --------- r register, register/memory 0f 42 [mod reg r/m] cmove/cmovz move if equal/zero 1 1 --------- r register, register/memory 0f 44 [mod reg r/m] cmovne/cmovnz move if not equal/not zero 1 1 --------- r register, register/memory 0f 45 [mod reg r/m] cmovg/cmovnle move if greater/not less or equal 1 1 --------- r register, register/memory 0f 4f [mod reg r/m] cmovle/cmovng move if less or equal/not greater 1 1 --------- r register, register/memory 0f 4e [mod reg r/m] cmovl/cmovnge move if less/not greater or equal 1 1 --------- r register, register/memory 0f 4c [mod reg r/m] cmovge/cmovnl move if greater or equal/not less 1 1 --------- r register, register/memory 0f 4d [mod reg r/m] cmovo move if overflow 1 1 --------- r register, register/memory 0f 40 [mod reg r/m] cmovno move if no overflow 0f 41 [mod reg r/m] 1 1 --------- r register, register/memory cmovp/cmovpe move if parity/parity even 0f 4a [mod reg r/m] 1 1 --------- r register, register/memory cmovnp/cmovpo move if not parity/parity odd 0f 4b [mod reg r/m] 1 1 --------- r register, register/memory cmovs move if sign 0f 48 [mod reg r/m] 1 1 --------- r register, register/memory table 8-26. processor core instruction set (continued) instruction opcode clock count (reg/cache hit) flags notes real mode prot?d mode odi t s z ap c fffffffff real mode prot?d mode
636 amd geode? lx processors data book instruction set 33234h cmovns move if not sign 0f 49 [mod reg r/m] 1 1 --------- r register, register/memory cmp compare integers x- - - xxxxx b h register to register 3 [10dw] [11 reg r/m] 1 1 register to memory 3 [101w] [mod reg r/m] 1 1 memory to register 3 [100w] [mod reg r/m] 1 1 immediate to register/memory 8 [00sw] [mod 111 r/m] ### 1 1 immediate to accumulator 3 [110w] ### 1 1 cmps compare string a [011w] 6 6 x- - - xxxxx b h cmpxchg compare and exchange x- - - xxxxx register1, register2 0f b [000w] [11 reg2 reg1] 4 4 memory, register 0f b [000w] [mod reg r/m] 4-5 4-5 cmpxchg8b compare and exchange 8 bytes 0f c7 [mod 001 r/m] --------- if {edx,eax} == dst 10 10 if {edx,eax} != dst 12 12 cpuid cpu identification 0f a2 --------- if eax <= 1 13 13 if 1 < eax < 2 31 10 10 if 2 31 <= eax <= (2 31 +6) 14 14 if eax > (2 31 +6) 11 11 cwd convert word to doubleword 99 1 1 --------- cwde convert word to doubleword extended 98 3 3 --------- daa decimal adjust al after addition 27 2 2 ---- xxxxx das decimal adjust al after subtraction 2f 2 2 ---- xxxxx dec decrement by 1 x- - - xxxx- b h register/memory byte fe [mod 001 r/m] 1 1 register/memory word/dword ff [mod 001 r/m] 1 1 register (short form) 4 [1 reg] 1 1 div unsigned divide ----xxuu- accumulator by register/memory divisor: byte word doubleword f [011w] [mod 110 r/m] 15 23 7-39 15 23 7-39 b,e e,h dmint enter debug management mode 0f 39 48-50 50-52 000000000 s, u s, u enter enter new stack frame c8 ##,# --------- level = 0 77 bh level = 1 13 13 level (l) > 1 15+21 15+21 hlt halt f4 13+ 13+ --------- l icebp call debug exception handler f1 29+ 29+ --x0----- u u idiv integer (signed) divide f [011w] [mod 111 r/m] ----xxuu- b,e e,h accumulator by register/memory divisor: byte word doubleword 16 24 40 16 24 7-40 table 8-26. processor core instruction set (continued) instruction opcode clock count (reg/cache hit) flags notes real mode prot?d mode odi t s z ap c fffffffff real mode prot?d mode
amd geode? lx processors data book 637 instruction set 33234h imul integer (signed) multiply x---xxuux b h accumulator by register/memory multiplier: byte word doubleword f [011w] [mod 101 r/m] 3 4 4 3 4 4 register with register/memory multiplier: word doubleword 0f af [mod reg r/m] 4 4 4 4 register/memory with immediate to register2 multiplier: byte word doubleword 6 [10s1] [mod reg r/m] ### 4-6 4-7 4-7 4-6 4-7 4-7 in input from i/o port --------- m fixed port e [010w] # 7 7/21 variable port e [110w] 7 7/21 inc increment by 1 x- - - xxxx- b h register/memory f [111w] [mod 000 r/m] 1 1 register (short form) 4 [0 reg] 1 1 ins input string from i/o port 6 [110w] 10 10/24 --------- b h,m int i software interrupt cd # 23 37-245 --x0----- b,e g,j,k,r int 3 breakpoint software interrupt cc 21-22 37-245 b,c g,i,k,r into overflow software interrupt if of==0 if of==1 (int 4) ce 4 7 4 7 b,c g,i,k,r invd invalidate cache 0f 08 9+ 9+ --------- t t invlpg invalidate tlb entry 0f 01 [mod 111 r/m] 7+ 7+ --------- iret interrupt return cf 6-13 13-239 xxxxxxxxx g,h,j,k, r jb/jnae/jc jump on below/not above or equal/carry --------- r 8-bit displacement 72 + 1 1 full displacement 0f 82 +++ 1 1 jbe/jna jump on below or equal/not above -------- r 8-bit displacement 76 + 1 1 full displacement 0f 86 +++ 1 1 jcxz/jecxz jump on cx/ecx zero e3 + 2 2 --------- r je/jz jump on equal/zero -------- r 8-bit displacement 74 + 1 1 full displacement 0f 84 +++ 1 1 jl/jnge jump on less/not greater or equal -------- r 8-bit displacement 7c + 1 1 full displacement 0f 8c +++ 1 1 jle/jng jump on less or equal/not greater -------- r 8-bit displacement 7e + 1 1 full displacement 0f 8e +++ 1 1 jmp unconditional jump -------- b h,j,k,r 8-bit displacement eb + 1 1 full displacement e9 +++ 1 1 register/memory indirect within segment ff [mod 100 r/m] 1/3 1/3 direct intersegment ea [unsigned full offset, selector] 79-254 indirect intersegment ff [mod 101 r/m] 9 11-256 jnb/jae/jnc jump on not below/above or equal/not carry -------- r 8-bit displacement 73 + 1 1 full displacement 0f 83 +++ 1 1 table 8-26. processor core instruction set (continued) instruction opcode clock count (reg/cache hit) flags notes real mode prot?d mode odi t s z ap c fffffffff real mode prot?d mode
638 amd geode? lx processors data book instruction set 33234h jnbe/ja jump on not below or equal/above -------- r 8-bit displacement 77 + 1 1 full displacement 0f 87 +++ 1 1 jne/jnz jump on not equal/not zero -------- r 8-bit displacement 75 + 1 1 full displacement 0f 85 +++ 1 1 jnl/jge jump on not less/greater or equal -------- r 8-bit displacement 7d + 1 1 full displacement 0f 8d +++ 1 1 jnle/jg jump on not less or equal/greater -------- r 8-bit displacement 7f + 1 1 full displacement 0f 8f +++ 1 1 jno jump on not overflow -------- r 8-bit displacement 71 + 1 1 full displacement 0f 81 +++ 1 1 jnp/jpo jump on not parity/parity odd -------- r 8-bit displacement 7b + 1 1 full displacement 0f 8b +++ 1 1 jns jump on not sign -------- r 8-bit displacement 79 + 1 1 full displacement 0f 89 +++ 1 1 jo jump on overflow -------- r 8-bit displacement 70 + 1 1 full displacement 0f 80 +++ 1 1 jp/jpe jump on parity/parity even -------- r 8-bit displacement 7a + 1 1 full displacement 0f 8a +++ 1 1 js jump on sign -------- r 8-bit displacement 78 + 1 1 full displacement 0f 88 +++ 1 1 lahf load ah with flags 9f 2 2 --------- lar load access rights 0f 02 [mod reg r/m] -----x--- a g,h,j,p from register/memory 9 lds load pointer to ds c5 [mod reg r/m] 4 9/15 --------- b h,i,j lea load effective address --------- no index register 8d [mod reg r/m] 1 1 with index register 1 1 leave 22 les load pointer to es c4 [mod reg r/m] 4 9/15 --------- b h,i,j lfence 11 lfs load pointer to fs 0f b4 [mod reg r/m] 4 9/15 --------- b h,i,j lgdt load gdt register 0f 01 [mod 010 r/m] 8-9 8-9 --------- b,c h,l lgs load pointer to gs 0f b5 [mod reg r/m] 4 9/15 --------- b h,i,j lidt load idt register 0f 01 [mod 011 r/m] 8-9 8-9 --------- b,c h,l lldt load ldt register 0f 00 [mod 010 r/m] --------- a g,h,j,l from register/memory 8 lmsw load machine status word --------- from register/memory 0f 01 [mod 110 r/m] 8 8 b,c h,l lods load string a [110 w] 2 2 --------- b h loop offset loop/no loop e2 + 2 2 --------- r table 8-26. processor core instruction set (continued) instruction opcode clock count (reg/cache hit) flags notes real mode prot?d mode odi t s z ap c fffffffff real mode prot?d mode
amd geode? lx processors data book 639 instruction set 33234h loopnz/loopne offset e0 + 2 2 --------- r loopz/loope offset e1 + 2 2 --------- r lsl load segment limit -----x--- from register/memory 0f 03 [mod reg r/m] 9 a g,h,j,p lss load pointer to ss 0f b2 [mod reg r/m] 4 9/15 --------- a h,i,j ltr load task register --------- from register/memory 0f 00 [mod 011 r/m] 9 a g,h,j,l leave leave current stack frame c9 2 2 --------- b h mfence 1 mov move data --------- b h register to register 8 [10dw] [11 reg r/m] 1 1 register to memory 8 [100w] [mod reg r/m] 1 1 register/memory to register 8 [101w] [mod reg r/m] 1 1 immediate to register/memory c [011w] [mod 000 r/m] ### 1 1 immediate to register (short form) b [w reg] ### 1 1 memory to accumulator (short form) a [000w] +++ 1 1 accumulator to memory (short form) a [001w] +++ 1 1 mov move to/from segment registers --------- i,j to stack segment 7/13 to all other segments: register/memory to segment register 8e [mod sreg3 r/m] 1 6/13 segment register to register/memory 8c [mod sreg3 r/m] 1 6/13 mov move to/from control registers --------- l register to cr 0f 22 [11 eee reg] 9-13 9-13 cr to register 0f 20 [11 eee reg] 2-5 2-5 mov move to/from debug registers --------- l register to dr 0f 23 [11 eee reg] 10/18 10/18 dr to register 0f 21 [11 eee reg] 8/18 8/18 mov move to/from test registers --------- ul,u register to tr 0f 26 [11 eee reg] 2 2 tr to register 0f 24 [11 eee reg] 1 1 movs move string a [010w] 4 4 --------- b h movsx move with sign extension --------- b h register from register/memory 0f b[111w] [mod reg r/m] 1 1 movzx move with zero extension --------- b h register from register/memory 0f b[011w] [mod reg r/m] 1 1 mul unsigned multiply x---xxuux b h accumulator with register/memory multiplier: byte word doubleword f [011w] [mod 100 r/m] 3 4 7 3 4 7 neg negate integer f [011w] [mod 011 r/m] 1 1 x- - - xxxxx b h nop no operation 90 1 1 --------- not boolean complement f [011w] [mod 010 r/m] 1 1 --------- b h oio official invalid opcode 0f ff 1 8-125 --x0----- or boolean or 0- - - xxux0 b h register to register 0 [10dw] [11 reg r/m] 1 1 register to memory 0 [100w] [mod reg r/m] 1 1 memory to register 0 [101w] [mod reg r/m] 1 1 immediate to register/memory 8 [00sw] [mod 001 r/m] ### 1 1 immediate to accumulator 0 [110w] ### 1 1 table 8-26. processor core instruction set (continued) instruction opcode clock count (reg/cache hit) flags notes real mode prot?d mode odi t s z ap c fffffffff real mode prot?d mode
640 amd geode? lx processors data book instruction set 33234h out output to port --------- m fixed port e [011w] # 8 8/23 variable port e [111w] 8 8/23 outs output string 6 [111w] 12 12/26 --------- b h,m pause 7 pop pop value off stack --------- b h,i,j register 8f [mod 000 r/m] 1 1 memory 8f [mod 000 r/m] 3 3 register (short form) 5 [1 reg] 1 1 ds 1f 1 6/13 es 07 1 6/13 ss 17 1 7/13 fs 0f a1 1 6/13 gs 0f 9a 1 6/13 popa pop all general registers 61 8 8 --------- b h popf pop stack into flags 9d 2 2 xxxxxxxxx b h,n prefix bytes --------- m assert hardware lock prefix f0 address size prefix 67 operand size prefix 66 segment override prefix -cs -ds -es -fs -gs -ss 2e 3e 26 64 65 36 push push value onto stack --------- b h register/memory ff [mod 110 r/m] 1/2 1/2 register (short form) 5 [0 reg] 1 1 cs 0e 1 1 ss 16 1 1 ds 1e 1 1 es 06 1 1 fs 0f a0 1 1 gs 0f a8 1 1 immediate 6 [10s0] ### 1 1 pusha push all general registers 60 8 8 --------- b h pushf push flags register 9c 2 2 --------- b h rcl rotate through carry left register/memory by 1 d [000w] [mod 010 r/m] 2 2 x -------x b h register/memory by cl d [001w] [mod 010 r/m] 4-6 4-6 u -------x register/memory by immediate c [000w] [mod 010 r/m] # 4-6 4-6 u -------x rcr rotate through carry right register/memory by 1 register/memory by cl register/memory by immediate bh d [000w] [mod 011 r/m] 3-5 3-4 x -------x d [001w] [mod 011 r/m] 4-7 4-7 u -------x c [000w] [mod 011 r/m] # 4-7 4-7 u -------x rdm leave debug management mode 0f 3a 36+ 36+ xxxxxxxxx s, u s, u rdmsr read tmodel specific register ( note 1 ) 0f 32 5 5 --------- rdpmc (note 1) 77 rdtsc read time stamp counter (note 1) 0f 31 5 5 --------- table 8-26. processor core instruction set (continued) instruction opcode clock count (reg/cache hit) flags notes real mode prot?d mode odi t s z ap c fffffffff real mode prot?d mode
amd geode? lx processors data book 641 instruction set 33234h rep cmps cx==0 66 cx==1 13 13 cx>1 10+3c 10+3c rep ins input string f3 6[110w] --------- b h,m cx==0 99/24 cx==1 cx>1 15+6c 15+6c/ 30+6c rep lods load string f3 a[110w] --------- b h cx==0 55 cx==1 10 10 cx>1 8+2c 8+2c rep movs move string f3 a[010w] --------- b h cx==0 55 cx==1 13 13 cx>1 11+2c 11+2c rep outs output string f3 6[111w] 16+10 c 16+10 c\ 31+10 c --------- b h,m rep stos store string f3 a[101w] 8+c 8+c --------- b h repe cmps compare string find non-match f3 a[011w] 11+4n 11+4n x - - - xxxxx b h repe scas scan string find non-al/ax/eax f3 a[111w] 7+2n 7+2n x - - - xxxxx b h repne cmps compare string find match f2 a[011w] 10+4n 10+4n x- - - xxxxx b h repne scas scan string find al/ax/eax f2 a[111w] 7+3n 7+3n x- - - xxxxx b h ret return from subroutine --------- within segment c3 3 3 b g,h,j,k, r within segment adding immediate to sp c2 ## 3 3 intersegment cb 6 10-48 intersegment adding immediate to sp ca ## 7 10-48 protected mode: different privilege level -intersegment -intersegment adding immediate to sp 35 35 rol rotate left register/memory by 1 d[000w] [mod 000 r/m] 2 2 x-------x b h register/memory by cl d[001w] [mod 000 r/m] 2 2 u-------x register/memory by immediate c[000w] [mod 000 r/m] # 2 2 u-------x ror rotate right register/memory by 1 d[000w] [mod 001 r/m] 2 2 x-------x b h register/memory by cl d[001w] [mod 001 r/m] 2 2 u-------x register/memory by immediate c[000w] [mod 001 r/m] # 2 2 u-------x rsdc restore segment register and descripto r 0f 79 [mod sreg3 r/m] 9 9 --------- s,u s,u rsldt restore ldtr and descriptor 0f 7b [mod 000 r/m] 9 9 --------- s,u s,u rsts restore tsr and descriptor 0f 7d [mod 000 r/m] 10 10 --------- s,u s,u rsm resume from smm mode 0f aa 35 35 xxxxxxxxx s,u s,u sahf store ah in flags 9e 1 1 ---- xxxxx table 8-26. processor core instruction set (continued) instruction opcode clock count (reg/cache hit) flags notes real mode prot?d mode odi t s z ap c fffffffff real mode prot?d mode
642 amd geode? lx processors data book instruction set 33234h sal shift left arithmetic bh register/memory by 1 d[000w] [mod 100 r/m] 1 1 x - - - x x u x x register/memory by cl d[001w] [mod 100 r/m] 1 1 u - - - x x u x x register/memory by immediate c[000w] [mod 100 r/m] # 1 1 u - - - x x u x x sar shift right arithmetic bh register/memory by 1 d[000w] [mod 111 r/m] 2 2 x - - - x x u x x register/memory by cl d[001w] [mod 111 r/m] 2 2 u - - - x x u x x register/memory by immediate c[000w] [mod 111 r/m] # 2 2 u - - - x x u x x sbb integer subtract with borrow bh register to register 1[10dw] [11 reg r/m] 1 1 x- - - xxxx x register to memory 1[100w] [mod reg r/m] 1 1 memory to register 1[101w] [mod reg r/m] 1 1 immediate to register/memory 8[00sw] [mod 011 r/m] ### 1 1 immediate to accumulator (short form) 1[110w] ### 1 1 scas scan string a [111w] 2 2 x- - - xxxx x b h setalc set al to cf d6 2 2 u u setb/setnae/setc set byte on below/not above or equal/carry --------- h to register/memory 0f 92 [mod 000 r/m] 1 1 setbe/setna set byte on below or equal/not above --------- h to register/memory 0f 96 [mod 000 r/m] 1 1 sete/setz set byte on equal/zero --------- h to register/memory 0f 94 [mod 000 r/m] 1 1 setl/setnge set byte on less/not greater or equal --------- h to register/memory 0f 9c [mod 000 r/m] 1 1 setle/setng set byte on less or equal/not greater --------- h to register/memory 0f 9e [mod 000 r/m] 1 1 setnb/setae/setnc set byte on not below/above or equal/not carry --------- h to register/memory 0f 93 [mod 000 r/m] 1 1 setnbe/seta set byte on not below or equal/above --------- h to register/memory 0f 97 [mod 000 r/m] 1 1 setne/setnz set byte on not equal/not zero --------- h to register/memory 0f 95 [mod 000 r/m] 1 1 setnl/setge set byte on not less/greater or equal --------- h to register/memory 0f 9d [mod 000 r/m] 1 1 setnle/setg set byte on not less or equal/greater --------- h to register/memory 0f 9f [mod 000 r/m] 1 1 setno set byte on not overflow --------- h to register/memory 0f 91 [mod 000 r/m] 1 1 setnp/setpo set byte on not parity/parity odd --------- h to register/memory 0f 9b [mod 000 r/m] 1 1 setns s et byte on not sign --------- h to register/memory 0f 99 [mod 000 r/m] 1 1 seto set byte on overflow --------- h to register/memory 0f 90 [mod 000 r/m] 1 1 setp/setpe set byte on parity/parity even --------- h to register/memory 0f 9a [mod 000 r/m] 1 1 sets set byte on sign h to register/memory 0f 98 [mod 000 r/m] 1 1 --------- table 8-26. processor core instruction set (continued) instruction opcode clock count (reg/cache hit) flags notes real mode prot?d mode odi t s z ap c fffffffff real mode prot?d mode
amd geode? lx processors data book 643 instruction set 33234h sfence 11 sgdt store gdt register b,c h to register/memory 0f 01 [mod 000 r/m] 6 6 --------- sidt store idt register b,c h to register/memory 0f 01 [mod 001 r/m] 6 6 --------- sldt store ldt register ah to register/memory 0f 00 [mod 000 r/m] 1 --------- str store task register ah to register/memory 0f 00 [mod 001 r/m] 3 --------- smsw store machine status word 0f 01 [mod 100 r/m] 2 2 --------- b,c h stos store string a [101w] 2 2 --------- b h shl shift left logical bh register/memory by 1 d [000w] [mod 100 r/m] 1 1 x - - - xxuxx register/memory by cl d [001w] [mod 100 r/m] 2 2 u - - - xxuxx register/memory by immediate c [000w] [mod 100 r/m] # 1 1 u - - - xxuxx shld shift left double u- - - xxuxx b h register/memory by immediate 0f a4 [mod reg r/m] # 2 1 register/memory by cl 0f a5 [mod reg r/m] 2 1 shr shift right logical bh register/memory by 1 d [000w] [mod 101 r/m] 2 1 x - - - xxuxx register/memory by cl d [001w] [mod 101 r/m] 2 1 u - - - xxuxx register/memory by immediate c [000w] [mod 101 r/m] # 2 1 u - - - xxuxx shrd shift right double u- - - xxuxx b h register/memory by immediate 0f ac [mod reg r/m] # 2 1 register/memory by cl 0f ad [mod reg r/m] 2 1 smint software smm entry 0f 38 56-58 56-58 000000000 s,u s,u stc set carry flag f9 1 1 --------1 std set direction flag fd 2 2 -1------- sti set interrupt flag fb 1 1 --1------ m sub integer subtract x -- - xxxxx b h register to register 2 [10dw] [11 reg r/m] 1 1 register to memory 2 [100w] [mod reg r/m] 1 1 memory to register 2 [101w] [mod reg r/m] 1 1 immediate to register/memory 8 [00sw] [mod 101 r/m] ### 1 1 immediate to accumulator (short form) 2 [110w] ### 1 1 svdc save segment register and descriptor 0f 78 [mod sreg3 r/m] 7 7 --------- s,u s,u svldt save ldtr and descriptor 0f 7a [mod 000 r/m] 7 7 --------- s,u s,u svts save tsr and descriptor 0f 7c [mod 000 r/m] 8 8 --------- s,u s,u sysenter fast system call entry 0f 34 10 10 --------- sysexit fast system call exit 0f 35 11 11 --------- test te s t b i t s 0 -- - xxux0 b h register/memory and register 8 [010w] [mod reg r/m] 1 1 immediate data and register/memory f [011w] [mod 000 r/m] ### 1 1 immediate data and accumulator a [100w] ### 1 1 verr verify read access -----x--- a g,h,j,p to register/memory 0f 00 [mod 100 r/m] 8 verw verify write access -----x--- a g,h,j,p to register/memory 0f 00 [mod 101 r/m] 8 wait wait until fpu not busy 9b 1 1 --------- wbinvd writeback and invalidate cache 0f 09 16+ 16+ --------- t t table 8-26. processor core instruction set (continued) instruction opcode clock count (reg/cache hit) flags notes real mode prot?d mode odi t s z ap c fffffffff real mode prot?d mode
644 amd geode? lx processors data book instruction set 33234h wrmsr write to model specific register 0f 30 10 10 --------- xadd exchange and add x- - - xxxxx register1, register2 0f c[000w] [11 reg2 reg1] 2 2 memory, register 0f c[000w] [mod reg r/m] 2 2 xchg exchange --------- b,f f,h register/memory with register 8[011w] [mod reg r/m] 2 2 register with accumulator 9[0 reg] 2 2 xlat translate byte d7 4 4 --------- h xor boolean exclusive or 0- - - xxux0 b h register to register 3 [00dw] [11 reg r/m] 1 1 register to memory 3 [000w] [mod reg r/m] 1 1 memory to register 3 [001w] [mod reg r/m] 1 1 immediate to register/memory 8 [00sw] [mod 110 r/m] ### 1 1 immediate to accumulator (short form) 3 [010w] ### 1 1 note 1. the instructions, rdtsc, rdpmc, and rdmsr all have the e ffect of serializing with pending memory requests. for example, a rdtsc will not complete until any pending line fills or prefetc hes have completed. this is an artifact of the amd geode cpu and geodelink architecture si nce out-of-order read re sponses are not supported. table 8-26. processor core instruction set (continued) instruction opcode clock count (reg/cache hit) flags notes real mode prot?d mode odi t s z ap c fffffffff real mode prot?d mode
amd geode? lx processors data book 645 instruction set 33234h instruction notes for instruction set summary notes a through c apply to real address mode only: a. this is a protected mode instruction. attempted execut ion in real mode results in exception 6 (invalid opcode). b. exception 13 fault (general protection) oc curs in real mode if an operand reference is made that partially or fully extends beyond the maximum cs, ds, es, fs, or gs segment limit. exception 12 fault (stack segment limit violation or not present) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum ss limit. c. this instruction may be executed in real mode. in real mode , its purpose is primarily to initialize the cpu for protected mode. notes e through g apply to real address mode and protected virtual address mode: e. an exception may occur, depending on the value of the operand. f. lock# is automatically asserted, regardless of the presence or absence of the lock prefix. g. lock# is asserted during descriptor table accesses. notes h through r apply to prot ected virtual address mode only: h. exception 13 fault occurs if the memory operand in cs, ds, es, fs, or gs cannot be used due to either a segment limit violation or an access rights violation. if a stack limit is violated, an exception 12 occurs. i. for segment load operations, the cpl, rpl, and dpl must agree with the privilege rules to avoid an exception 13 fault. the segment?s descriptor must indi cate ?present? or exception 11 (cs, ds, es, fs, or gs not present). if the ss register is loaded, and a stack segment not present is detected, an exception 12 occurs. j. all segment descriptor accesses in the gdt or ldt made by this instruction automatically assert lock# to maintain descriptor integrity in multiprocessor systems. k. jmp, call, int, ret, and iret instructions referring to another code segment cause an exception 13, if an applicable privilege rule is violated. l. an exception 13 fault occurs if cpl is greater than 0 (0 is the most privileged level). m. an exception 13 fault occurs if cpl is greater than iopl. n. the if bit of the flags register is not updated if cpl is gr eater than iopl. the iopl and vm fields of the flags register are updated only if cpl = 0. o. the pe bit of the msw (cr0) cannot be reset by this in struction. use mov into cr0 if you need to reset the pe bit. p. any violation of privilege rules as they apply to the sele ctor operand do not cause a prot ection exception; rather, the zero flag is cleared. q. if the processor?s memory operand violates a segment lim it or segment access rights, an exception 13 fault occurs before the esc instruction is executed. an exception 12 faul t occurs if the stack limit is violated by the operand?s starting address. r. the destination of a jmp, call, int, ret, or iret must be in the defined limit of a co de segment or an exception 13 fault occurs. issue s applies to amd-specif ic smm and dmm instructions: s. an invalid opcode exception 6 occurs unless the current privilege level is zero (most privileged) and either the instruc- tion is enabled in smm_ctl, the instru ction is enabled in dmm_ctl, the proc essor is in system management mode, or the processor is in debug management mode. issue t applies to the cache invalidation instruction with the cache operating in writeback mode: t. the total clock count is the clock count shown plus the nu mber of clocks required to write all ?modified? cache lines to external memory. u. non-standard processor core instructions. see section 8.3. 4 "non-standard processor core instructions" on page 646 for details.
646 amd geode? lx processors data book instruction set 33234h 8.3.4 non-standard processor core instructions 8.3.4.1 dmint - enter debug management mode operation opcode instruction c locks description 0f 39 dmint 50-52 enter dmm and call the dmi handler if (cpl<>0 or (dmm_inst_en=0 and smm=0 and dmm=0)) #ud; else dmm_header[ac_temp0] <= ac_temp0; dmm_header[temp6] <= temp6; dmm_header[dmm_flags] <= dmm_flags; dmm_header[eflags] <= eflags; dmm_header[cr0] <= cr0; dmm_header[next_ip] <= ip of instruction after dmint; dmm_header[current_ip] <= ip of dmint instruction; dmm_header[cs_limit] <= cs.limit; dmm_header[cs_base] <= cs.base; dmm_header[cs_selector] <= cs.selector; dmm_header[cs_flags] <= cs.flags; dmm_header[ss_selector] <= ss.selector; dmm_header[ss_flags] <= ss.flags; dmm_header[xdr7] <= xdr7; dmm_header[xdr6] <= xdr6; dmm_header[dr7] <= dr7; dmm_header[dr6] <= dr6; if (dmm_cache_disable) cr0 <= 32?h00000010; else cr0 <= {1?b0, cr0.cd, cr0.nw, 29?h010}; dr7 <= 32?h00000400; xdr7 <= 32?h00000000; ss.flags <= {ss.flags[15:7], 2?b0, ss.flags[4:0]}; cs.flags <= 16?h009a; cs.selector <= dmm_base >> 4; cs.base <= dmm_base; if (dmm_limit < 32?g100000) cs.limit <= dmm_limit; cs.g <= 1?b0; else cs.limit <= dmm_limit | 32?hfff; cs.g <= 1?b1; eflags <= 32?h00000002; dmm <= 1; jump to cs at offset of 0;
amd geode? lx processors data book 647 instruction set 33234h description the dmint instruction saves portions of the processors stat e to the debug management mode (dmm) header, alters the processors state for dmm, enters dmm, and then calls the dmm mode handler. below is the format of the dmm header. flags affected all eflags are returned to their reset values. exceptions #ud if current privilege level is not 0, or the dmm_inst_en = 0 and if the processor is not in smm and if the pro- cessor is not in dmm. notes data address breakpoints on dmm header addresses that o ccur when executing the dmin t instruction are ignored. the dmint instruction clears the v, x, and h bits of th e dmm header. dmint sets the s bit of the dmm header. the next_ip failed of the dmm header will poin t to the instruction after the dmint. 8.3.4.2 icebp - call debug exception handler operation same as an int 1 instruction. description the icebp instruction generates a call to the debug exception handl er. it?s advantage over the int 1 instruction is that it is a single byte opcode. flags affected the eflags are pushed to the stack, and may then be modifi ed before the debug exception handler is called. the eflags may be restored by the debug exception handler?s iret. notes debuggers should not insert icebp instruction immediately after an instruction that alte rs the stack segment (mov_ss). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dr6 -4 dr7 -8 xdr6 -c xdr7 -10 ss flags ss selector -14 gb 0av 0 1 dpl 1 0 e w a index ti rpl cs flags cs selector -18 gd 0av 01dpl11c f r a index ti rpl cs base -1c 0 cs limit -20 current_ip -24 next_ip -28 cr0 -2c eflags -30 0c w 0c r 0vx 0hs 0 0 0-34 temp6 -38 ac temp0 -3c opcode instruction c locks description f1 icebp 29+ call debug exception handler
648 amd geode? lx processors data book instruction set 33234h 8.3.4.3 mov - move to /from test registers operation if (cpl <> 0) then #gp(0); else dest <= src; description the above forms of the mov instruction store the contents of a test register (either tr0, tr 1, tr2, tr3, tr4, tr5, tr6, or tr7) to a general purpose register (e ither eax, ecx, edx, ebx, esp, ebp, esi, or edi), or load a test register from a general purpose register. thirty-two bit operands are always used with these inst ructions, regardless of the operand size attribute. flags affected none. exceptions #gp(0) if the current privilege level is not 0. notes these are not the intel or amd geode lx pr ocessor test registers. writing to a te st register has no side effects. reading from a test register has no side effects. the reg field within the modr/m byte specifies which of the test registers is involved. reg values of 0, 1, 2, 3, 4, 5, 6, 7 specify tr0, tr1, tr2, tr3, tr4, tr5, tr6, and tr7 respectively. the two bits in the mod field are always 11. the r/m field specifies the general register involved. moving a value into a test register has no side effects. software other than dmi handlers should not use test regist ers, because dmi handlers might not preserve the contents of test registers. dmi handlers may use test registers as a plac e for saving and restoring general registers when the state of the stack is unknown. opcode instruction c locks description 0f 24 /r mov r32,tr 1 move test register to general register 0f 26 /r mov tr, r32 2 move general register to test register
amd geode? lx processors data book 649 instruction set 33234h 8.3.4.4 rdm - leave debug management mode operation description the rdm instruction restores the state of the processor from the dmm header, and then jumps to the address indicated in the next_ip field of the dmm header. be low is the format of the dmm header. flags affected all bits of the eflags register is restored from the dmm header. opcode instruction c locks description 0f 3a rdm 36 return from dmi 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dr6 -4 dr7 -8 xdr6 -c xdr7 -10 ss flags ss selector -14 gb 0av 0 1 dpl 1 0 e w a index ti rpl cs flags cs selector -18 gd 0av 01dpl11c f r a index ti rpl cs base -1c 0 cs limit -20 current_ip -24 next_ip -28 cr0 -2c eflags -30 0c w 0c r 0vx 0hs 0 0 0-34 temp6 -38 ac temp0 -3c if (cpl<>0 or (dmm_inst_en=0 and smm=0 and dmm=0)) #ud; else dr6 <= dmm_headr[dr6]; dr7 <= dmm_header[dr7]; xdr6 <= dmm_header[xdr6]; xdr7 <= dmm_header[xdr7]; ss.flags <= dmm_header[ss.flags]; ss.selector <= dmm_ header[ss.selector]; cpl <= dmm_header[ss.dpl] cs.flags <= dmm_header[cs.flags]; cs.selector <= dmm_header[cs.selector]; cs.base <= dmm_header[cs.base]; cs.limit <= dmm_header[cs.limit]; cr0 <= dmm_header[cr0]; eflags <= dmm_header[eflags]; dmm <= 0; if (dmm_header[h]) halt processor; else jump to cs at offset of dmm_header[next_ip];
650 amd geode? lx processors data book instruction set 33234h exceptions #ud if current privilege level is not 0, or the dmm_inst_en = 0 and if the processor is not in smm and if the processor is not in dmm. notes data address breakpoints on dmm header addresses are i gnored during the execution of the rsm instruction. the rdm instruction does not check the values th at it reads from the dmm header for validity. the rdm instruction sets the current privilege le vel to the ss dpl value read from the dmm header. if a rdm restores the processor to real m ode, the vm bit of the eflags register is cleared regardless of the state of the vm bit in the eflags value of the dmm header. if rdm restores the processor to a privilege level that is not 3, then t he vm bit of the eflags regi ster is cleared, regardless of the contents of the vm bit in the eflags value of the dmm header. 8.3.4.5 rsdc - restore segmen t register and descriptor operation description restore the specified segment descriptor (either ds, es, fs, gs, ss, or cs) from memory. below is the format of the descriptor contents in memory. flags affected none. exceptions #ud if current privilege level is not 0, or the smm_inst_en = 0 and if the processor is not in smm and if the processor is not in dmm. notes the reg field within the mod r/m byte specifies which segment?s register and descriptor should be restored. reg fields of 0, 1, 2, 3, 4, and 5 specify the es, cs, ss, ds, fs, and gs se lectors respectively. the rsdc instruction is not recognized if the reg field is 6 or 7. the rsdc instruction does not check its memory operand for validity. care should be taken to always load valid data into segment registers. a rsdc cs instruction?s alteration of the cs base does not take affect until the exec ution of the next non-sequential instruction or pipeline flush. a pipeline flush could be caused by an external suspend, an external debug stall, or an smc snoop hit. a rsdc cs instruction?s alteration of the cs limit takes affect immediately. a rsdc ss instruction alters the cpl to the dpl value. if th e executable bit (x) is set, then the cs becomes unwritable. external interrupts, single-step traps, and debug exceptions are not taken between a rsdc cs instruction and the rsldt instruction (section 8.3.4.6 on page 651). opcode instruction c locks description 0f 79 /r rsdc sr, m80 11 restore descriptor from memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 selector[15:3] ti rpl +8 base[31:24] g b 0 v limit[19:16] 1 dpl 1 x e w a base[23:16] +4 base[15:0] limit[15:0] +0 if (cpl<>0 or (smm_inst_en =0 and smm=0 and dmm=0)) #ud; else seg.descr <= mem80;
amd geode? lx processors data book 651 instruction set 33234h 8.3.4.6 rsldt - restore local descri ptor table register and descriptor operation description restore the local descriptor table register and descriptor from memory. below is the format of the descriptor contents in memory. flags affected none. exceptions #ud if current privilege level is not 0, or the smm_inst_en = 0 and if the processor is not in smm and if the processor is not in dmm. notes the reg field within the mod r/m byte must be zero for the rsldt instruction to be recognized. the rsldt instruction does not check its memory operand for validity. care should be taken to always load valid data into the ldt. opcode instruction c locks description 0f 7b rsldt m80 11 restore ldtr from memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 selector[15:3] ti rpl +8 base[31:24] g b 0 v limit[19:16] 1 dpl 1 0 e w a base[23:16] +4 base[15:0] limit[15:0] +0 if (cpl<>0 or (smm_inst_en =0 and smm=0 and dmm=0)) #ud; else ldt.descr <= mem80;
652 amd geode? lx processors data book instruction set 33234h 8.3.4.7 rsm - leave s ystem management mode operation description the rsm instruction restores the stat e of the processor from the system management mode (s mm) header, and then jumps to the address indicated by the next_ip field of the smm header. below is the format of the smm header. flags affected all bits of the eflags register is restored from the smm header. exceptions #ud if current privilege level is not 0, or the smm_inst_en = 0 and if the processor is not in smm and if the processor is not in dmm. opcode instruction c locks description 0f aa rsm 36 return from smi 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dr7 -4 eflags -8 cr0 -c current_ip -10 next_ip -14 cs_flags code segment selector -18 gd 0av 0 1 dpl 1 1 cf r a index ti rpl cs_base -1c 0 cs_limit[19:0] -20 ss_flags smm flags -24 gb 0av 01dpl10ewa c r nvxmhsp ic w 0 i/o size i/o address[15:0] -28 i/o_data -2c smm_ctl -30 0-34 if (cpl<>0 or (smm_inst_en =0 and smm=0 and dmm=0)) #ud; else smm_ctl <= smm_header[smm_ctl]; ss.flags <= smm_header[ss.flags]; cpl <= smm_header[ss.dpl]; cs.limit <= smm_header[cs.limit]; cs.base <= smm_header[cs.base] cs.selector <= smm_header[cs.selector]; cs.flags <= smm_header[cs.flags]; cr0 <= smm_header[cr0]; eflags <= smm_header[eflags]; if (!dmm_ctl.dbg_as_dmi) dr7 <= smm_header[dr7]; if (smm_header[n]) smm <= 1; else smm <= 0; if (smm_header[h]) halt processor; else jump to cs at offset of smm_header[next_ip];
amd geode? lx processors data book 653 instruction set 33234h notes the rsm instruction does not check the values th at it reads from the smm header for validity. the rsm instruction set the curr ent privilege level to the ss dp l value read from the smm header. if a rsm restores the processor to real mode, the vm bit of t he eflags register is cleared r egardless of the state of the vm bit in the eflags value of the smm header. if rsm restores the processor to a privilege level that is not 3, then the vm bit of the eflags register is cleared, regardless of the contents of the vm bit in the eflags value of the smm header. 8.3.4.8 rsts - restore task register and descriptor operation description restore the task register and descriptor from memory. belo w is the format of the descriptor contents in memory. flags affected none. exceptions #ud if current privilege level is not 0, or the smm_inst_en = 0 and if the processor is not in smm and if the processor is not in dmm. notes the reg field within the mod r/m byte must be zero for the rsts instruction to be recognized. the rsts instruction does not check its memory operand for validity. care should be taken to always load valid data into the ts. 8.3.4.9 setalc - set al to cf operation al <= {8{cf}}; description if the eflags cf is set, then the setalc instruction sets al to ffh. otherwise, setalc sets al to ffh. flags affected none. opcode instruction c locks description 0f 7d rsts m80 12 restore ts from memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 selector[15:3] ti rpl +8 base[31:24] g b 0 v limit[19:16] 1 dpl 1 0 e w a base[23:16] +4 base[15:0] limit[15:0] +0 opcode instruction c locks description d6 setalc 2 set al according to cf. if (cpl<>0 or (smm_inst_en =0 and smm=0 and dmm=0)) #ud; else ts.descr <= mem80;
654 amd geode? lx processors data book instruction set 33234h exceptions none. notes none. 8.3.4.10 smint - enter system management mode operation opcode instruction c locks description 0f 38 smint 55 enter smm and call the smi handler if (cpl<>0 or (smm_inst_en =0 and smm=0 and dmm=0)) #ud; else smm_header[smm_ctl] <= smm_ctl; smm_header[i/o_data] <= 0; smm_header[i/o_address] <= 0; smm_header[i/o_size] <= 0; smm_header[smm_flag s] <= smm_flags; smm_header[ss_flags] <= ss.flags; smm_header[cs_limit] <= cs.limit; smm_header[cs_base] <= cs.base; smm_header[cs_selector] <= cs.selector; smm_header[cs_flags] <= cs.flags; smm_header[next_ip] <= ip of instruction after smint; smm_header[current_ip] <= ip of smint instruction; smm_header[cr0] <= cr0; smm_header[eflags] <= eflags; smm_header[dr7] <= dr7; cr0 <= {1?b0, cr0.cd, cr0.nw, 29?h010}; if (!dmm_ctl.dbg_as_dmi) dr7 <= 32?h00000400; ss.flags <= {ss.flags[15:7], 2?b0, ss.flags[4:0]}; cs.flags <= 16?h009a; cs.selector <= smm_base >> 4; cs.base <= smm_base; if (smm_limit < 32?g100000) cs.limit <= smm_limit; cs.g <= 1?b0; else cs.limit <= smm_limit | 32?hfff; cs.g <= 1?b1; eflags <= 32?h00000002; smm_ctl <= {smm_ctl[31:3],1?b0, smm_ctl[1], 1?b0}; smm <= 1; jump to cs at offset of 0;
amd geode? lx processors data book 655 instruction set 33234h description the smint instruction saves portions of the processors state to the system management mode (smm) h eader, alters the processors state for smm, enters smm, and then calls the smm handler. below is the format of the smm header. flags affected all eflags are returned to their reset values. 8.3.4.11 exceptions #ud if current privilege level is not 0, or the smm_inst_en = 0 and if the processor is not in smm and if the processor is not in dmm. notes the smint instruction will clear the v, x, m, h, p, i, i/o address, i/o size, and i/o data fields of the smm header. the current_ip field of the smm header will poin t to the smint instruction. the next _ip field of the smm header will point to the instruction following the smint instruction. the s bit of the smm header will be set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dr7 -4 eflags -8 cr0 -c current_ip -10 next_ip -14 cs_flags code segment selector -18 gd 0av 0 1 dpl 1 1 cf r a index ti rpl cs_base -1c 0 cs_limit[19:0] -20 ss_flags smm flags -24 gb 0av 01dpl10ewa c r nvxmhsp ic w 0 i/o size i/o address[15:0] -28 i/o_data -2c smm_ctl -30
656 amd geode? lx processors data book instruction set 33234h 8.3.4.12 svdc - save segmen t register and descriptor operation description write the specified segment descriptor (either ds, es, fs, gs, ss, or cs) to memory. below is the format of the descriptor contents in memory. flags affected none. exceptions #ud if current privilege level is not 0, or the smm_inst_en = 0 and if the processor is not in smm and if the processor is not in dmm. notes the reg field within the mod r/m byte specifies which segment?s register and descriptor should be written. reg fields of 0, 1, 2, 3, 4, and 5 specify the es, cs, ss, ds, fs, and gs se lectors respectively. the rsdc instruction is not recognized if the reg field is 6 or 7. 8.3.4.13 svldt - save local descrip tor table register and descriptor operation description write the local descriptor table register and descriptor to memory. below is the format of the descriptor contents in mem- ory. flags affected none. opcode instruction clocks description 0f 78 /r svdc sr, m80 7 restore descriptor from memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 selector[15:3] ti rpl +8 base[31:24] g b 0 v limit[19:16] 1 dpl 1 0 e w a base[23:16] +4 base[15:0] limit[15:0] +0 opcode instruction c locks description 0f 7a svldt m80 7 save ldt to memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 selector[15:3] ti rpl +8 base[31:24] g b 0 v limit[19:16] 1 dpl 1 0 e w a base[23:16] +4 base[15:0] limit[15:0] +0 if (cpl<>0 or (smm_inst_en =0 and smm=0 and dmm=0)) #ud; else mem80 <= seg.descr; if (cpl<>0 or (smm_inst_en =0 and smm=0 and dmm=0)) #ud; else mem80 <= ldt.descr;
amd geode? lx processors data book 657 instruction set 33234h exceptions #ud if current privilege level is not 0, or the smm_inst_en = 0 and if the processor is not in smm and if the processor is not in dmm. notes the reg field within the mod r/m byte must be zero for the svldt instruction to be recognized. 8.3.4.14 svts - save task register and descriptor operation description write the task register and descriptor to memory. below is the format of the descriptor contents in memory.. flags affected none. exceptions #ud if current privilege level is not 0, or the smm_inst_en = 0 and if the processor is not in smm and if the processor is not in dmm. notes the reg field within the mod r/m byte must be zero for the svts instruction to be recognized. opcode instruction c locks description 0f 7c svts m80 8 save ts to memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 selector[15:3] ti rpl +8 base[31:24] g b 0 v limit[19:16] 1 dpl 1 0 e w a base[23:16] +4 base[15:0] limit[15:0] +0 if (cpl<>0 or (smm_inst_en =0 and smm=0 and dmm=0)) #ud; else mem80 <= ts.descr;
658 amd geode? lx processors data book instruction set 33234h 8.4 mmx?, fpu, and amd 3dno w!? technology in structions sets the cpu is functionally divided into the floating point unit (fpu) unit and the integer unit. the fpu has been extended to process mmx, amd 3dnow!, and floating point instructions in parallel with the integer unit. when the integer unit detects an mmx instruction, the instruct ion is passed to the fpu or execution. the integer unit con- tinues to execute instructions while the fpu executes the mmx instruction. if another mmx instruction is encountered, the second mmx instruction is placed in the mmx que ue. up to six mmx instructions can be queued. when the integer unit detects a floating point instruction without memory operands, after two clock cycles the instruction passes to the fpu for execution. the int eger unit continues to execute instructi ons while the fpu executes the floating point instruction. if another fpu instruct ion is encountered, the second fpu instruction is placed in the fpu queue. up to four fpu instructions can be queued. in the event of an fpu e xception, while other fpu instru ctions are queued, the state of the cpu is saved to ensure recovery. the mmx instruction set (including extensions) is summarize d in table 8-28. the fpu instruction set is summarized in table 8-29. the amd 3dnow! instruction set (including extens ions) is summarized in table 8-30. the abbreviations used in the instruction sets are listed in table 8-27. note: the following opcodes are reserved: d9d7, d9e2, d9e7, ddfc, ded8, deda, dedc, dedd, dede, and dffc. if a reserved opcode is executed, unpredictable results may occur (exceptions are not generated). table 8-27. mmx?, fpu, and amd 3dnow!? instruction set table legend abbreviation description <--- result written. [11 mm reg] binary or binary groups of digits. mm one of eight 64-bit mmx registers. reg a general purpose register. <--- sat --- if required, the resu ltant data is saturat ed to remain in the associated data range. <--- move --- source data is moved to result location. [byte] eight 8-bit bytes are processed in parallel. [word] four 16-bit words are processed in parallel. [dword] two 32-bit dwords are processed in parallel. [qword] one 64-bit qword is processed. [sign xxx] the byte, word, dword, or qwo rd most significant bit is a sign bit. mm1, mm2 mmx register 1, mmx register 2. mod r/m mod and r/m byte encoding (table 8-8 on page 622). pack source data is truncated or saturated to next smaller data size, then concatenated. packdw pack two dwords from source and two dwords from destination into four words in the desti- nation register. packwb pack four words from source and four words from destination into eight bytes in the destina- tion register. imm8 one-byte of immediate value. memory64 64 bits in memory located in eight consecutive bytes. memory32 32 bits in memory located in four consecutive bytes. index 0 (imm8) the value imm8 [1:0] *16. index 1 (imm8) the value imm8 [3:2] *16. index 2 (imm8) the value imm8 [5:4] *16. index 3 (imm8) the value imm8 [7:6] *16. windex 0 (imm8) the range given by [index0 (imm8) + 15: index0 (imm8)].
amd geode? lx processors data book 659 instruction set 33234h windex 1 (imm8) the range given by [index1 (imm8) + 15: index1 (imm8)]. windex 2 (imm8) the range given by [index2 (imm8) + 15: index2 (imm8)]. windex 3 (imm8) the range given by [i ndex3 (imm8) r15: indes3 (imm8)]. windexall (imm8) the four different index # (imm8) ordered in the same way as word. msb [bytes] the most significant bits of the different eight bytes in qword, ordered from higher to lower bytes. msb [words] the most significant bits (sign bit) of th e different four words in a qword ordered from higher to lower. trun if required, the resultant data is truncated to remain within the associated range. n stack register number. tos (note 1) top of stack register point ed to by sss in the status register. st(1) (note 1) fpu register next to tos. st(n) (note 1) a specific fpu register, relative to tos. m.wi 16-bit integer operand from memory. m.si 32-bit integer operand from memory. m.li 64-bit integer operand from memory. m.sr 32-bit real operand from memory. m.dr 64-bit real operand from memory. m.xr 80-bit real operand from memory. m.bcd 18-digit bcd integer operand from memory. cc fpu condition code. env regs status, mode control and tag registers, instruction pointer and operand pointer. note 1. all references to tos and st(n) refer to stack layout prior to execution. values popped off the stack are discarded. a pop from the stack increments the top of the stack point er. a push to the stack decr ements the top of the stack pointer. table 8-27. mmx?, fpu, and amd 3dnow!? instruction set table legend abbreviation description
660 amd geode? lx processors data book instruction set 33234h table 8-28. mmx? instruction set mmx? instructions opcode operation clock ct notes emms empty mmx state 0f77 tag word <--- ffffh (empties the floating point tag word) 1 1 maskmovq streaming (cache bypass) store usin g byte mask (using edi register) 2 mmx register1with mmx register2 0ff7 [11 mm1 mm2] memory [edi] [byte] <--- mmx reg 2 [sign byte] ? mmx reg 1 [byte] : memory [edi] [byte] movd move doubleword register to mmx register 0f6e [11 mm reg] mmx reg [qword] <--- zero extend --- reg [dword] 1 mmx register to register 0f7e [11 mm reg] reg [qword] <--- mmx reg [low dword] 1 memory to mmx register 0f6e [mod mm r/m] mmx regr [qword] <--- zero extend --- memory [dword] 1 mmx register to memory 0f7e [mod mm r/m] memory [dword] <--- mmx reg [low dword] 1 movntq streaming (cache bypass) store 1 mmx register to memory64 0fe7 [mod mm r/m] memory64 [qword] <--- mmx reg [qword] movq move quardword mmx register 2 to mmx register 1 0f6f [11 mm1 mm2] mmx reg 1 [qword] <--- mmx reg 2 [qword] 1 mmx register 1 to mmx register 2 0f7f [11 mm1 mm2] mmx reg 2 [qword] <--- mmx reg 1 [qword] 1 memory to mmx register 0f6f [mod mm r/m] mmx reg [qword] <--- memory[qword] 1 mmx register to memory 0f7f [mod mm r/m] memory [qword] <--- mmx reg [qword] 1 packssdw pack dword with signed saturation mmx register 2 to mmx register 1 0f6b [11 mm1 mm2] mmx reg 1 [qword] <--- packdw, signed sat --- mmx reg 2, mmx reg 1 2 memory to mmx register 0f6b [mod mm r/m] mmx reg [qword] <--- packdw, signed sat --- memory, mmx reg 2 packsswb pack word with signed saturation mmx register 2 to mmx register 1 0f63 [11 mm1 mm2] mmx reg 1 [qword] <--- packwb, signed sat --- mmx reg 2, mmx reg 1 2 memory to mmx register 0f63 [mod mm r/m] mmx reg [qword] <--- packwb, signed sat --- memory, mmx reg 2 packuswb pack word with unsigned saturation mmx register 2 to mmx register 1 0f67 [11 mm1 mm2] mmx reg 1 [qword] <--- packwb, unsigned sat --- mmx reg 2, mmx reg 1 2 memory to mmx register 0f67 [mod mm r/m] mmx reg [qword] <--- packwb, unsigned sat --- memory, mmx reg 2 paddb packed add byte with wrap-around mmx register 2 to mmx register 1 0ffc [11 mm1 mm2] mmx reg 1 [byte] <--- mmx reg 1 [byte] + mmx reg 2 [byte] 2 memory to mmx register 0ffc [mod mm r/m] mmx reg[byte] <--- memory [byte] + mmx reg [byte] 2 paddd packed add dword with wrap-around mmx register 2 to mmx register 1 0ffe [11 mm1 mm2] mmx reg 1 [sign dword] <--- mmx reg 1 [sign dword] + mmx reg 2 [sign dword] 2 memory to mmx register 0ffe [mod mm r/m] mmx reg [sign dword] <--- memory [sign dword] + mmx reg [sign dword] 2 paddsb packed add signed byte with saturation mmx register 2 to mmx register 1 0fec [11 mm1 mm2] mmx reg 1 [sign byte] <--- sat --- (mmx reg 1 [sign byte] + mmx reg 2 [sign byte]) 2 memory to register 0fec [mod mm r/m] mmx reg [sign byte] <--- sat --- (memory [sign byte] + mmx reg [sign byte]) 2 paddsw packed add signed word with saturation mmx register 2 to mmx register 1 0fed [11 mm1 mm2] mmx reg 1 [sign word] <--- sat --- (mmx reg 1 [sign word] + mmx reg 2 [sign word]) 2 memory to register 0fed [mod mm r/m] mmx reg [sign word] <--- sat --- (memory [sign word] + mmx reg [sign word]) 2 paddusb add unsigned byte with saturation mmx register 2 to mmx register 1 0fdc [11 mm1 mm2] mmx reg 1 [byte] <--- sat --- (mmx reg 1 [byte] + mmx reg 2 [byte]) 2 memory to register 0fdc [mod mm r/m] mmx reg [byte] <--- sat --- (memory [byte] + mmx reg [byte]) 2
amd geode? lx processors data book 661 instruction set 33234h paddusw add unsigned word with saturation mmx register 2 to mmx register 1 0fdd [11 mm1 mm2] mmx reg 1 [word] <--- sat --- (mmx reg 1 [word] + mmx reg 2 [word]) 2 memory to register 0fdd [mod mm r/m] mmx reg [word] <--- sat --- (memory [word] + mmx reg [word]) 2 paddw packed add word with wrap-around mmx register 2 to mmx register 1 0ffd [11 mm1 mm2] mmx reg 1 [word] <--- mmx reg 1 [word] + mmx reg 2 [word] 2 memory to mmx register 0ffd [mod mm r/m] mmx reg [word] <--- memory [word] + mmx reg [word] 2 pand bitwise logical and mmx register 2 to mmx register 1 0fdb [11 mm1 mm2] mmx reg 1 [qword] --- mmx reg 1 [qword], <--- logic and --- mmx reg 2 [qword] 2 memory to mmx register 0fdb [mod mm r/m] mmx reg [qword] memory [qword], <--- logic and --- mmx reg [qword] 2 pandn bitwise logical and not mmx register 2 to mmx register 1 0fdf [11 mm1 mm2] mmx reg 1 [qword] not (mmx reg 1 [qword], <--- logic and --- mmx reg 2) [qword] 2 memory to mmx register 0fdf [mod mm r/m] mmx reg [qword] --- not (mmx reg [qword], <--- logic and --- memory [qword]) 2 pavgb packed average of unsigned byte mmx register 1 with mmx register 2 0fe0 [11 mm1 mm2] mmx reg 1 [byte] <--- round up --- (mmx reg 1 [byte] + mmx reg 2 [byte] + 01h)/2 2 mmx register with memory64 0fe0 [mod mm r/m] mmx reg 1 [byte] <--- round up --- (mmx reg 1 [byte] + memory64 [byte] + 01h)/2 2 pavgw packed average of unsigned word mmx register 1 with mmx register 2 0fe3 [11 mm1 mm2] mmx reg 1 [word] <--- round up --- (mmx reg 1[word] + mmx reg 2 [word] + 01h)/2 2 mmx register with memory 0fe3 [mod mm r/m] mmx reg 1[word] <--- round up --- (mmx reg, [word] + memory64 [word] + 01h)/2 2 pcmpeqb packed byte compare for equality mmx register 2 with mmx register 1 0f74 [11 mm1 mm2] mmx reg 1 [byte] <--- ffh --- if mmx reg 1 [byte] = mmx reg 2 [byte] mmx reg 1 [byte]<--- 00h --- if mmx reg 1 [byte] not = mmx reg 2 [byte] 2 memory with mmx register 0f74 [mod mm r/m] mmx reg [byte] <--- ffh --- if memory[byte] = mmx reg [byte] mmx reg [byte] <--- 00h --- if memory[byte] not = mmx reg [byte] 2 pcmpeqd packed dword compare for equality mmx register 2 with mmx register 1 0f76 [11 mm1 mm2] mmx reg 1 [dword] <--- ffff ffffh --- if mmx reg 1 [dword] = mmx reg 2 [dword] mmx reg 1 [dword]<--- 0000 0000h ---if mmx reg 1[dword] not = mmx reg 2 [dword] 2 memory with mmx register 0f76 [mod mm r/m] mmx reg [dword] <--- ffff ffffh --- if memory[dword] = mmx reg [dword] mmx reg [dword] <--- 0000 0000h --- if memory[dword] not = mmx reg [dword] 2 pcmpeqw packed word compare for equality mmx register 2 with mmx register 1 0f75 [11 mm1 mm2] mmx reg 1 [word] <--- ffffh --- if mmx reg 1 [word] = mmx reg 2 [word] mmx reg 1 [word]<--- 0000h --- if mmx reg 1 [word] not = mmx reg 2 [word] 2 memory with mmx register 0f75 [mod mm r/m] mmx reg [word] <--- ffffh --- if memory[word] = mmx reg [word] mmx reg [word] <--- 0000h --- if memory[word] not = mmx reg [word] 2 pcmpgtb pack compare greater than byte mmx register 2 to mmx register 1 0f64 [11 mm1 mm2] mmx reg 1 [byte] <--- ffh --- if mmx reg 1 [byte] > mmx reg 2 [byte] mmx reg 1 [byte]<--- 00h --- if mmx reg 1 [byte] not > mmx reg 2 [byte] 2 memory with mmx register 0f64 [mod mm r/m] mmx reg [byte] <--- ffh --- if memory[byte] > mmx reg [byte] mmx reg [byte] <--- 00h --- if memory[byte] not > mmx reg [byte] 2 table 8-28. mmx? instruction set (continued) mmx? instructions opcode operation clock ct notes
662 amd geode? lx processors data book instruction set 33234h pcmpgtd pack compare greater than dword mmx register 2 to mmx register 1 0f66 [11 mm1 mm2] mmx reg 1 [dword] <--- ffff ffffh --- if mmx reg 1 [dword] > mmx reg 2 [dword] mmx reg 1 [dword]<--- 0000 0000h ---if mmx reg 1 [dword]not > mmx reg 2 [dword] 2 memory with mmx register 0f66 [mod mm r/m] mmx reg [dword] <--- ffff ffffh --- if memory[dword] > mmx reg [dword] mmx reg [dword] <--- 0000 0000h --- if memory[dword] not > mmx reg [dword] 2 pcmpgtw pack compare greater than word mmx register 2 to mmx register 1 0f65 [11 mm1 mm2] mmx reg 1 [word] <--- ffffh --- if mmx reg 1 [word] > mmx reg 2 [word] mmx reg 1 [word]<--- 0000h --- if mmx reg 1 [word] not > mmx reg 2 [word] 2 memory with mmx register 0f65 [mod mm r/m] mmx reg [word] <--- ffffh --- if memory[word] > mmx reg [word] mmx reg [word] <--- 0000h --- if memory[word] not > mmx reg [word] 2 pextrw extract word into integer register 1 register 32, mmx register 2 imm8 0fc5 [11 reg mm] # reg 32 [high word] <--- 0000 reg32 [low word] <--- mmx reg [windex0 (imm8)] pinsrw insert word from integer register mmx register, register 32 imm8 0fc4 [11 mm1 reg] # tmp1 <--- 0 tmp1 [windex0 (imm8)] <--- reg 32 [low word] tmp2 <--- mmx reg tmp2 [windex0 (imm8)] <--- 0 mmx reg <--- tmp 1 logic or tmp2 2 mmx register, memory 16, imm8 0fc4 [mod mm r/m] # temp1 <--- 0 tmp1 [windex0 (imm8)] <--- memory 16 tmp2 <--- mmx reg tmp2 [windex0 (imm8)] <--- 0 mmx reg <--- tmp1 logic or tmp2 [windex 0 (imm8)] 2 pmaddwd packed multiply and add mmx register 2 to mmx register 1 0ff5 [11 mm1 mm2] mmx reg 1 [low dword] <--- (mmx reg 1 [low dword] * mmx reg 2 [low sign word] + (mmx reg 1 [low dword] * mmx reg2 [high sign word] mmx reg 1 [high dword] <--- (mmx reg 1 [high dword] * mmx reg 2 [low sign word] + (mmx reg 1 [high dword] * mmx reg2 [high sign word] 2 memory to mmx register 0ff5 [mod mm r/m] mmx reg 1 [low dword] <--- (memory [low dword] * mmx reg [low sign word] + (memory1 [low dword] * mmx reg [high sign word]) mmx reg 1 [high dword] <--- (memory [higi dword] * mmx reg [low sign word] + (memory1 [high dword] * mmx reg [high sign word]) 2 pmaxsw packed maximum signed word mmx register 1 with mmx register 2 0fee [11 mm1 mm2] mmx reg 1 [word] <--- mmx reg 1 [word] --- if (mmx reg 1 [sign word] > mmx reg 2 [sign word]) mmx reg 1 [word] <--- mmx reg 2 [word] --- if (mmx reg 1 [sign word] not > mmx reg 2 [sign word] 2 mmx register with memory64 0fee [mod mm r/m] mmx reg [word] <--- mmx reg [word] --- if (mmx reg [sign word] > memory64 [word]) mmx reg [word] <--- memory64 [word] --- if (mmx reg [sign word] not > memory64 [sign word] 2 pmaxub packed maximum unsigned byte mmx register 1 with mmx register 2 0fde [11 mm1 mm2] mmx reg 1 [byte] <--- mmx reg 1 [byte] --- if (mmx reg 1 [byte] > mmx reg 2 [byte]0 mmx reg 1 [byte] <--- mmx reg 2 [byte] --- if (mmx reg 1 [byte] not > mmx reg 2 [byte]) 2 mmx register with memory64 0fde [mod mm r/m] mmx reg [byte] <--- mmx reg [byte] --- if (mmx reg [byte] > memory64 [byte]) mmx reg [byte] <--- memory64 [byte] --- if (mmx reg [byte] not > memory64 [byte]) 2 table 8-28. mmx? instruction set (continued) mmx? instructions opcode operation clock ct notes
amd geode? lx processors data book 663 instruction set 33234h pminsw packed minimum signed word mmx register 1with mmx register 2 0fea [11 mm1 mm2] mmx reg 1 [word] <--- mmx reg 1 [word] --- if (mmx reg 1 [sign word] < mmx reg 2 [sign word]) mmx reg 1 [word] <--- mmx reg 2 [word] --- if (mmx reg 1 [sign word] not < mmx reg 2 [sign word]) 2 mmx register 1with memory64 0fea [mod mm r/m] mmx reg [word] <--- mmx reg 1 [word] --- if (mmx reg [sign word] < memory64 [sign word]) mmx reg [word] <--- memory64 [word] --- if (mmx reg [sign word] not < memory64 [sign word]) 2 pminub packed minimum unsigned byte mmx register 1with mmx register 2 0fda [11 mm1 mm2] mmx reg 1 [byte] <--- mmx reg 1 [byte] --- if (mmx reg 1 [byte] < mmx reg 2 [byte]) 2 mmx reg 1 [byte] <--- mmx reg 2 [byte] --- if (mmx reg 1 [byte] not < mmx reg 2 [byte]) 2 mmx register 1with memory64 0fda [mod mm r/m] mmx reg [byte] <--- mmx reg [byte] --- if (mmx reg [byte] < memory64 [byte]) 2 mmx reg [byte] <--- memory64 [byte] --- if (mmx reg [byte] not < memory64 [byte]) 2 pmovmskb move byte mask to integer register 1 register 32 with mmx register 0fd7 [11 reg mm] reg32 <--- zero extend, msb [bytes] pmulhrw packed multiply high with rounding mmx register 2 to mmx register 1 0fb7 [11 mm1 mm2] multiply the signed packed word in the mmx register/memory with the signed packed word in the mmx register. round with 1/2 bit 15, and store bits 30 - 15 of result in the mmx register. 2 memory to mmx register 0fb7 [mod mm r/m] 2 pmulhuw packed multiply high unsigned word mmx register1 with mmx register2 0fe4 [11 mm1 mm2] mmx reg 1 [word] <--- high word --- (mmxreg 1[word] * mmx reg 2 [word]) 2 mmx register with memory64 0fe4 [mod mm r/m] mmx reg [word] <--- high word --- (mmx reg [word] * memory64 [word]) 2 pmulhw packed multiply high mmx register 2 to mmx register 1 0fe5 [11 mm1 mm2] mmx reg 1 [word] <--- high word --- (mmx reg 1 [sign word] * mmx reg 2 [sign word]) 2 memory to mmx register 0fe5 [mod mm r/m] mmx reg [word] <--- high word --- mmx reg [sign word] * memory64 [sign word] 2 pmullw packed multiply low mmx register 2 to mmx register 1 0fd5 [11 mm1 mm2] mmx reg 1 [word] <--- low word --- (mmx reg 1 [sign word] * mmx reg 2 [sign word]) 2 memory to mmx register 0fd5 [mod mm r/m] mmx reg 1 [word] <--- low word --- (mmx reg [sign word] * memory64 [sign word]) 2 por bitwise or mmx register 2 to mmx register 1 0feb [11 mm1 mm2] mmx reg 1 [qword] <--- mmx reg 1 [qword] logic or mmx reg 2 [qword] 2 memory to mmx register 0feb [mod mm r/m] mmx reg [qword] <--- mmx reg [qword] logic or memory64 [qword] 2 prefetch nta move data closer to the processor using the nta register memory8 0f18 [mod 000 r/m] prefetch0 move data closer to the processor using the t0 register memory8 0f18 [mod 001 r/m] prefetch1 move data closer to the processor using the t1 register memory8 0f18 [mod 010 r/m] prefetch2 move data closer to the processor using the t2 register memory8 0f18 [mod 011 r/m] psadbw packed sum of absolute byte differences mmx register1 with mmx register2 0ff6 [11 mm1 mm2] mmx reg 1 [low word] <--- sum --- (abs --- (mmxreg 1[byte] - mmx reg 2 [byte])) mmx reg 1 [upper three words] <--- 0 3 mmx register with memory64 0ff6 [mod mm r/m] mmx reg [low word] <--- sum --- (abs --- (mmx reg [byte] - memory64 [byte])) mmx reg [up three word] <--- 0 3 table 8-28. mmx? instruction set (continued) mmx? instructions opcode operation clock ct notes
664 amd geode? lx processors data book instruction set 33234h pshufw packed shuffle word mmx register1, mmx register2, imm8 0f70 [11 mm1 mm2] # mmx reg 1 [word] <--- mmx reg 2 [windexall (imm8)] 2 mmx register, memory64, imm8 0f70 [mod mm r/m] # mmx reg [word] <--- memory64 [windexall (imm8)] 2 pslld packed shift left logical dword mmx register 1 by mmx register 2 0ff2 [11 mm1 mm2] mmx reg 1 [dword] <--- mmx reg 1 [dword] shift left by mmx reg 2 [dword], shifting in zeroes 2 mmx register by memory 0ff2 [mod mm r/m] mmx reg [dword] <--- mmx reg [dword] shift left by memory [dword], shifting in zeroes 2 mmx register by immediate 0f72 [11 110 mm] # mmx reg [dword] <--- mmx reg [dword] shift left by [im byte], shifting in zeroes 2 psllq packed shift left logical qword mmx register 1 by mmx register 2 0ff3 [11 mm1 mm2] mmx reg 1 [qword] <--- mmx reg 1 [qword] shift left by mmx reg 2 [qword], shifting in zeroes 2 mmx register by memory 0ff3 [mod mm r/m] mmx reg [qword] <--- mmx reg [qword] shift left by memory [qword], shifting in zeroes 2 mmx register by immediate 0f73 [11 110 mm] # mmx reg [qword] <--- mmx reg [qword]shift left by [im byte], shifting in zeroes 2 psllw packed shift left logical word mmx register 1 by mmx register 2 0ff1 [11 mm1 mm2] mmx reg 1 [word] <--- mmx reg 1 [word] shift left by mmx reg 2 [word], shifting in zeroes 2 mmx register by memory 0ff1 [mod mm r/m] mmx reg [word] <--- mmx reg [word] shift left by memory [word], shifting in zeroes 2 mmx register by immediate 0f71 [11 110mm] # mmx reg [word] <--- mmx reg [word] shift left by [im byte], shifting in zeroes 2 psrad packed shift right arithmetic dword mmx register 1 by mmx register 2 0fe2 [11 mm1 mm2] mmx reg 1 [dword] <--- mmx reg 1 [dword] shift right by mmx reg 2 [dword], shifting in sign bits 2 mmx register by memory 0fe2 [mod mm r/m] mmx reg [dword] <--- mmx reg [dword] shift right by memory [dword], shifting in sign bits 2 mmx register by immediate 0f72 [11 100 mm] # mmx reg [dword] <--- mmx reg [dword] shift right by [im byte], shifting in sign bits 2 psraw packed shift right arithmetic word mmx register 1 by mmx register 2 0fe1 [11 mm1 mm2] mmx reg 1 [word] <--- mmx reg 1 [word] shift right by mmx reg 2 [word], shifting in sign bits 2 mmx register by memory 0fe1 [mod mm r/m] mmx reg [word] <--- mmx reg [word] shift right by memory [word], shifting in sign bits 2 mmx register by immediate 0f71 [11 100 mm] # mmx reg [word] <--- mmx reg [word] shift right by [im byte], shifting in sign bits 2 psrld packed shift right logical dword mmx register 1 by mmx register 2 0fd2 [11 mm1 mm2] mmx reg 1 [dword] <--- mmx reg 1 [dword] shift right by mmx reg 2 [dword], shifting in zeroes 2 mmx register by memory 0fd2 [mod mm r/m] mmx reg [dword] <--- mmx reg [dword] shift right by mem- ory[dword], shifting in zeroes 2 mmx register by immediate 0f72 [11 010 mm] # mmx reg [dword] <--- mmx reg [dword]shift right by [im byte], shifting in zeroes 2 psrlq packed shift right logical qword mmx register 1 by mmx register 2 0fd3 [11 mm1 mm2] mmx reg 1 [qword] <--- mmx reg 1 [qword] shift right by mmx reg 2 [qword], shifting in zeroes 3 mmx register by memory 0fd3 [mod mm r/m] mmx reg [qword] <--- mmx reg [qword] shift right by memory [qword], shifting in zeroes 3 mmx register by immediate 0f73 [11 010 mm] # mmx reg [qword] <--- mmx reg [qword] shift right by [im byte], shifting in zeroes 3 psrlw packed shift right logical word mmx register 1 by mmx register 2 0fd1 [11 mm1 mm2] mmx reg 1 [word] <--- mmx reg 1 [word] shift right by mmx reg 2 [word], shifting in zeroes 2 mmx register by memory 0fd1 [mod mm r/m] mmx reg [word] <--- mmx reg [word] shift right by memory [word], shifting in zeroes 2 mmx register by immediate 0f71 [11 010 mm] # mmx reg [word] <--- mmx reg [word] shift right by imm [word], shifting in zeroes 2 table 8-28. mmx? instruction set (continued) mmx? instructions opcode operation clock ct notes
amd geode? lx processors data book 665 instruction set 33234h psubb subtract byte with wrap-around mmx register 2 to mmx register 1 0ff8 [11 mm1 mm2] mmx reg 1 [byte] <--- mmx reg 1 [byte] - mmx reg 2 [byte] 2 memory to mmx register 0ff8 [mod mm r/m] mmx reg [byte] <--- mmx reg [byte] - memory [byte] 2 psubd subtract dword with wrap-around mmx register 2 to mmx register 1 0ffa [11 mm1 mm2] mmx reg 1 [dword] <--- mmx reg 1 [dword] - mmx reg 2 [dword] 2 memory to mmx register 0ffa [mod mm r/m] mmx reg [dword] <--- mmx reg [dword] - memory64 [dword] 2 psubsb subtract byte signed with saturation mmx register 2 to mmx register 1 0fe8 [11 mm1 mm2] mmx reg 1 [sign byte] <--- sat -- (mmx reg 1 [sign byte] sub- tract mmx reg 2 [sign byte]) 2 memory to mmx register 0fe8 [mod mm r/m] mmx reg [sign byte] <--- sat --- (mmx reg [sign byte] subtract memory64 [sign byte]) 2 psubsw subtract word signed with saturation mmx register 2 to mmx register 1 0fe9 [11 mm1 mm2] mmx reg 1 [sign word] <--- sat --- (mmx reg 1 [sign word] - mmx reg 2 [sign word]) 2 memory to mmx register 0fe9 [mod mm r/m] mmx reg [sign word] <--- sat --- (mmx reg [sign word] - memory64 [sign word]) 2 psubusb subtract byte unsigned with saturation mmx register 2 to mmx register 1 0fd8 [11 mm1 mm2] mmx reg 1 [byte] <--- sat --- (mmx reg 1 [byte] - mmx reg 2 [byte]) 2 memory to mmx register 0fd8 [11 mm reg] mmx reg [byte] <--- sat --- (mmx reg [byte] - memory64 [byte]) 2 psubusw subtract word unsigned with saturation mmx register 2 to mmx register 1 0fd9 [11 mm1 mm2] mmx reg 1 [word] <--- sat --- (mmx reg 1 [word] - mmx reg 2 [word]) 2 memory to mmx register 0fd9 [11 mm reg] mmx reg [word] <--- sat --- (mmx reg [word] - memory64 [word]) 2 psubw subtract word with wrap-around mmx register 2 to mmx register 1 0ff9 [11 mm1 mm2] mmx reg 1 [word] <--- (mmx reg 1 [word] - mmx reg 2 [word]) 2 memory to mmx register 0ff9 [mod mm r/m] mmx reg [word] <--- (mmx reg [word] - memory64 [word]) 2 punpckhbw unpack high packed byte, data to packed words mmx register 2 to mmx register 1 0f68 [11 mm1 mm2] mmx reg 1 [word] <--- {mmx reg 1 [high byte], mmx reg 2 [high byte]} 2 memory to mmx register 0f68 [11 mm reg] mmx reg [word] <--- {memory64 [high byte], mmx reg [high byte]} 2 punpckhdq unpack high packed dword, data to qword mmx register 2 to mmx register 1 0f6a [11 mm1 mm2] mmx reg 1 <--- mmx reg 1 [high dword], mmx reg 2 [high dword] 2 memory to mmx register 0f6a [11 mm reg] mmx reg <--- {memory64 [high dword], mmx reg [high dword]} 2 punpckhwd unpack high packed word, data to packed dwords mmx register 2 to mmx register 1 0f69 [11 mm1 mm2] mmx reg 1 [dword] <--- mmx reg 1 [high word], mmx reg 2 [high word] 2 memory to mmx register 0f69 [11 mm reg] mmx reg [dword] <--- memory64 [high word], mmx reg [high word] 2 punpcklbw unpack low packed byte, data to packed words mmx register 2 to mmx register 1 0f60 [11 mm1 mm2] mmx reg 1 [word] <--- mmx reg 1 [low byte], mmx reg 2 [low byte] 2 memory to mmx register 0f60 [11 mm reg] mmx reg [word] <--- memory64 [low byte], mmx reg [low byte] 2 punpckldq unpack low packed dword, data to qword mmx register 2 to mmx register 1 0f62 [11 mm1 mm2] mmx reg 1 <--- mmx reg 1 [low dword], mmx reg 2 [low dword] 2 memory to mmx register 0f62 [11 mm reg] mmx reg <--- memory64 [low dword], mmx reg [low dword] 2 punpcklwd unpack low packed word, data to packed dwords mmx register 2 to mmx register 1 0f61 [11 mm1 mm2] mmx reg 1 [dword] <--- mmx reg 1 [low word], mmx reg 2 [low word] 2 memory to mmx register 0f61 [11 mm reg] mmx reg [dword] <--- memory64 [low word], mmx reg [low word] 2 table 8-28. mmx? instruction set (continued) mmx? instructions opcode operation clock ct notes
666 amd geode? lx processors data book instruction set 33234h 1) this instruction must wait for the fpu pipeline to flush. cycle count depends on what inst ructions are in the pipeline. pxor bitwise xor mmx register 2 to mmx register 1 0fef [11 mm1 mm2] mmx reg 1 [qword] --- mmx reg 1 [qword], <--- logic exclusive or mmx reg 2 [qword] 2 memory to mmx register 0fef [11 mm reg] mmx reg [qword] --- memory64 [qword], <--- logic exclusive or mmx reg [qword] 2 sfence store fence 0fae [mod 111 r/m] table 8-28. mmx? instruction set (continued) mmx? instructions opcode operation clock ct notes
amd geode? lx processors data book 667 instruction set 33234h table 8-29. fpu instruction set fpu instruction opcode operation clock ct single/dbl (or extended) notes f2xm1 function evaluation 2x-1 d9 f0 tos <--- 2 tos -1 145 - 166 2 fabs floating absolute value d9 e1 tos <--- | tos | 1 3 fadd floating point add top of stack dc [1100 0 n] st(n) <--- st(n) + tos 1/6 80-bit register d8 [1100 0 n] tos <--- tos + st(n) 1/6 64-bit real dc [mod 000 r/m] tos <--- tos + m.dr 1/6 32-bit real d8 [mod 000 r/m] tos <--- tos + m.sr 1/6 faddp floating point add, pop de [1100 0 n] st(n) <--- st(n) + tos; then pop tos 1/6 fiadd floating point integer add 32-bit integer da [mod 000 r/m] tos <--- tos + m.si 2/7 16-bit integer de [mod 000 r/m] tos <--- tos + m.wi 2/7 fchs floating change sign d9 e0 tos <--- - tos 1 fclex clear exceptions (9b) db e2 wait then clear exceptions 1+ 2 fnclex clear exceptions db e2 clear exceptions 1+ 2 fcmovb floating point conditional move if below da [1100 0 n] if (cf=1) st(0) <--- st(n) 1 3 fcmove floating point conditional move if equal da [1100 1 n] if (zf=1) st(0) <--- st(n) 1 3 fcmovbe floating point conditional move if below or equal da [1101 0 n] if (cf=1 or zf=1) st(0) <--- st(n) 1 3 fcmovu floating point conditional move if unordered da [1101 1 n] if (pf=1) st(0) <--- st(n) 1 3 fcmovnb floating point conditional move if not below db [1100 0 n] if (cf=0) st(0) <--- st(n) 1 3 fcmovne floating point conditional move if not equal db [1100 1 n] if (zf=0) st(0) <--- st(n) 1 3 fcmovnbe floating point conditional move if not below or equal db [1101 0 n] if (cf=0 and zf=0) st(0) <--- st(n) 1 3 fcmovnu floating point conditional move if not unordered db [1101 1 n] if (pf=0) st(0) <--- st(n) 1 3 fcom floating point compare 80-bit register d8 [1101 0 n] cc set by tos - st(n) 1/6 64-bit real dc [mod 010 r/m] cc set by tos - m.dr 1/6 32-bit real d8 [mod 010 r/m] cc set by tos - m.sr 1/6 fcomp floating point compare, pop 80-bit register d8 [1101 1 n] cc set by tos - st(n); then pop tos 1/6 64-bit real dc [mod 011 r/m] cc set by tos - m.dr; then pop tos 1/6 32-bit real d8 [mod 011 r/m] cc set by tos - m.sr; then pop tos 1/6 fcompp floating point compare, pop two stack elements de d9 cc set by tos - st(1); then pop tos and st(1) 1/6 fcomi floating point compare real and set eflags 80-bit register db [1111 0 n] eflag set by tos - st(n) 1/6 fcomip floating point compare real and set eflags, pop 80-bit register df [1111 0 n] eflag set by tos - st(n); then pop tos 1/6 fucomi floating point unordered compare real and set eflags 80-bit integer db [1110 1 n] eflag set by tos - st(n) 1/6 fucomip floating point unordered compare real and set eflags, pop 80-bit integer df [1110 1 n] eflag set by tos - st(n); then pop tos 1/6 ficom floating point integer compare 32-bit integer da [mod 010 r/m] cc set by tos - m.wi 2/7 16-bit integer de [mod 010 r/m] cc set by tos - m.si 2/7 ficomp floating point integer compare, pop 32-bit integer da [mod 011 r/m] cc set by tos - m.wi; then pop tos 2/7 16-bit integer de [mod 011 r/m cc set by tos - m.si; then pop tos 2/7 fcos function evaluation: cos(x) d9 ff tos <--- cos(tos) 146 - 215 1
668 amd geode? lx processors data book instruction set 33234h fdecstp decrement stack pointer d9 f6 decrement top of stack pointer 1 3 fdiv floating point divide top of stack dc [1111 1 n] st(n) <--- st(n) / tos 12/47 80-bit register d8 [1111 0 n] tos <--- tos / st(n) 12/47 64-bit real dc [mod 110 r/m] tos <--- tos / m.dr 12/47 32-bit real d8 [mod 110 r/m] tos <--- tos / m.sr 12/47 fdivp floating point divide, pop de [1111 1 n] st(n) <--- st(n) / tos; then pop tos 12/47 fdivr floating point divide reversed top of stack dc [1111 0 n] tos <--- st(n) / tos 12/47 80-bit register d8 [1111 1 n] st(n) <--- tos / st(n) 12/47 64-bit real dc [mod 111 r/m] tos <--- m.dr / tos 12/47 32-bit real d8 [mod 111 r/m] tos <--- m.sr / tos 12/47 fdivrp floating point divide reversed, pop de [1111 0 n] st(n) <--- tos / st(n); then pop tos 12/47 fidiv floating point integer divide 32-bit integer da [mod 110 r/m] tos <--- tos / m.si 13/48 16-bit integer de [mod 110 r/m] tos <--- tos / m.wi 13/48 fidivr floating point integer divide reversed 32-bit integer da [mod 111 r/m] tos <--- m.si / tos 13/48 16-bit integer de [mod 111 r/m] tos <--- m.wi / tos 13/48 ffree free floating point register dd [1100 0 n] tag(n) <--- empty 1 3 fincstp increment stack pointer d9 f7 increment top-of-stack pointer 1 3 finit initialize fpu (9b)db e3 wait, then initialize 1 2 fninit initialize fpu db e3 initialize 1 2 fld load data to fpu register top of stack d9 [1100 0 n] push st(n) onto stack 1 3 80-bit real db [mod 101 /m] push m.xr onto stack 1 3 64-bit real dd [mod 000 r/m] push m.dr onto stack 1 3 32-bit real d9 [mod 000 r/m] push m.sr onto stack 1 3 fbld load packed bcd data to fpu register df [mod 100 r/m] push m.bcd onto stack 28 fild load integer data to fpu register 64-bit integer df [mod 101 r/m] push m.li onto stack 4 32-bit integer db [mod 000 r/m] push m.si onto stack 1 16-bit integer df [mod 000 r/m] push m.wi onto stack 1 fld1 load floating const.= 1.0 d9 e8 push 1.0 onto stack 1 3 fldcw load fpu mode control register d9 [mod 101 r/m] ctl word <--- memory 1 3 fldenv load fpu environment d9 [mod 100 r/m] env regs <--- memory 1 3 fldl2e load floating const.= log2(e) d9 ea push log 2 (e) onto stack 1 3 fldl2t load floating const.= log2(10) d9 e9 push log 2 (10) onto stack 1 3 fldlg2 load floating const.= log10(2) d9 ec push log 10 (2) onto stack 1 3 fldln2 load floating const.= ln(2) d9 ed push log e (2) onto stack 1 3 fldpi load floating const.= d9 eb push onto stack 1 3 fldz load floating const.= 0.0 d9 ee push 0.0 onto stack 1 3 fmul floating point multiply top of stack dc [1100 1 n] st(n) <--- st(n) tos 1/10 80-bit register d8 [1100 1 n] tos <--- tos st(n) 1/10 64-bit real dc [mod 001 r/m] tos <--- tos m.dr 1/10 32-bit real d8 [mod 001 r/m] tos <--- tos m.sr 1/10 fmulp floating point multiply & pop de [1100 1 n] st(n) <--- st(n) tos; then pop tos 1/10 fimul floating point integer multiply 32-bit integer da [mod 001 r/m] tos <--- tos m.si 2/11 16-bit integer de [mod 001 r/m] tos <--- tos m.wi 2/11 fnop no operation d9 d0 no operation 1 3 table 8-29. fpu instruction set (continued) fpu instruction opcode operation clock ct single/dbl (or extended) notes
amd geode? lx processors data book 669 instruction set 33234h fpatan function eval: tan-1(y/x) d9 f3 st(1) <--- atan[st(1) / tos]; then pop tos 269 - 354 3 fprem floating point remainder d9 f8 tos <--- rem[tos / st(1)] 53 - 208 fprem1 floating point remainder ieee d9 f5 tos <--- rem[tos / st(1)] 53 - 208 fptan function eval: tan(x) d9 f2 tos <--- tan(tos); then push 1.0 onto stack 217 - 232 1, 2 frndint round to integer d9 fc tos <--- round(tos) 12 frstor load fpu environment and register dd [mod 100 r/m] restore state 19 2 fsave save fpu environment and register (9b)dd [mod 110 r/m] wait, then save state 19 2 fnsave save fpu environment and register dd [mod 110 r/m] save state 19 2 fscale floating multiply by 2n d9 fd tos <--- tos 2 (st(1)) 3 fsin function evaluation: sin(x) d9 fe tos <--- sin(tos) 130 - 215 1 fsincos function eval.: sin(x)& cos(x) d9 fb temp <--- tos; tos <--- sin(temp); then push cos(temp) onto stack 345 - 374 1, 2 fsqrt floating point square root d9 fa tos <--- square root of tos 13/54 fst store fpu register fpu stack dd [1101 0 n] st(n) <--- tos 1 3 64-bit real dd [mod 010 r/m] m.dr <--- tos 6 32-bit real d9 [mod 010 r/m] m.sr <--- tos 1/4 fstp store fpu register, pop fpu stack db [1101 1 n] st(n) <--- tos; then pop tos 1 3 80-bit real db [mod 111 r/m] m.xr <--- tos; then pop tos 1 3 64-bit real dd [mod 011 r/m] m.dr <--- tos; then pop tos 6 32-bit real d9 [mod 011 r/m] m.sr <--- tos; then pop tos 1/4 fbstp store bcd data, pop df [mod 110 r/m] m.bcd <--- tos; then pop tos 82 fist store integer fpu register 32-bit integer db [mod 010 r/m] m.si <--- tos 4 16-bit integer df [mod 010 r/m] m.wi <--- tos 3 fistp store integer fpu register, pop 64-bit integer df [mod 111 r/m] m.li <--- tos; then pop tos 6 32-bit integer db [mod 011 r/m] m.si <--- tos; then pop tos 4 16-bit integer df [mod 011 r/m] m.wi <--- tos; then pop tos 3 fstcw store fpu mode control register (9b)d9 [mod 111 r/m] wait memory <--- control mode register 1 2 fnstcw store fpu mode control register d9 [mod 111 r/m] memory <--- control mode register 1 2 fstenv store fpu environment (9b)d9 [mod 110 r/m] wait memory <--- env. registers 1 2 fnstenv store fpu environment d9 [mod 110 r/m] memory <--- env. registers 1 2 fstsw store fpu status register (9b)dd [mod 111 r/m] wait memory <--- status register 1 2 fnstsw store fpu status register dd [mod 111 r/m] memory <--- status register 1 2 fstsw ax store fpu status register to ax (9b)df e0 wait ax <--- status register 1 2 fnstsw ax store fpu status register to ax df e0 ax <--- status register 1 2 fsub floating point subtract top of stack dc [1110 1 n] st(n) <--- st(n) - tos 1/6 80-bit register d8 [1110 0 n] tos <--- tos - st(n 1/6 64-bit real dc [mod 100 r/m] tos <--- tos - m.dr 1/6 32-bit real d8 [mod 100 r/m] tos <--- tos - m.sr 1/6 fsubp floating point subtract, pop de [1110 1 n] st(n) <--- st(n) - tos; then pop tos 1/6 fsubr floating point subtract reverse top of stack dc [1110 0 n] tos <--- st(n) - tos 1/6 80-bit register d8 [1110 1 n] st(n) <--- tos - st(n) 1/6 64-bit real dc [mod 101 r/m] tos <--- m.dr - tos 1/6 32-bit real d8 [mod 101 r/m] tos <--- m.sr - tos 1/6 fsubrp floating point subtract reverse, pop de [1110 0 n] st(n) <--- tos - st(n); then pop tos 1/6 table 8-29. fpu instruction set (continued) fpu instruction opcode operation clock ct single/dbl (or extended) notes
670 amd geode? lx processors data book instruction set 33234h all references to tos and st(n) refer to stack layout prior to execution. values popped off the stack are discarded. a pop from the stack increments the top of stack pointer. a push to the stack decrements the top of stack pointer. issues: 1) for fcos, fsin, fsincos, and fptan, time shown is for the absolute value of tos < /4: ? if fsincos is outside this range, add two time s the fprem clock counts for argument reduction ? if fcos, fsin, or fptan is outside this range, add fprem clock counts for argument reduction 2) these instructions must wait for the fpu pipeline to flus h. cycle count depends on what instructions are in the pipe- line. 3) these instructions are executed in a separate unit and execute in parallel with other multicycle instructions. 4) the amd geode lx processor performs pfrcp and pfrsqrt to 24- bit accuracy in one cycle, so these instructions are unnecessary. they are treated as a move. 5) 5. the following opcodes are reserved: d9d7, d9e2, d9e7, ddfc, ded8, deda, dedc, dedd, dede, and dffc. if a reserved opcode is executed, unpre- dictable results may occur (exceptions are not generated). fisub floating point integer subtract 32-bit integer da [mod 100 r/m] tos <--- tos - m.si 2/7 16-bit integer de [mod 100 r/m] tos <--- tos - m.wi 2/7 fisubr floating point integer subtract reverse 32-bit integer reversed da [mod 101 r/m] tos <--- m.si - tos 2/7 16-bit integer reversed de [mod 101 r/m] tos <--- m.wi - tos 2/7 ftst test top of stack d9 e4 cc set by tos - 0.0 1 fucom unordered compare dd [1110 0 n] cc set by tos - st(n) 1/6 fucomp unordered compare, pop dd [1110 1 n] cc set by tos - st(n); then pop tos 1/6 fucompp unordered compare, pop two elements da e9 cc set by tos - st(i); then pop tos and st(1) 1/6 fwait wait 9b wait for fpu not busy 1+ 2 fxam report class of operand d9 e5 cc <--- class of tos 1 3 fxch exchange register with tos d9 [1100 1 n] tos <--> st(n) exchange 1 3 fxtract extract exponent d9 f4 temp <--- tos; tos <--- exponent (temp); then push significant (temp) onto stack 3/6 fly2x function eval. y log2(x) d9 f1 st(1) <--- st(1) log 2 (tos); then pop tos 204 - 222 fly2xp1 function eval. y log2(x+1) d9 f9 st(1) <--- st(1) log 2 (1+tos); then pop tos 220 4 table 8-29. fpu instruction set (continued) fpu instruction opcode operation clock ct single/dbl (or extended) notes
amd geode? lx processors data book 671 instruction set 33234h table 8-30. amd 3dnow!? technology instruction set amd 3dnow!? instructions opcode/imm8 operation clk cnt notes femms faster exit of the mmx or 3dnow! state 0f0e tag word <--- ffffh (empties the floating point tag word) mmx registers <--- undefined value 11 pavgusb average of unsigned packed 8-bit values 2 mmx register 1 with mmx register2 0f0f [11 mm1 mm2] bf mmx reg1 [byte] <--- rounded up -- - (mmx reg 1 [byte] + mmx reg 2 [byte] + 01h)/2 mmx register with memory64 0f0f [mod mm r/m] bf mmx reg [byte] <--- rounded up --- (mmx reg 1 [byte] + memory [byte] + 01h)/2 pf2id converts packed floating-point operand to packed 32-bit integer 2 mmx register 1 by mmx register2 0f0f [11 mm1 mm2] 1d mmx reg 1 [dword] <--- sat integer --- mmx reg 2 [dword] mmx register 1 by memory64 0f0f [mod mm r/m] 1d mmx reg 1 [dword] <--- sat integer --- memory64 [dword] pf2iw packed floating-point to integer word conversion with sign extend 2 mmx register1 by mmx register2 0f0f [11 mm1 mm2] 1c mmx reg 1 [dword] <--- integer sign extended --- sat --- mmx reg 2 [dword] mmx register by memory64 0f0f [mod mm r/m] 1c mmx reg [dword] <--- integer sign extended --- sat --- memory64 [dword] pfacc floating-point accumulate 2 mmx register 1 with mmx register2 0f0f [11 mm1 mm2] ae mmx reg 1 [low dword] <--- mmx reg 1 [low dword] + mmx reg 1 [high dword] mmx reg 1 [high dword] <--- mmx reg 2 [low dword] + mmx reg 2 [high dword] mmx register 1 with memory64 0f0f [mod mm r/m] ae mmx reg 1 [low dword] <--- mmx reg 1[low dword] + mmx reg 1 [high dword] mmx reg 1 [high dword] <--- memory64 [low dword] + memory64 [high dword] pfadd packed floating-point addition 2 mmx register1 with mmx register2 0f0f [11 mm1 mm2] 9e mmx reg 1[dword] <--- mmx reg 1 [dword] + mmx reg 2 [dword] mmx register1 with memory64 0f0f [mod mm r/m] 9e mmx reg 1 [dword] <--- mmx reg 1 [dword] + memory64 [dword] pfcmpeq packed floating-point comparison, equal to 2 mmx register 1with mmx register 2 0f0f [11 mm1 mm2] b0 mmx reg 1 [dword] <--- ffff ffffh --- if (mmx reg 1 [dword] = mmx reg 2 [dword]) mmx [dword] <--- 0000 0000 h --- if (mmx reg 1 [dword] not + mmx reg 2 [dword]) mmx register with memory64 0f0f [mod mm r/m] b0 mmx reg [dword] <--- ffff ffffh --- if (mmx reg [dword] = memory64 [dword]) mmx reg [dword] <---0000 0000h --- if (mmx reg [dword] not = memory64 [dword]) pfcmpge packed floating-point comparison, greater than or equal to 2 mmx register 1 with mmx register2 0f0f [11 mm1 mm2] 90 mmx reg 1 [dword] <--- ffff ffffh --- if (mmx reg 1 [dword] > mmx reg 2 [dword]) mmx reg 1 [dword] <---0000 0000h --- if (mmx reg 1 [dword] not > mmx reg 2 [dword]) mmx register with memory64 0f0f [mod mm r/m] 90 mmx reg 1 [dword] <--- ffff ffffh --- if (mmx reg 1[dword] > memory64 [dword]) mmx reg [dword] <--- 0000 0000h --- if (mmx reg [dword] not > memory64 [dword]) pfcmpgt packed floating- point comparison, greater than 2 mmx register1 with mmx register2 0f0f [11 mm1 mm2] a0 mmx reg 1 [dword] <--- ffff ffffh --- if (mmx reg 1 [dword] > mmx reg 2 [dword]) mmx reg 1 [dword] <---0000 0000h --- if (mmx reg 1 [dword] not > mmx reg 2 [dword]) mmx register with memory64 0f0f [mod mm r/m] a0 mmx reg [dword] <---ffff ffffh --- if (mmx reg [dword] > memory64 [dword]) mmx reg [dword] <--- 0000 0000h --- if (mmx reg [dword] not > memory64 [dword])
672 amd geode? lx processors data book instruction set 33234h pfmax packed floating-point maximum 2 mmx register1 with mmx register2 0f0f [11 mm1 mm2] a4 mmx reg 1[dword] <--- mmx reg 1 [dword] --- if (mmx reg 1 [dword] > mmx reg 2 [dword]) mmx reg 1 [dword] <--- mmx reg 2 [dword] --- if (mmx reg 1 [dword] not > mmx reg 2 [dword]) mmx register with memory64 0f0f [mod mm r/m] a4 mmx reg [dword] <--- mmx reg [dword] --- if (mmx reg [dword] > memory64 [dword]) mmx reg [dword] <--- memory [dword --- if (mmx reg [dword] not > memory64 [dword]) pfmin packed floating - point minimum 2 mmx register 1 with mmx register2 0f0f [11 mm1 mm2] 94 mmx reg 1 [dword] <--- mmx reg 1 [dword] --- if (mmx reg 1 [dword] < mmx reg 2 [dword]) mmx reg 1 [dword] <--- mmx reg 1 [dword] --- if (mmx reg 1 [dword] not < mmx reg 2 [dword]) mmx register1 with mwnory64 0f0f [mod mm r/m] 94 mmx reg [dword] <--- mmx reg [dword] --- if (mmx reg [dword] < memory64 [dword]) mmx reg [dword] <--- memory64 [dword] --- if (mmx reg [dword] not < memory64 [dword]) pfmul packed floating-point multiplication 2 mmx register 1 with mmx register 2 0f0f [11 mm1 mm2] b4 mmx reg 1 [dword] <--- sat --- mmx reg 1 [dword] * mmx reg 2 [dword] mmx register with memory64 0f0f [mod mm 2] b4 mmx reg [dword] <--- sat --- mmx reg [dword] * memory64 [dword] pfnacc packed floating-point negative accumulate 2 mmx register1 with mmx register2 0f0f [11 mm1 mm2] 8a mmx reg 1 [low dword] <--- (mmx reg 1 [low dword] - mmx reg 1 [high dword]) mmx reg 1 [high dword] <--- (mmx reg 2 [low dword] - mmx reg 2 [high dword]) mmx register with memory64 0f0f [mod mm r/m] 8a mmx reg [low dword] <--- (mmx reg [low dword] - mmx reg [high dword]) mmx reg [high dword] <--- (memory64 [low dword] - memory64 [high dword]) pfpnacc packed floating-point mixed positive-negative accumulate 2 mmx register1 with mmx register2 0f0f [11 mm1 mm2] 8e mmx reg 1 [low dword] <--- (mmx reg 1 [low dword] - mmx reg 1 [high dword]) mmx reg 1 [high dword] <--- (mmx reg 2 [low dword] + mmx reg 2 [high dword]) mmx register with memory64 0f0f [mod mm r/m] 8e mmx reg [low dword] <--- (mmx reg [low dword] - mmx reg [low dword]) mmx reg [high dword] <--- (memory64 [low dword] - memory64 [high dword]) pfrcp floating-point reciprocal approximation 21 mmx register1 with mmx register2 0f0f [11 mm1 mm2] 96 mmx reg 1 [low dword] <--- sat --- reciprocal --- mmx reg 2 [low dword] mmx reg 1 [high dword] <--- sat --- reciprocal --- mmx reg 2 [low dword] mmx register with memory64 0f0f [mod mm r/m] 96 mmx reg [low dword] <--- sat --- reciprocal --- memory64 [low dword] mmx reg [high dword] <--- sat --- reciprocal --- memory64 [low dword] pfrcpv floating-point reciprocal vector 23 mmx register1 with mmx register 0f0f [11 mm1 mm2] 86 mmx reg 1 [low dword] <---sat --- reciprocal --- mmx reg 2 [low dword] mmx reg 1 [high dword] <--- sat --- reciprocal mmx reg 2 [high dword] mmx register with memory64 0f0f [mod mm r/m] 86 mmx reg [low dword] <---sat --- reciprocal value - memory64 [low dword] mmx reg [high dword] <--- sat --- reciprocal value - memory64 [high dword] pfrcpit1 packed floating-point reciprocal, first iteration step 11, 2 mmx register1 with mmx register 2 0f0f [11 mm1 mm2] a6 mmx reg 1 [dword] <--- move --- mmx reg 2 [dword] mmx register with memory64 0f0f [mod mm r/m] a6 mmx reg [dword] <-- move --- memory64 [dword] pfrcpit2 packed floating-point reciprocal/reciprocal square root, second iteration step 11, 2 mmx register 1 with mmx register 2 0fdf [11 mm1 mm2] b6 mmx reg 1 [dword] <--- move --- mmx reg 2 [dword] mmx register with memory64 0fdf [mod mm r/m] b6 mmx reg [dword] <--- move --- memory64 [dword] table 8-30. amd 3dnow!? technology instruction set (continued) amd 3dnow!? instructions opcode/imm8 operation clk cnt notes
amd geode? lx processors data book 673 instruction set 33234h 1) these instructions must wait for the fpu pipeline to flus h. cycle count depends on what instructions are in the pipe- line. 2) the amd geode lx processor performs pfrcp and pfrsqrt to 24- bit accuracy in one cycle, so these instructions are unnecessary. they are treated as a move. 3) non-standard amd 3dnow! instruction. see section 8.4.1 on page 674 for details. pfsrqit1 packed floating-point reciprocal square root, first iteration step 11, 2 mmx register1 with mmx register 2 0f0f [11 mm1 mm2] a7 mmx reg 1 [dword] <--- move --- mmx reg 2 [dword] mmx register with memory64 0f0f [mod mm r/m] a7 mmx reg [dword] <--- move --- memory64 [dword] pfrsqrt floating-point reciprocal square root 2 mmx register 1 by mmx register 2 0f0f [11 mm1 mm2] 97 mmx reg.1 [low dword] <--- reciprocal --- square root --- mmx reg 2 [low dword] mmx reg 2 [high dword] <--- reciprocal --- square root --- mmx reg 2 [low dword] mmx register by memory64 0f0f [mod mm r/m] 97 mmx reg [low dword] <--- reciprocal --- square root --- memory64 [low dword] mmx reg [high word] <--- reciprocal --- square root --- memory64 [low dword] pfrsqrtv floating-point reciprocal square root vector 23 mmx register1 with mmx register2 0f0f [11 mm1 mm2] 87 mmx reg 1 [low dword] <--- sat --- reciprocal --- square root --- mmx reg 2 [low dword] mmx reg 1 [high word] <--- sat --- reciprocal --- square root --- mmx reg 2 [high dword] mmx register with memory64 0f0f [mod mm r/m] 87 mmx reg [low dword] <---sat --- reciprocal --- square root --- memory64 [low dword] mmx reg [high dword] <--- sat --- reciprocal --- square root --- memory64 [high dword] pfsub packed floating- point subtraction 2 mmx register1 with mmx register2 0f0f [11 mm1 mm2] 9a mmx reg 1 [dword] <--- (mmx reg1 [dword] - mmx reg 2 [dword]) mmx register with mmx memory64 0f0f [mod mm r/m 9a mmx reg [dword] <--- (mmx reg [dword] - memory64 [dword]) pfsubr packed floating-point reverse subtraction 2 mmx register1 with mmx register2 0f0f [11mm1 mm2] aa mmx reg 1 [dword] <---(mmx reg 2 [dword] - mmx reg [dword]) mmx register with memory64 0f0f [mod mm r/m] aa mmx reg [dword] <--- (memory64 [dword] - mmx reg [dword]) pi2fd packed 32-bit integer to floating-point conversion 2 mmx register1 by mmx regester2 0f0f [11 mm1 mm2] 0d mmx reg 1 [dword] <--- trun --- float --- mmx reg 2 [dword] mmx register by memory64 0f0f [mod mm r/m] 0d mmx reg [dword] <--- trun --- float --- memory64 [dword] pif2w packed integer word to floating-point conversion 2 mmx register1 by mmx register2 0f0f [11 mm1 mm2] 0c mmx reg 1 [low dword] <--- float --- mmx reg 2 [low word (low dword)] mmx reg 1 [high dword] <--- float --- mmx reg 2 [low word (high dword)] mmx register by memory64 0f0f [mod mm r/m] 0c mmx reg [low dword] <--- float --- memory64 [low word (low dword)] mmx reg [high dword] <--- float --- memory64 [low dword (high dword)] pmulhrw multiply signed packed 16-bit value with rounding and store the high 16 bits 2 mmx register1 with mmx register2 0f0f [11 mm1 mm2 b7 mmx reg 1 [word] <--- (mmx reg 1 [word] * mmx reg 2 [word]) + 8000h mmx register with memory64 0f0f [mod mm r/m b7 mmx reg [word] <--- (mmx reg [word] * memory64 [word]) + 8000h prefetch/prefetchw prefetch cache line into l1 data cache (dcache) memory 8 0f0d pswapd packed swap doubleword 1 mmx register1 by mmx register2 0f0f [11 mm1 mm2] bb mmx reg 1 [low dword] <--- mmx reg 2 [high dword] mmx reg 1 [high dword] <--- mmx reg 2 [low dword] mmx register by memory64 0f0f [mod mm r/m] bb mmx reg [low dword] <--- memory64 [high dword] mmx reg [high dword] <--- memory64 [low dword] table 8-30. amd 3dnow!? technology instruction set (continued) amd 3dnow!? instructions opcode/imm8 operation clk cnt notes
674 amd geode? lx processors data book instruction set 33234h 8.4.1 non-standard amd 3dnow!? technology instructions 8.4.1.1 pfrcpv - floating-point reciprocal approximation operation dest[31:0] <= reciprocal(src[31:0]); dest[63:32] <= reci procal(src[63:32]); description pfrcpv performs the same operation as the pfrcp instruction except that pfrcpv operates on both halves of its oper- ands, while pfrcp operates on only bits [31:0] of its operand. flags affected none. exceptions #gp(0) if a memory operand is illegal and not in ss. #ss(0) if memory operand is illegal and in ss. #pf(code) page fault. #ac unaligned access. #ud illegal opcode. notes this instruction is enabled by the inv_3dnow_enabl e bit (bit 1) of the id_config msr (msr 00001250h). 8.4.1.2 pfrsqrtv - fl oating-point reciprocal square root approximation operation description pfrsqrtv performs the same operation as the pfrsqrt in struction except that pfrsqrtv operates on both halves of its operands, while pfsqrt operates on only bits [31:0] of its operand. flags affected none. exceptions #gp(0) if a memory operand is illegal and not in ss. #ss(0) if memory operand is illegal and in ss. #pf(code) page fault. #ac unaligned access. #ud illegal opcode. notes this instruction is enabled by the inv_3dnow_enabl e bit (bit 1) of the id_config msr (msr 00001250h). opcode instruction c locks description 0f 0f / 86 pfrcpv xr,xr/m64 2 approximate reciprocal opcode instruction c locks description 0f 0f / 87 pfrsqrtv xr,xr/m64 2 approximate reciprocal square root dest[31:0] <= reciproc al_square_root(src[31:0]); dest[63:32] <= reciproc al_square_root(src[63:32]);
amd geode? lx processors data book 675 9 package specifications 33234h 9.0 package specifications 9.1 physical dimensions the figures in this section provide the mechanical package outline for the bgu481 (481-terminal ball grid array cavity up) figure 9-1. bgu481 top/side view/dimensions
676 amd geode? lx processors data book package specifications 33234h figure 9-2. bgu481 bottom view/dimensions
a amd geode? lx processors data book 677 appendix a: support documentation 33234h appendix a support documentation a.1 order information ordering information for the amd geode? lx processors is c ontained in this section. the ordering part number (opn) is formed by a combination of elements. an example of the opn is shown in figure a-1. valid opn combinations are pro- vided in table a-1 on page 678. figure a-1. amd geode? lx processors opn example alx c ee t j c v 800 family/architecture: alx = amd geode? lx processor family opn (note) note: spaces are added to the ordering number shown above for viewing clarity only. c display type: v = crt, tft, and vop performance indicator: package type: ee = bgu (te-pbga) c = 0c to 85c commercial d = 0c to 85c commercial lead (pb) free h = 0c to 80c commercial lead (pb) free f = -40c to 85c industrial lead (pb) free 2 = 128k l2 cache, no eeprom c = 128k l2 cache, with eeprom j = 400 mhz memory, geodelink? architecture (500/600 mhz cpu) h = 333 mhz memory, geodelink? architecture (433 mhz cpu) k = 266 mhz memory, geodelink? architecture (366 mhz cpu) t = 1.20v x = 1.25v y = 1.40v 900 operates at 600 mhz 800 operates at 500 mhz 700 operates at 433 mhz 600 operates at 366 mhz c 3w d 4w g 6w case temperature: cache/eeprom indicator: system bus speed: operating voltage: performance indicator: maximum thermal design power (mtdp):
678 amd geode? lx processors data book appendix a: order information 33234h table a-1. valid opn combinations family architecture mtdp performance indicator package type operating voltag e system bus speed eeprom indicator display type case temperature/ solder type (note) alx g 900 ee y j 2 v h alx d 800 ee x j 2 v c d f cc d alx c 700 ee t h 2 v c d cc d alx c 600 ee t k 2 v d note: jc = 3.7 c/w consult your local amd sales office to confirm availability of specific valid combinations and to check on newly released combi nations possibly not listed.
amd geode? lx processors data book 679 appendix a: data book revision history 33234h a.2 data book revision history this document is a report of the revi sion/creation process of the data book fo r the amd geode? lx processors. any revi- sion (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table(s) below. table a-2. revision history revision # (pdf date) revisions / comments 0.1 (april 2004) advance information. 0.5 (september 2004) added data registers descriptions, el ectrical specifications, and package specification sections. still preliminary and in the review/proofing process. 0.9 (january 2005) added functional descriptions and other corrections. a (may 2005) engineering edits. b (october 2005) majority of edits to electrical section. c (april 2006) engineering edits. d (june 2006) engineering edits. e (november 2006) added lx 900@1.5w processor va lues and other clarification edits/corrections. f (may 2007) added industrial temperature values and other minor edits/corrections. g (may 2008) minor edits/corrections. see table a-3 for details. h (february 2009) added lx 600@0.7w parameters. table a-3. edits to current revision section revision section 1.0 "overview" ? section 1.1 "general description" on page 11: ? updated link to amd embedded developer support web site. ? section 1.2 "features" on page 12: ? added lx 600@0.7w to power management bullet and footnote. section 6.2 "geodelink? memory controller regis- ter descriptions" ? section 6.2.2.11 "feature enables (mc_cf1017_data)" on page 231: ? slightly modified wr2dat bit description. section 7.0 "electrical specifications" ? table 7-2 "operating conditions" on page 598: ? added lx 600@0.7w and ddr2 values. ? table 7-3 "amd geode lx 900@1.5w proc essor dc currents" on page 600, table 7-4 "amd geode lx 800@0.9w processor dc currents" on page 601, and table 7-5 "amd geode lx 700@0.8w processor dc currents" on page 602: ? added i memddr2on parameter and values. ? table 7-6 "amd geode lx 600@0.7w processor dc currents" on page 603: ? new table. section a.1 "order infor- mation" ? figure a-1 "amd geode? lx processors opn example" on page 677: ? added ?k? to system bus speed and ?600? to performance indicator. ? table a-1 "valid opn combinations" on page 678: ? added lx 600@0.7w opn.
one amd place ? p.o. box 3453 ? sunnyvale, ca 94088-3453 usa ? tel: 408-749-4000 or 800-538-8450 ? twx: 910-339-9280 ? telex: 3 4-6306 www.amd.com

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